已合并
refactor: unify transto5hd implementations #5146
leozjr创建于 21 天前
refactor: unify transto5hd implementations #5146
已合并
从已删除 :fix/transto5hd-inline合入到cann/asc-devkitmaster
共 14 个文件变更+590-179
| @@ -1373,6 +1373,7 @@ | |||
| 1373 | - [asc_mmad(废弃)](SIMD-API/c_api/deprecated_interface/asc_mmad_deprecated.md) | 1373 | - [asc_mmad(废弃)](SIMD-API/c_api/deprecated_interface/asc_mmad_deprecated.md) |
| 1374 | - [asc_mmad_mx(废弃)](SIMD-API/c_api/deprecated_interface/asc_mmad_mx_deprecated.md) | 1374 | - [asc_mmad_mx(废弃)](SIMD-API/c_api/deprecated_interface/asc_mmad_mx_deprecated.md) |
| 1375 | - [asc_mmad_sparse(废弃)](SIMD-API/c_api/deprecated_interface/asc_mmad_sparse_deprecated.md) | 1375 | - [asc_mmad_sparse(废弃)](SIMD-API/c_api/deprecated_interface/asc_mmad_sparse_deprecated.md) |
| 1376 | + - [asc_transto5hd_sync(废弃)](SIMD-API/c_api/deprecated_interface/asc_transto5hd_sync_deprecated.md) | ||
| 1376 | 1377 | ||
| 1377 | - [Tensor API](SIMD-API/tensor_api/tensor_api.md) | 1378 | - [Tensor API](SIMD-API/tensor_api/tensor_api.md) |
| 1378 | - [Tensor API列表](SIMD-API/tensor_api/tensor_api_list.md) | 1379 | - [Tensor API列表](SIMD-API/tensor_api/tensor_api_list.md) |
| @@ -788,3 +788,4 @@ C API文档按最细粒度公共头文件归类。除试验接口外,整体使 | |||
| 788 | |[asc_mmad(废弃)](deprecated_interface/asc_mmad_deprecated.md)|矩阵乘加计算接口。|`c_api/cube_compute/cube_compute.h`| | 788 | |[asc_mmad(废弃)](deprecated_interface/asc_mmad_deprecated.md)|矩阵乘加计算接口。|`c_api/cube_compute/cube_compute.h`| |
| 789 | |[asc_mmad_mx(废弃)](deprecated_interface/asc_mmad_mx_deprecated.md)|带有量化系数的矩阵乘加计算接口。|`c_api/cube_compute/cube_compute.h`| | 789 | |[asc_mmad_mx(废弃)](deprecated_interface/asc_mmad_mx_deprecated.md)|带有量化系数的矩阵乘加计算接口。|`c_api/cube_compute/cube_compute.h`| |
| 790 | |[asc_mmad_sparse(废弃)](deprecated_interface/asc_mmad_sparse_deprecated.md)|稀疏矩阵乘加计算接口。|`c_api/cube_compute/cube_compute.h`| | 790 | |[asc_mmad_sparse(废弃)](deprecated_interface/asc_mmad_sparse_deprecated.md)|稀疏矩阵乘加计算接口。|`c_api/cube_compute/cube_compute.h`| |
| 791 | +| [asc_transto5hd_sync(废弃)](deprecated_interface/asc_transto5hd_sync_deprecated.md) | 数据格式转换接口。 | | ||
| @@ -0,0 +1,175 @@ | |||
| 1 | +# asc_transto5hd_sync(废弃) | ||
| 2 | + | ||
| 3 | +## 产品支持情况 | ||
| 4 | + | ||
| 5 | +<!-- npu="950" id1 --> | ||
| 6 | +- Ascend 950PR/Ascend 950DT:支持 | ||
| 7 | +<!-- end id1 --> | ||
| 8 | +<!-- npu="A3" id2 --> | ||
| 9 | +- Atlas A3 训练系列产品/Atlas A3 推理系列产品:支持 | ||
| 10 | +<!-- end id2 --> | ||
| 11 | +<!-- npu="910b" id3 --> | ||
| 12 | +- Atlas A2 训练系列产品/Atlas A2 推理系列产品:支持 | ||
| 13 | +<!-- end id3 --> | ||
| 14 | +<!-- npu="310b" id4 --> | ||
| 15 | +- Atlas 200I/500 A2 推理产品:不支持 | ||
| 16 | +<!-- end id4 --> | ||
| 17 | +<!-- npu="310p" id5 --> | ||
| 18 | +- Atlas 推理系列产品AI Core:不支持 | ||
| 19 | +<!-- end id5 --> | ||
| 20 | +<!-- npu="310p" id6 --> | ||
| 21 | +- Atlas 推理系列产品Vector Core:不支持 | ||
| 22 | +<!-- end id6 --> | ||
| 23 | +<!-- npu="910" id7 --> | ||
| 24 | +- Atlas 训练系列产品:不支持 | ||
| 25 | +<!-- end id7 --> | ||
| 26 | + | ||
| 27 | +## 功能说明 | ||
| 28 | + | ||
| 29 | +**`asc_transto5hd_b8_sync`、`asc_transto5hd_b16_sync`和`asc_transto5hd_b32_sync`接口已废弃。请使用[asc_transto5hd](../vector_compute/vector_permute_sel/asc_transto5hd.md)接口和[asc_sync](../sync/asc_sync.md)接口替代。** | ||
| 30 | + | ||
| 31 | +数据格式转换,一般用于将NCHW格式转换成NC1HWC0格式。特别的,也可以用于二维矩阵数据块的转置。本接口单次Repeat内可处理512Byte的数据(16个DataBlock),根据数据类型不同,支持不同shape的矩阵转置(比如数据类型为half时,单次Repeat可完成16*16大小的矩阵转置),同时还可以支持多次Repeat操作。 | ||
| 32 | + | ||
| 33 | +单次repeat内转换规则如下: | ||
| 34 | + | ||
| 35 | +- 当输入数据类型位宽为16位时,每个DataBlock中包含16个数,指令内部会循环16次,每次循环都会分别从指定的16个DataBlock中的对应位置取值,组成一个新的DataBlock单元放入目的地址中。如下图所示,图中的srcList[0]-srcList[15]代表源操作数的16个DataBlock。 | ||
| 36 | + | ||
| 37 | +- 当数据类型位宽为32位时,每个DataBlock包含8个数,指令内部会循环8次,每次循环都会分别从指定的16个DataBlock中的对应位置取值,组成2个新的DataBlock放入目的地址中。如下图所示: | ||
| 38 | + | ||
| 39 | +- 当数据类型位宽为8位时,每个DataBlock包含32个数,指令内部会循环16次,每次循环都会分别从指定的16个DataBlock中的对应位置取值,组成半个DataBlock放入目的地址中,读取和存放是在DataBlock的高半部还是低半部由参数srcHighHalf和dstHighHalf决定。如下图所示: | ||
| 40 | + | ||
| 41 | +基于以上的转换规则,使用该接口进行NC1HWC0格式转换或者矩阵转置。NC1HWC0格式转换相对复杂,这里给出其具体的转换方法: | ||
| 42 | + | ||
| 43 | +NCHW格式转换成NC1HWC0格式时,如果是数据类型的位宽为32位或者16位,则C0=16;如果数据类型的位宽为8位,则C0=32。下图以C0=16为例进行介绍: | ||
| 44 | + | ||
| 45 | +## 函数原型 | ||
| 46 | + | ||
| 47 | +- 同步计算 | ||
| 48 | +```cpp | ||
| 49 | +__aicore__ inline void asc_transto5hd_b32_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, | ||
| 50 | + uint16_t dst_stride, uint16_t src_stride) | ||
| 51 | +__aicore__ inline void asc_transto5hd_b16_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, | ||
| 52 | + uint16_t dst_stride, uint16_t src_stride) | ||
| 53 | +__aicore__ inline void asc_transto5hd_b8_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, | ||
| 54 | + uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, bool src_high_half) | ||
| 55 | +``` | ||
| 56 | + | ||
| 57 | +## 参数说明 | ||
| 58 | + | ||
| 59 | +**表1** 参数说明 | ||
| 60 | + | ||
| 61 | +|参数名|输入/输出|描述| | ||
| 62 | +| ------------ | ------------ | ------------ | | ||
| 63 | +|dst|输出|目的地址寄存器。| | ||
| 64 | +|src|输入|源地址寄存器。| | ||
| 65 | +|repeat|输入|重复迭代次数, repeat∈[0,255]。<br>注意事项:<br>•当repeat为1时,目的操作数/源操作数的有效起始位置为dst/src序列输入的起始位置加上dst_stride/src_stride。如果要让目的操作数/源操作数的有效起始位置为dst/src序列输入的起始位置,需要将dst_stride/src_stride置为0。<br>•当repeat大于1时,第一次repeat中目的操作数/源操作数的有效起始位置为dst/src序列输入的起始位置,第二次会加上dst_stride/src_stride。以此类推。| | ||
| 66 | +|dst_stride|输入|相邻迭代间,目的操作数相同DataBlock地址Stride,单位:DataBlock。<br>相邻迭代间相同DataBlock的地址步长参数的详细说明请参考[repeatStride](../general_description_and_constraints.md#repeatStride)。| | ||
| 67 | +|src_stride|输入|相邻迭代间,源操作数相同DataBlock地址Stride,单位:DataBlock。<br>相邻迭代间相同DataBlock的地址步长参数的详细说明请参考[repeatStride](../general_description_and_constraints.md#repeatStride)。| | ||
| 68 | +|dst_high_half|输入|指定每个dst地址中的数据存储到DataBlock的高半部还是低半部,该配置只配置int8_t/uint8_t的数据类型。<br>支持的数据类型为bool,有以下两种取值:<br>• true:表示存储于DataBlock的高半部。<br>• false:表示存储于DataBlock的低半部。| | ||
| 69 | +|src_high_half|输入|指定每个src地址中的数据存储到DataBlock的高半部还是低半部,该配置只配置int8_t/uint8_t的数据类型。<br>支持的数据类型为bool,有以下两种取值:<br>• true:表示存储于DataBlock的高半部。<br>•false:表示存储于DataBlock的低半部。| | ||
| 70 | + | ||
| 71 | +## 返回值说明 | ||
| 72 | + | ||
| 73 | +无 | ||
| 74 | + | ||
| 75 | +## 流水类型 | ||
| 76 | + | ||
| 77 | +PIPE_V | ||
| 78 | + | ||
| 79 | +## 约束说明 | ||
| 80 | + | ||
| 81 | +- 操作数地址对齐约束请参考[存储单元说明](../general_description_and_constraints.md#存储单元说明)。 | ||
| 82 | +- 操作数地址重叠约束请参考[通用地址重叠约束](../../general_description_and_constraints.md#通用地址重叠约束)。 | ||
| 83 | +- 进行NCHW格式到NC1HWC0格式的转换时,一般用法是将src/dst中的每个元素配置为每个HW平面的起点。 | ||
| 84 | +- 为了性能更优,数据类型位宽为8位时建议先固定dst_high_half/src_high_half,再HW方向Repeat后,再改变dst_high_half/src_high_half。 | ||
| 85 | + | ||
| 86 | +## 调用示例 | ||
| 87 | + | ||
| 88 | +```cpp | ||
| 89 | +// 示例一: | ||
| 90 | +constexpr uint64_t total_length = 256; // total_length指参与计算的数据长度 | ||
| 91 | +__ubuf__ half src[total_length]; | ||
| 92 | +__ubuf__ half dst[total_length]; | ||
| 93 | +const uint32_t STEP = 16; | ||
| 94 | +// src_list和dst_list是16个DataBlock地址的数组 | ||
| 95 | +__ubuf__ half* src_list[16] = { | ||
| 96 | + (__ubuf__ half*)(src + 0 * STEP), | ||
| 97 | + (__ubuf__ half*)(src + 1 * STEP), | ||
| 98 | + (__ubuf__ half*)(src + 2 * STEP), | ||
| 99 | + (__ubuf__ half*)(src + 3 * STEP), | ||
| 100 | + (__ubuf__ half*)(src + 4 * STEP), | ||
| 101 | + (__ubuf__ half*)(src + 5 * STEP), | ||
| 102 | + (__ubuf__ half*)(src + 6 * STEP), | ||
| 103 | + (__ubuf__ half*)(src + 7 * STEP), | ||
| 104 | + (__ubuf__ half*)(src + 8 * STEP), | ||
| 105 | + (__ubuf__ half*)(src + 9 * STEP), | ||
| 106 | + (__ubuf__ half*)(src + 10 * STEP), | ||
| 107 | + (__ubuf__ half*)(src + 11 * STEP), | ||
| 108 | + (__ubuf__ half*)(src + 12 * STEP), | ||
| 109 | + (__ubuf__ half*)(src + 13 * STEP), | ||
| 110 | + (__ubuf__ half*)(src + 14 * STEP), | ||
| 111 | + (__ubuf__ half*)(src + 15 * STEP) | ||
| 112 | +}; | ||
| 113 | +__ubuf__ half* dst_list[16] = { | ||
| 114 | + (__ubuf__ half*)(dst + 0 * STEP), | ||
| 115 | + (__ubuf__ half*)(dst + 1 * STEP), | ||
| 116 | + (__ubuf__ half*)(dst + 2 * STEP), | ||
| 117 | + (__ubuf__ half*)(dst + 3 * STEP), | ||
| 118 | + (__ubuf__ half*)(dst + 4 * STEP), | ||
| 119 | + (__ubuf__ half*)(dst + 5 * STEP), | ||
| 120 | + (__ubuf__ half*)(dst + 6 * STEP), | ||
| 121 | + (__ubuf__ half*)(dst + 7 * STEP), | ||
| 122 | + (__ubuf__ half*)(dst + 8 * STEP), | ||
| 123 | + (__ubuf__ half*)(dst + 9 * STEP), | ||
| 124 | + (__ubuf__ half*)(dst + 10 * STEP), | ||
| 125 | + (__ubuf__ half*)(dst + 11 * STEP), | ||
| 126 | + (__ubuf__ half*)(dst + 12 * STEP), | ||
| 127 | + (__ubuf__ half*)(dst + 13 * STEP), | ||
| 128 | + (__ubuf__ half*)(dst + 14 * STEP), | ||
| 129 | + (__ubuf__ half*)(dst + 15 * STEP) | ||
| 130 | +}; | ||
| 131 | +const int32_t VA_REG_ARRAY_LEN = 8; | ||
| 132 | +uint8_t repeat = 1; | ||
| 133 | +uint16_t dst_stride = 0; | ||
| 134 | +uint16_t src_stride = 0; | ||
| 135 | + | ||
| 136 | +// asc_set_va_reg接口要求前8个和后8个地址序列与地址寄存器分别关联 | ||
| 137 | +asc_set_va_reg(VA0, dst_list); | ||
| 138 | +asc_set_va_reg(VA1, dst_list + VA_REG_ARRAY_LEN); | ||
| 139 | +asc_set_va_reg(VA2, src_list); | ||
| 140 | +asc_set_va_reg(VA3, src_list + VA_REG_ARRAY_LEN); | ||
| 141 | + | ||
| 142 | +asc_transto5hd_b16(VA0, VA2, repeat, dst_stride, src_stride); | ||
| 143 | + | ||
| 144 | +// 示例二: | ||
| 145 | +constexpr uint64_t total_length = 2 * 32 * 16 * 16; // total_length指参与计算的数据长度 | ||
| 146 | +__ubuf__ half src[total_length]; | ||
| 147 | +__ubuf__ half dst[total_length]; | ||
| 148 | +const uint32_t DST_STEP = 16; | ||
| 149 | +const uint32_t SRC_STEP = 16 * 16; | ||
| 150 | +const uint32_t OFFSET = 16 * 16 * 16; | ||
| 151 | +const int32_t VA_REG_ARRAY_LEN = 8; | ||
| 152 | +uint8_t repeat = 16; | ||
| 153 | +uint16_t dst_stride = 16; | ||
| 154 | +uint16_t src_stride = 1; | ||
| 155 | + | ||
| 156 | +// src_list和dst_list定义在循环外部 | ||
| 157 | +__ubuf__ half* src_list[16]; | ||
| 158 | +__ubuf__ half* dst_list[16]; | ||
| 159 | + | ||
| 160 | +for (int j = 0; j < 4; ++j) { | ||
| 161 | + // 在循环内更新地址列表 | ||
| 162 | + for (int i = 0; i < 16; ++i) { | ||
| 163 | + src_list[i] = (__ubuf__ half*)(src + OFFSET * j + i * SRC_STEP); | ||
| 164 | + dst_list[i] = (__ubuf__ half*)(dst + OFFSET * j + i * DST_STEP); | ||
| 165 | + } | ||
| 166 | + | ||
| 167 | + // 每次循环都要设置寄存器并执行转换 | ||
| 168 | + asc_set_va_reg(VA0, dst_list); | ||
| 169 | + asc_set_va_reg(VA1, dst_list + VA_REG_ARRAY_LEN); | ||
| 170 | + asc_set_va_reg(VA2, src_list); | ||
| 171 | + asc_set_va_reg(VA3, src_list + VA_REG_ARRAY_LEN); | ||
| 172 | + | ||
| 173 | + asc_transto5hd_b16(VA0, VA2, repeat, dst_stride, src_stride); | ||
| 174 | +} | ||
| 175 | +``` | ||
| @@ -52,16 +52,6 @@ __aicore__ inline void asc_transto5hd_b8(ub_addr8_t dst, ub_addr8_t src, uint8_t | |||
| 52 | uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, bool src_high_half) | 52 | uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, bool src_high_half) |
| 53 | ``` | 53 | ``` |
| 54 | 54 | ||
| 55 | -- 同步计算 | ||
| 56 | -```cpp | ||
| 57 | -__aicore__ inline void asc_transto5hd_b32_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, | ||
| 58 | - uint16_t dst_stride, uint16_t src_stride) | ||
| 59 | -__aicore__ inline void asc_transto5hd_b16_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, | ||
| 60 | - uint16_t dst_stride, uint16_t src_stride) | ||
| 61 | -__aicore__ inline void asc_transto5hd_b8_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, | ||
| 62 | - uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, bool src_high_half) | ||
| 63 | -``` | ||
| 64 | - | ||
| 65 | ## 参数说明 | 55 | ## 参数说明 |
| 66 | 56 | ||
| 67 | **表1** 参数说明 | 57 | **表1** 参数说明 |
| @@ -88,6 +78,8 @@ PIPE_V | |||
| 88 | 78 | ||
| 89 | - 操作数地址对齐约束请参考[存储单元说明](../../general_description_and_constraints.md#存储单元说明)。 | 79 | - 操作数地址对齐约束请参考[存储单元说明](../../general_description_and_constraints.md#存储单元说明)。 |
| 90 | - 操作数地址重叠约束请参考[通用地址重叠约束](../../general_description_and_constraints.md#通用地址重叠约束)。 | 80 | - 操作数地址重叠约束请参考[通用地址重叠约束](../../general_description_and_constraints.md#通用地址重叠约束)。 |
| 81 | +- `dst`和`src`不能传入相同的地址寄存器起始位置,即目的地址寄存器对和源地址寄存器对不能重叠。 | ||
| 82 | +- 为获得更优性能,建议`dst`、`src`、`dst_high_half`和`src_high_half`传入编译期常量,例如直接传入VA0、VA2、true或false,或传入由这些常量初始化的局部变量。`dst`和`src`仅支持VA0、VA2、VA4、VA6,且不能相同,配置方式请参考[asc_set_va_reg](./asc_set_va_reg.md);每个地址寄存器存储8个地址,接口会将传入的起始寄存器与相邻寄存器组成一组,处理16个地址。传入运行时变量时,编译器会保留地址寄存器或布尔参数的分支判断,影响性能。 | ||
| 91 | - 进行NCHW格式到NC1HWC0格式的转换时,一般用法是将src/dst中的每个元素配置为每个HW平面的起点。 | 83 | - 进行NCHW格式到NC1HWC0格式的转换时,一般用法是将src/dst中的每个元素配置为每个HW平面的起点。 |
| 92 | - 为了性能更优,数据类型位宽为8位时建议先固定dst_high_half/src_high_half,再HW方向Repeat后,再改变dst_high_half/src_high_half。 | 84 | - 为了性能更优,数据类型位宽为8位时建议先固定dst_high_half/src_high_half,再HW方向Repeat后,再改变dst_high_half/src_high_half。 |
| 93 | 85 | ||
| @@ -480,3 +480,6 @@ | |||
| 480 | 480 | ||
| 481 | 使用`uint8_t unit_flag`入参的`asc_mmad_sparse()`接口已废弃,请使用[asc_mmad_sparse](../SIMD-API/c_api/cube_compute/asc_mmad_sparse.md)接口。`asc_mmad_sparse_sync()`接口已废弃,请使用[asc_mmad_sparse](../SIMD-API/c_api/cube_compute/asc_mmad_sparse.md)接口和[asc_sync](../SIMD-API/c_api/sync/asc_sync.md)接口。 | 481 | 使用`uint8_t unit_flag`入参的`asc_mmad_sparse()`接口已废弃,请使用[asc_mmad_sparse](../SIMD-API/c_api/cube_compute/asc_mmad_sparse.md)接口。`asc_mmad_sparse_sync()`接口已废弃,请使用[asc_mmad_sparse](../SIMD-API/c_api/cube_compute/asc_mmad_sparse.md)接口和[asc_sync](../SIMD-API/c_api/sync/asc_sync.md)接口。 |
| 482 | <!-- end id10 --> | 482 | <!-- end id10 --> |
| 483 | +- [asc_transto5hd_sync(废弃)](../SIMD-API/c_api/deprecated_interface/asc_transto5hd_sync_deprecated.md)接口 | ||
| 484 | + | ||
| 485 | + 此接口已废弃。请使用[asc_transto5hd](../SIMD-API/c_api/vector_compute/vector_permute_sel/asc_transto5hd.md)接口和[asc_sync](../SIMD-API/c_api/sync/asc_sync.md)接口。 | ||
| @@ -5308,35 +5308,50 @@ __aicore__ inline void asc_transpose_sync(__ubuf__ uint16_t* dst, __ubuf__ uint1 | |||
| 5308 | asc_transpose_sync_impl(dst, src); | 5308 | asc_transpose_sync_impl(dst, src); |
| 5309 | } | 5309 | } |
| 5310 | 5310 | ||
| 5311 | -// __aicore__ inline void asc_transto5hd_b8(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 5311 | +// ==========asc_transto5hd(b8/b16/b32)========== |
| 5312 | -// uint16_t src_stride, bool dst_high_half, bool src_high_half) | 5312 | +__aicore__ inline void asc_transto5hd_b8( |
| 5313 | -#define asc_transto5hd_b8(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half) \ | 5313 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, |
| 5314 | - asc_transto5hd_b8_impl((dst), (src), (repeat), (dst_stride), (src_stride), (dst_high_half), (src_high_half)) | 5314 | + bool src_high_half) |
| 5315 | +{ | ||
| 5316 | + asc_transto5hd_b8_impl(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 5317 | +} | ||
| 5315 | 5318 | ||
| 5316 | -// __aicore__ inline void asc_transto5hd_b8_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 5319 | +[[deprecated("NOTICE: asc_transto5hd_b8_sync is deprecated. " |
| 5317 | -// uint16_t src_stride, bool dst_high_half, bool src_high_half) | 5320 | + "Please use asc_transto5hd_b8 and asc_sync instead.")]] |
| 5318 | -#define asc_transto5hd_b8_sync(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half) \ | 5321 | +__aicore__ inline void asc_transto5hd_b8_sync( |
| 5319 | - asc_transto5hd_b8_sync_impl((dst), (src), (repeat), (dst_stride), (src_stride), (dst_high_half), (src_high_half)) | 5322 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, |
| 5323 | + bool src_high_half) | ||
| 5324 | +{ | ||
| 5325 | + asc_transto5hd_b8_sync_impl(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 5326 | +} | ||
| 5320 | 5327 | ||
| 5321 | -// __aicore__ inline void asc_transto5hd_b16(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 5328 | +__aicore__ inline void asc_transto5hd_b16( |
| 5322 | -// uint16_t src_stride) | 5329 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 5323 | -#define asc_transto5hd_b16(dst, src, repeat, dst_stride, src_stride) \ | 5330 | +{ |
| 5324 | - asc_transto5hd_b16_impl((dst), (src), (repeat), (dst_stride), (src_stride)) | 5331 | + asc_transto5hd_b16_impl(dst, src, repeat, dst_stride, src_stride); |
| 5332 | +} | ||
| 5325 | 5333 | ||
| 5326 | -// __aicore__ inline void asc_transto5hd_b16_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 5334 | +[[deprecated("NOTICE: asc_transto5hd_b16_sync is deprecated. " |
| 5327 | -// uint16_t src_stride) | 5335 | + "Please use asc_transto5hd_b16 and asc_sync instead.")]] |
| 5328 | -#define asc_transto5hd_b16_sync(dst, src, repeat, dst_stride, src_stride) \ | 5336 | +__aicore__ inline void asc_transto5hd_b16_sync( |
| 5329 | - asc_transto5hd_b16_sync_impl((dst), (src), (repeat), (dst_stride), (src_stride)) | 5337 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 5338 | +{ | ||
| 5339 | + asc_transto5hd_b16_sync_impl(dst, src, repeat, dst_stride, src_stride); | ||
| 5340 | +} | ||
| 5330 | 5341 | ||
| 5331 | -// __aicore__ inline void asc_transto5hd_b32(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 5342 | +__aicore__ inline void asc_transto5hd_b32( |
| 5332 | -// uint16_t src_stride) | 5343 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 5333 | -#define asc_transto5hd_b32(dst, src, repeat, dst_stride, src_stride) \ | 5344 | +{ |
| 5334 | - asc_transto5hd_b32_impl((dst), (src), (repeat), (dst_stride), (src_stride)) | 5345 | + asc_transto5hd_b32_impl(dst, src, repeat, dst_stride, src_stride); |
| 5346 | +} | ||
| 5335 | 5347 | ||
| 5336 | -// __aicore__ inline void asc_transto5hd_b32_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 5348 | +[[deprecated("NOTICE: asc_transto5hd_b32_sync is deprecated. " |
| 5337 | -// uint16_t src_stride) | 5349 | + "Please use asc_transto5hd_b32 and asc_sync instead.")]] |
| 5338 | -#define asc_transto5hd_b32_sync(dst, src, repeat, dst_stride, src_stride) \ | 5350 | +__aicore__ inline void asc_transto5hd_b32_sync( |
| 5339 | - asc_transto5hd_b32_sync_impl((dst), (src), (repeat), (dst_stride), (src_stride)) | 5351 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 5352 | +{ | ||
| 5353 | + asc_transto5hd_b32_sync_impl(dst, src, repeat, dst_stride, src_stride); | ||
| 5354 | +} | ||
| 5340 | 5355 | ||
| 5341 | // ==========asc_duplicate(half/int16_t/uint16_t/bfloat16_t/float/int32_t/uint32_t)========== | 5356 | // ==========asc_duplicate(half/int16_t/uint16_t/bfloat16_t/float/int32_t/uint32_t)========== |
| 5342 | __aicore__ inline void asc_duplicate( | 5357 | __aicore__ inline void asc_duplicate( |
| @@ -20,57 +20,165 @@ | |||
| 20 | 20 | ||
| 21 | 21 | ||
| 22 | 22 | ||
| 23 | -// __aicore__ inline void asc_transto5hd_b8_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 23 | +#define ASC_TRANSTO5HD_B8_CALL(dst_va, src_va, repeat, dst_stride, src_stride, dst_high_half, src_high_half) \ |
| 24 | -// uint16_t src_stride, bool dst_high_half, bool src_high_half) | 24 | + do { \ |
| 25 | -#define asc_transto5hd_b8_impl(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half) \ | 25 | + if (!(dst_high_half)) { \ |
| 26 | - do { \ | 26 | + if (!(src_high_half)) { \ |
| 27 | - if ASC_IS_AIV { \ | 27 | + scatter_vnchwconv_b8(dst_va, src_va, repeat, dst_stride, src_stride, false, false); \ |
| 28 | - scatter_vnchwconv_b8( \ | 28 | + } else { \ |
| 29 | - (dst), (src), (repeat), (dst_stride), (src_stride), (dst_high_half), (src_high_half)); \ | 29 | + scatter_vnchwconv_b8(dst_va, src_va, repeat, dst_stride, src_stride, false, true); \ |
| 30 | - } \ | 30 | + } \ |
| 31 | + } else if (!(src_high_half)) { \ | ||
| 32 | + scatter_vnchwconv_b8(dst_va, src_va, repeat, dst_stride, src_stride, true, false); \ | ||
| 33 | + } else { \ | ||
| 34 | + scatter_vnchwconv_b8(dst_va, src_va, repeat, dst_stride, src_stride, true, true); \ | ||
| 35 | + } \ | ||
| 31 | } while (0) | 36 | } while (0) |
| 32 | 37 | ||
| 33 | -// __aicore__ inline void asc_transto5hd_b8_sync_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t | 38 | +__aicore__ inline void asc_transto5hd_b8_impl( |
| 34 | -// dst_stride, uint16_t src_stride, bool dst_high_half, bool src_high_half) | 39 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, |
| 35 | -#define asc_transto5hd_b8_sync_impl(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half) \ | 40 | + bool src_high_half) |
| 36 | - do { \ | 41 | +{ |
| 37 | - asc_transto5hd_b8_impl((dst), (src), (repeat), (dst_stride), (src_stride), (dst_high_half), (src_high_half)); \ | 42 | + if ASC_IS_AIV { |
| 38 | - asc_sync_post_process(); \ | 43 | + if (dst == ub_addr8_t::VA0) { |
| 39 | - } while (0) | 44 | + if (src == ub_addr8_t::VA2) { |
| 45 | + ASC_TRANSTO5HD_B8_CALL(VA0, VA2, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 46 | + } else if (src == ub_addr8_t::VA4) { | ||
| 47 | + ASC_TRANSTO5HD_B8_CALL(VA0, VA4, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 48 | + } else if (src == ub_addr8_t::VA6) { | ||
| 49 | + ASC_TRANSTO5HD_B8_CALL(VA0, VA6, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 50 | + } | ||
| 51 | + } else if (dst == ub_addr8_t::VA2) { | ||
| 52 | + if (src == ub_addr8_t::VA0) { | ||
| 53 | + ASC_TRANSTO5HD_B8_CALL(VA2, VA0, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 54 | + } else if (src == ub_addr8_t::VA4) { | ||
| 55 | + ASC_TRANSTO5HD_B8_CALL(VA2, VA4, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 56 | + } else if (src == ub_addr8_t::VA6) { | ||
| 57 | + ASC_TRANSTO5HD_B8_CALL(VA2, VA6, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 58 | + } | ||
| 59 | + } else if (dst == ub_addr8_t::VA4) { | ||
| 60 | + if (src == ub_addr8_t::VA0) { | ||
| 61 | + ASC_TRANSTO5HD_B8_CALL(VA4, VA0, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 62 | + } else if (src == ub_addr8_t::VA2) { | ||
| 63 | + ASC_TRANSTO5HD_B8_CALL(VA4, VA2, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 64 | + } else if (src == ub_addr8_t::VA6) { | ||
| 65 | + ASC_TRANSTO5HD_B8_CALL(VA4, VA6, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 66 | + } | ||
| 67 | + } else if (dst == ub_addr8_t::VA6) { | ||
| 68 | + if (src == ub_addr8_t::VA0) { | ||
| 69 | + ASC_TRANSTO5HD_B8_CALL(VA6, VA0, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 70 | + } else if (src == ub_addr8_t::VA2) { | ||
| 71 | + ASC_TRANSTO5HD_B8_CALL(VA6, VA2, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 72 | + } else if (src == ub_addr8_t::VA4) { | ||
| 73 | + ASC_TRANSTO5HD_B8_CALL(VA6, VA4, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 74 | + } | ||
| 75 | + } | ||
| 76 | + } | ||
| 77 | +} | ||
| 40 | 78 | ||
| 41 | -// __aicore__ inline void asc_transto5hd_b16_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 79 | +#undef ASC_TRANSTO5HD_B8_CALL |
| 42 | -// uint16_t src_stride) | ||
| 43 | - | ||
| 44 | - do { \ | ||
| 45 | - if ASC_IS_AIV { \ | ||
| 46 | - scatter_vnchwconv_b16((dst), (src), (repeat), (dst_stride), (src_stride)); \ | ||
| 47 | - } \ | ||
| 48 | - } while (0) | ||
| 49 | 80 | ||
| 50 | -// __aicore__ inline void asc_transto5hd_b16_sync_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t | 81 | +__aicore__ inline void asc_transto5hd_b8_sync_impl( |
| 51 | -// dst_stride, uint16_t src_stride) | 82 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, |
| 52 | -#define asc_transto5hd_b16_sync_impl(dst, src, repeat, dst_stride, src_stride) \ | 83 | + bool src_high_half) |
| 53 | - do { \ | 84 | +{ |
| 54 | - asc_transto5hd_b16_impl((dst), (src), (repeat), (dst_stride), (src_stride)); \ | 85 | + asc_transto5hd_b8_impl(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half); |
| 55 | - asc_sync_post_process(); \ | 86 | + asc_sync_post_process(); |
| 56 | - } while (0) | 87 | +} |
| 57 | 88 | ||
| 58 | -// __aicore__ inline void asc_transto5hd_b32_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 89 | +__aicore__ inline void asc_transto5hd_b16_impl( |
| 59 | -// uint16_t src_stride) | 90 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 60 | -#define asc_transto5hd_b32_impl(dst, src, repeat, dst_stride, src_stride) \ | 91 | +{ |
| 61 | - do { \ | 92 | + if ASC_IS_AIV { |
| 62 | - if ASC_IS_AIV { \ | 93 | + if (dst == ub_addr8_t::VA0) { |
| 63 | - scatter_vnchwconv_b32((dst), (src), (repeat), (dst_stride), (src_stride)); \ | 94 | + if (src == ub_addr8_t::VA2) { |
| 64 | - } \ | 95 | + scatter_vnchwconv_b16(VA0, VA2, repeat, dst_stride, src_stride); |
| 65 | - } while (0) | 96 | + } else if (src == ub_addr8_t::VA4) { |
| 97 | + scatter_vnchwconv_b16(VA0, VA4, repeat, dst_stride, src_stride); | ||
| 98 | + } else if (src == ub_addr8_t::VA6) { | ||
| 99 | + scatter_vnchwconv_b16(VA0, VA6, repeat, dst_stride, src_stride); | ||
| 100 | + } | ||
| 101 | + } else if (dst == ub_addr8_t::VA2) { | ||
| 102 | + if (src == ub_addr8_t::VA0) { | ||
| 103 | + scatter_vnchwconv_b16(VA2, VA0, repeat, dst_stride, src_stride); | ||
| 104 | + } else if (src == ub_addr8_t::VA4) { | ||
| 105 | + scatter_vnchwconv_b16(VA2, VA4, repeat, dst_stride, src_stride); | ||
| 106 | + } else if (src == ub_addr8_t::VA6) { | ||
| 107 | + scatter_vnchwconv_b16(VA2, VA6, repeat, dst_stride, src_stride); | ||
| 108 | + } | ||
| 109 | + } else if (dst == ub_addr8_t::VA4) { | ||
| 110 | + if (src == ub_addr8_t::VA0) { | ||
| 111 | + scatter_vnchwconv_b16(VA4, VA0, repeat, dst_stride, src_stride); | ||
| 112 | + } else if (src == ub_addr8_t::VA2) { | ||
| 113 | + scatter_vnchwconv_b16(VA4, VA2, repeat, dst_stride, src_stride); | ||
| 114 | + } else if (src == ub_addr8_t::VA6) { | ||
| 115 | + scatter_vnchwconv_b16(VA4, VA6, repeat, dst_stride, src_stride); | ||
| 116 | + } | ||
| 117 | + } else if (dst == ub_addr8_t::VA6) { | ||
| 118 | + if (src == ub_addr8_t::VA0) { | ||
| 119 | + scatter_vnchwconv_b16(VA6, VA0, repeat, dst_stride, src_stride); | ||
| 120 | + } else if (src == ub_addr8_t::VA2) { | ||
| 121 | + scatter_vnchwconv_b16(VA6, VA2, repeat, dst_stride, src_stride); | ||
| 122 | + } else if (src == ub_addr8_t::VA4) { | ||
| 123 | + scatter_vnchwconv_b16(VA6, VA4, repeat, dst_stride, src_stride); | ||
| 124 | + } | ||
| 125 | + } | ||
| 126 | + } | ||
| 127 | +} | ||
| 66 | 128 | ||
| 67 | -// __aicore__ inline void asc_transto5hd_b32_sync_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t | 129 | +__aicore__ inline void asc_transto5hd_b16_sync_impl( |
| 68 | -// dst_stride, uint16_t src_stride) | 130 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 69 | -#define asc_transto5hd_b32_sync_impl(dst, src, repeat, dst_stride, src_stride) \ | 131 | +{ |
| 70 | - do { \ | 132 | + asc_transto5hd_b16_impl(dst, src, repeat, dst_stride, src_stride); |
| 71 | - asc_transto5hd_b32_impl((dst), (src), (repeat), (dst_stride), (src_stride)); \ | 133 | + asc_sync_post_process(); |
| 72 | - asc_sync_post_process(); \ | 134 | +} |
| 73 | - } while (0) | 135 | + |
| 136 | +__aicore__ inline void asc_transto5hd_b32_impl( | ||
| 137 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) | ||
| 138 | +{ | ||
| 139 | + if ASC_IS_AIV { | ||
| 140 | + if (dst == ub_addr8_t::VA0) { | ||
| 141 | + if (src == ub_addr8_t::VA2) { | ||
| 142 | + scatter_vnchwconv_b32(VA0, VA2, repeat, dst_stride, src_stride); | ||
| 143 | + } else if (src == ub_addr8_t::VA4) { | ||
| 144 | + scatter_vnchwconv_b32(VA0, VA4, repeat, dst_stride, src_stride); | ||
| 145 | + } else if (src == ub_addr8_t::VA6) { | ||
| 146 | + scatter_vnchwconv_b32(VA0, VA6, repeat, dst_stride, src_stride); | ||
| 147 | + } | ||
| 148 | + } else if (dst == ub_addr8_t::VA2) { | ||
| 149 | + if (src == ub_addr8_t::VA0) { | ||
| 150 | + scatter_vnchwconv_b32(VA2, VA0, repeat, dst_stride, src_stride); | ||
| 151 | + } else if (src == ub_addr8_t::VA4) { | ||
| 152 | + scatter_vnchwconv_b32(VA2, VA4, repeat, dst_stride, src_stride); | ||
| 153 | + } else if (src == ub_addr8_t::VA6) { | ||
| 154 | + scatter_vnchwconv_b32(VA2, VA6, repeat, dst_stride, src_stride); | ||
| 155 | + } | ||
| 156 | + } else if (dst == ub_addr8_t::VA4) { | ||
| 157 | + if (src == ub_addr8_t::VA0) { | ||
| 158 | + scatter_vnchwconv_b32(VA4, VA0, repeat, dst_stride, src_stride); | ||
| 159 | + } else if (src == ub_addr8_t::VA2) { | ||
| 160 | + scatter_vnchwconv_b32(VA4, VA2, repeat, dst_stride, src_stride); | ||
| 161 | + } else if (src == ub_addr8_t::VA6) { | ||
| 162 | + scatter_vnchwconv_b32(VA4, VA6, repeat, dst_stride, src_stride); | ||
| 163 | + } | ||
| 164 | + } else if (dst == ub_addr8_t::VA6) { | ||
| 165 | + if (src == ub_addr8_t::VA0) { | ||
| 166 | + scatter_vnchwconv_b32(VA6, VA0, repeat, dst_stride, src_stride); | ||
| 167 | + } else if (src == ub_addr8_t::VA2) { | ||
| 168 | + scatter_vnchwconv_b32(VA6, VA2, repeat, dst_stride, src_stride); | ||
| 169 | + } else if (src == ub_addr8_t::VA4) { | ||
| 170 | + scatter_vnchwconv_b32(VA6, VA4, repeat, dst_stride, src_stride); | ||
| 171 | + } | ||
| 172 | + } | ||
| 173 | + } | ||
| 174 | +} | ||
| 175 | + | ||
| 176 | +__aicore__ inline void asc_transto5hd_b32_sync_impl( | ||
| 177 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) | ||
| 178 | +{ | ||
| 179 | + asc_transto5hd_b32_impl(dst, src, repeat, dst_stride, src_stride); | ||
| 180 | + asc_sync_post_process(); | ||
| 181 | +} | ||
| 74 | 182 | ||
| 75 | 183 | ||
| 76 | 184 | ||
| @@ -9909,35 +9909,50 @@ __aicore__ inline void asc_transpose_sync(__ubuf__ uint16_t* dst, __ubuf__ uint1 | |||
| 9909 | asc_transpose_sync_impl(dst, src); | 9909 | asc_transpose_sync_impl(dst, src); |
| 9910 | } | 9910 | } |
| 9911 | 9911 | ||
| 9912 | -// __aicore__ inline void asc_transto5hd_b8(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 9912 | +// ==========asc_transto5hd(b8/b16/b32)========== |
| 9913 | -// uint16_t src_stride, bool dst_high_half, bool src_high_half) | 9913 | +__aicore__ inline void asc_transto5hd_b8( |
| 9914 | -#define asc_transto5hd_b8(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half) \ | 9914 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, |
| 9915 | - asc_transto5hd_b8_impl((dst), (src), (repeat), (dst_stride), (src_stride), (dst_high_half), (src_high_half)) | 9915 | + bool src_high_half) |
| 9916 | +{ | ||
| 9917 | + asc_transto5hd_b8_impl(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 9918 | +} | ||
| 9916 | 9919 | ||
| 9917 | -// __aicore__ inline void asc_transto5hd_b8_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 9920 | +[[deprecated("NOTICE: asc_transto5hd_b8_sync is deprecated. " |
| 9918 | -// uint16_t src_stride, bool dst_high_half, bool src_high_half) | 9921 | + "Please use asc_transto5hd_b8 and asc_sync instead.")]] |
| 9919 | -#define asc_transto5hd_b8_sync(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half) \ | 9922 | +__aicore__ inline void asc_transto5hd_b8_sync( |
| 9920 | - asc_transto5hd_b8_sync_impl((dst), (src), (repeat), (dst_stride), (src_stride), (dst_high_half), (src_high_half)) | 9923 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, |
| 9924 | + bool src_high_half) | ||
| 9925 | +{ | ||
| 9926 | + asc_transto5hd_b8_sync_impl(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 9927 | +} | ||
| 9921 | 9928 | ||
| 9922 | -// __aicore__ inline void asc_transto5hd_b16(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 9929 | +__aicore__ inline void asc_transto5hd_b16( |
| 9923 | -// uint16_t src_stride) | 9930 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 9924 | -#define asc_transto5hd_b16(dst, src, repeat, dst_stride, src_stride) \ | 9931 | +{ |
| 9925 | - asc_transto5hd_b16_impl((dst), (src), (repeat), (dst_stride), (src_stride)) | 9932 | + asc_transto5hd_b16_impl(dst, src, repeat, dst_stride, src_stride); |
| 9933 | +} | ||
| 9926 | 9934 | ||
| 9927 | -// __aicore__ inline void asc_transto5hd_b16_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 9935 | +[[deprecated("NOTICE: asc_transto5hd_b16_sync is deprecated. " |
| 9928 | -// uint16_t src_stride) | 9936 | + "Please use asc_transto5hd_b16 and asc_sync instead.")]] |
| 9929 | -#define asc_transto5hd_b16_sync(dst, src, repeat, dst_stride, src_stride) \ | 9937 | +__aicore__ inline void asc_transto5hd_b16_sync( |
| 9930 | - asc_transto5hd_b16_sync_impl((dst), (src), (repeat), (dst_stride), (src_stride)) | 9938 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 9939 | +{ | ||
| 9940 | + asc_transto5hd_b16_sync_impl(dst, src, repeat, dst_stride, src_stride); | ||
| 9941 | +} | ||
| 9931 | 9942 | ||
| 9932 | -// __aicore__ inline void asc_transto5hd_b32(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 9943 | +__aicore__ inline void asc_transto5hd_b32( |
| 9933 | -// uint16_t src_stride) | 9944 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 9934 | -#define asc_transto5hd_b32(dst, src, repeat, dst_stride, src_stride) \ | 9945 | +{ |
| 9935 | - asc_transto5hd_b32_impl((dst), (src), (repeat), (dst_stride), (src_stride)) | 9946 | + asc_transto5hd_b32_impl(dst, src, repeat, dst_stride, src_stride); |
| 9947 | +} | ||
| 9936 | 9948 | ||
| 9937 | -// __aicore__ inline void asc_transto5hd_b32_sync(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 9949 | +[[deprecated("NOTICE: asc_transto5hd_b32_sync is deprecated. " |
| 9938 | -// uint16_t src_stride) | 9950 | + "Please use asc_transto5hd_b32 and asc_sync instead.")]] |
| 9939 | -#define asc_transto5hd_b32_sync(dst, src, repeat, dst_stride, src_stride) \ | 9951 | +__aicore__ inline void asc_transto5hd_b32_sync( |
L | |||
| 9940 | - asc_transto5hd_b32_sync_impl((dst), (src), (repeat), (dst_stride), (src_stride)) | 9952 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 9953 | +{ | ||
| 9954 | + asc_transto5hd_b32_sync_impl(dst, src, repeat, dst_stride, src_stride); | ||
| 9955 | +} | ||
| 9941 | 9956 | ||
| 9942 | // ===================asc_set_va_reg===================== | 9957 | // ===================asc_set_va_reg===================== |
| 9943 | __aicore__ inline void asc_set_va_reg(ub_addr8_t addr, __ubuf__ int8_t** src_array) | 9958 | __aicore__ inline void asc_set_va_reg(ub_addr8_t addr, __ubuf__ int8_t** src_array) |
| @@ -24,57 +24,165 @@ | |||
| 24 | 24 | ||
| 25 | 25 | ||
| 26 | 26 | ||
| 27 | -// __aicore__ inline void asc_transto5hd_b8_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 27 | +#define ASC_TRANSTO5HD_B8_CALL(dst_va, src_va, repeat, dst_stride, src_stride, dst_high_half, src_high_half) \ |
| 28 | -// uint16_t src_stride, bool dst_high_half, bool src_high_half) | 28 | + do { \ |
| 29 | -#define asc_transto5hd_b8_impl(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half) \ | 29 | + if (!(dst_high_half)) { \ |
| 30 | - do { \ | 30 | + if (!(src_high_half)) { \ |
| 31 | - if ASC_IS_AIV { \ | 31 | + scatter_vnchwconv_b8(dst_va, src_va, repeat, dst_stride, src_stride, false, false); \ |
| 32 | - scatter_vnchwconv_b8( \ | 32 | + } else { \ |
| 33 | - (dst), (src), (repeat), (dst_stride), (src_stride), (dst_high_half), (src_high_half)); \ | 33 | + scatter_vnchwconv_b8(dst_va, src_va, repeat, dst_stride, src_stride, false, true); \ |
| 34 | - } \ | 34 | + } \ |
| 35 | + } else if (!(src_high_half)) { \ | ||
| 36 | + scatter_vnchwconv_b8(dst_va, src_va, repeat, dst_stride, src_stride, true, false); \ | ||
| 37 | + } else { \ | ||
| 38 | + scatter_vnchwconv_b8(dst_va, src_va, repeat, dst_stride, src_stride, true, true); \ | ||
| 39 | + } \ | ||
| 35 | } while (0) | 40 | } while (0) |
| 36 | 41 | ||
| 37 | -// __aicore__ inline void asc_transto5hd_b8_sync_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t | 42 | +__aicore__ inline void asc_transto5hd_b8_impl( |
| 38 | -// dst_stride, uint16_t src_stride, bool dst_high_half, bool src_high_half) | 43 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, |
| 39 | -#define asc_transto5hd_b8_sync_impl(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half) \ | 44 | + bool src_high_half) |
| 40 | - do { \ | 45 | +{ |
| 41 | - asc_transto5hd_b8_impl((dst), (src), (repeat), (dst_stride), (src_stride), (dst_high_half), (src_high_half)); \ | 46 | + if ASC_IS_AIV { |
| 42 | - asc_sync_post_process(); \ | 47 | + if (dst == ub_addr8_t::VA0) { |
| 43 | - } while (0) | 48 | + if (src == ub_addr8_t::VA2) { |
| 49 | + ASC_TRANSTO5HD_B8_CALL(VA0, VA2, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 50 | + } else if (src == ub_addr8_t::VA4) { | ||
| 51 | + ASC_TRANSTO5HD_B8_CALL(VA0, VA4, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 52 | + } else if (src == ub_addr8_t::VA6) { | ||
| 53 | + ASC_TRANSTO5HD_B8_CALL(VA0, VA6, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 54 | + } | ||
| 55 | + } else if (dst == ub_addr8_t::VA2) { | ||
| 56 | + if (src == ub_addr8_t::VA0) { | ||
| 57 | + ASC_TRANSTO5HD_B8_CALL(VA2, VA0, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 58 | + } else if (src == ub_addr8_t::VA4) { | ||
| 59 | + ASC_TRANSTO5HD_B8_CALL(VA2, VA4, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 60 | + } else if (src == ub_addr8_t::VA6) { | ||
| 61 | + ASC_TRANSTO5HD_B8_CALL(VA2, VA6, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 62 | + } | ||
| 63 | + } else if (dst == ub_addr8_t::VA4) { | ||
| 64 | + if (src == ub_addr8_t::VA0) { | ||
| 65 | + ASC_TRANSTO5HD_B8_CALL(VA4, VA0, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 66 | + } else if (src == ub_addr8_t::VA2) { | ||
| 67 | + ASC_TRANSTO5HD_B8_CALL(VA4, VA2, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 68 | + } else if (src == ub_addr8_t::VA6) { | ||
| 69 | + ASC_TRANSTO5HD_B8_CALL(VA4, VA6, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 70 | + } | ||
| 71 | + } else if (dst == ub_addr8_t::VA6) { | ||
| 72 | + if (src == ub_addr8_t::VA0) { | ||
| 73 | + ASC_TRANSTO5HD_B8_CALL(VA6, VA0, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 74 | + } else if (src == ub_addr8_t::VA2) { | ||
| 75 | + ASC_TRANSTO5HD_B8_CALL(VA6, VA2, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 76 | + } else if (src == ub_addr8_t::VA4) { | ||
| 77 | + ASC_TRANSTO5HD_B8_CALL(VA6, VA4, repeat, dst_stride, src_stride, dst_high_half, src_high_half); | ||
| 78 | + } | ||
| 79 | + } | ||
| 80 | + } | ||
| 81 | +} | ||
| 44 | 82 | ||
| 45 | -// __aicore__ inline void asc_transto5hd_b16_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 83 | +#undef ASC_TRANSTO5HD_B8_CALL |
| 46 | -// uint16_t src_stride) | ||
| 47 | - | ||
| 48 | - do { \ | ||
| 49 | - if ASC_IS_AIV { \ | ||
| 50 | - scatter_vnchwconv_b16((dst), (src), (repeat), (dst_stride), (src_stride)); \ | ||
| 51 | - } \ | ||
| 52 | - } while (0) | ||
| 53 | 84 | ||
| 54 | -// __aicore__ inline void asc_transto5hd_b16_sync_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t | 85 | +__aicore__ inline void asc_transto5hd_b8_sync_impl( |
不再提供_sync形式的接口 ![]() ![]() | |||
| 55 | -// dst_stride, uint16_t src_stride) | 86 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, |
| 56 | -#define asc_transto5hd_b16_sync_impl(dst, src, repeat, dst_stride, src_stride) \ | 87 | + bool src_high_half) |
| 57 | - do { \ | 88 | +{ |
| 58 | - asc_transto5hd_b16_impl((dst), (src), (repeat), (dst_stride), (src_stride)); \ | 89 | + asc_transto5hd_b8_impl(dst, src, repeat, dst_stride, src_stride, dst_high_half, src_high_half); |
| 59 | - asc_sync_post_process(); \ | 90 | + asc_sync_post_process(); |
| 60 | - } while (0) | 91 | +} |
| 61 | 92 | ||
| 62 | -// __aicore__ inline void asc_transto5hd_b32_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, | 93 | +__aicore__ inline void asc_transto5hd_b16_impl( |
| 63 | -// uint16_t src_stride) | 94 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 64 | -#define asc_transto5hd_b32_impl(dst, src, repeat, dst_stride, src_stride) \ | 95 | +{ |
| 65 | - do { \ | 96 | + if ASC_IS_AIV { |
| 66 | - if ASC_IS_AIV { \ | 97 | + if (dst == ub_addr8_t::VA0) { |
| 67 | - scatter_vnchwconv_b32((dst), (src), (repeat), (dst_stride), (src_stride)); \ | 98 | + if (src == ub_addr8_t::VA2) { |
| 68 | - } \ | 99 | + scatter_vnchwconv_b16(VA0, VA2, repeat, dst_stride, src_stride); |
| 69 | - } while (0) | 100 | + } else if (src == ub_addr8_t::VA4) { |
| 101 | + scatter_vnchwconv_b16(VA0, VA4, repeat, dst_stride, src_stride); | ||
| 102 | + } else if (src == ub_addr8_t::VA6) { | ||
| 103 | + scatter_vnchwconv_b16(VA0, VA6, repeat, dst_stride, src_stride); | ||
| 104 | + } | ||
| 105 | + } else if (dst == ub_addr8_t::VA2) { | ||
| 106 | + if (src == ub_addr8_t::VA0) { | ||
| 107 | + scatter_vnchwconv_b16(VA2, VA0, repeat, dst_stride, src_stride); | ||
| 108 | + } else if (src == ub_addr8_t::VA4) { | ||
| 109 | + scatter_vnchwconv_b16(VA2, VA4, repeat, dst_stride, src_stride); | ||
| 110 | + } else if (src == ub_addr8_t::VA6) { | ||
| 111 | + scatter_vnchwconv_b16(VA2, VA6, repeat, dst_stride, src_stride); | ||
| 112 | + } | ||
| 113 | + } else if (dst == ub_addr8_t::VA4) { | ||
| 114 | + if (src == ub_addr8_t::VA0) { | ||
| 115 | + scatter_vnchwconv_b16(VA4, VA0, repeat, dst_stride, src_stride); | ||
| 116 | + } else if (src == ub_addr8_t::VA2) { | ||
| 117 | + scatter_vnchwconv_b16(VA4, VA2, repeat, dst_stride, src_stride); | ||
| 118 | + } else if (src == ub_addr8_t::VA6) { | ||
| 119 | + scatter_vnchwconv_b16(VA4, VA6, repeat, dst_stride, src_stride); | ||
| 120 | + } | ||
| 121 | + } else if (dst == ub_addr8_t::VA6) { | ||
| 122 | + if (src == ub_addr8_t::VA0) { | ||
| 123 | + scatter_vnchwconv_b16(VA6, VA0, repeat, dst_stride, src_stride); | ||
| 124 | + } else if (src == ub_addr8_t::VA2) { | ||
| 125 | + scatter_vnchwconv_b16(VA6, VA2, repeat, dst_stride, src_stride); | ||
| 126 | + } else if (src == ub_addr8_t::VA4) { | ||
| 127 | + scatter_vnchwconv_b16(VA6, VA4, repeat, dst_stride, src_stride); | ||
| 128 | + } | ||
| 129 | + } | ||
| 130 | + } | ||
| 131 | +} | ||
| 70 | 132 | ||
| 71 | -// __aicore__ inline void asc_transto5hd_b32_sync_impl(ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t | 133 | +__aicore__ inline void asc_transto5hd_b16_sync_impl( |
| 72 | -// dst_stride, uint16_t src_stride) | 134 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 73 | -#define asc_transto5hd_b32_sync_impl(dst, src, repeat, dst_stride, src_stride) \ | 135 | +{ |
| 74 | - do { \ | 136 | + asc_transto5hd_b16_impl(dst, src, repeat, dst_stride, src_stride); |
| 75 | - asc_transto5hd_b32_impl((dst), (src), (repeat), (dst_stride), (src_stride)); \ | 137 | + asc_sync_post_process(); |
| 76 | - asc_sync_post_process(); \ | 138 | +} |
| 77 | - } while (0) | 139 | + |
| 140 | +__aicore__ inline void asc_transto5hd_b32_impl( | ||
| 141 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) | ||
| 142 | +{ | ||
| 143 | + if ASC_IS_AIV { | ||
| 144 | + if (dst == ub_addr8_t::VA0) { | ||
| 145 | + if (src == ub_addr8_t::VA2) { | ||
| 146 | + scatter_vnchwconv_b32(VA0, VA2, repeat, dst_stride, src_stride); | ||
| 147 | + } else if (src == ub_addr8_t::VA4) { | ||
| 148 | + scatter_vnchwconv_b32(VA0, VA4, repeat, dst_stride, src_stride); | ||
| 149 | + } else if (src == ub_addr8_t::VA6) { | ||
| 150 | + scatter_vnchwconv_b32(VA0, VA6, repeat, dst_stride, src_stride); | ||
| 151 | + } | ||
| 152 | + } else if (dst == ub_addr8_t::VA2) { | ||
| 153 | + if (src == ub_addr8_t::VA0) { | ||
| 154 | + scatter_vnchwconv_b32(VA2, VA0, repeat, dst_stride, src_stride); | ||
| 155 | + } else if (src == ub_addr8_t::VA4) { | ||
| 156 | + scatter_vnchwconv_b32(VA2, VA4, repeat, dst_stride, src_stride); | ||
| 157 | + } else if (src == ub_addr8_t::VA6) { | ||
| 158 | + scatter_vnchwconv_b32(VA2, VA6, repeat, dst_stride, src_stride); | ||
| 159 | + } | ||
| 160 | + } else if (dst == ub_addr8_t::VA4) { | ||
| 161 | + if (src == ub_addr8_t::VA0) { | ||
| 162 | + scatter_vnchwconv_b32(VA4, VA0, repeat, dst_stride, src_stride); | ||
| 163 | + } else if (src == ub_addr8_t::VA2) { | ||
| 164 | + scatter_vnchwconv_b32(VA4, VA2, repeat, dst_stride, src_stride); | ||
| 165 | + } else if (src == ub_addr8_t::VA6) { | ||
| 166 | + scatter_vnchwconv_b32(VA4, VA6, repeat, dst_stride, src_stride); | ||
| 167 | + } | ||
| 168 | + } else if (dst == ub_addr8_t::VA6) { | ||
| 169 | + if (src == ub_addr8_t::VA0) { | ||
| 170 | + scatter_vnchwconv_b32(VA6, VA0, repeat, dst_stride, src_stride); | ||
| 171 | + } else if (src == ub_addr8_t::VA2) { | ||
| 172 | + scatter_vnchwconv_b32(VA6, VA2, repeat, dst_stride, src_stride); | ||
| 173 | + } else if (src == ub_addr8_t::VA4) { | ||
| 174 | + scatter_vnchwconv_b32(VA6, VA4, repeat, dst_stride, src_stride); | ||
| 175 | + } | ||
| 176 | + } | ||
| 177 | + } | ||
| 178 | +} | ||
| 179 | + | ||
| 180 | +__aicore__ inline void asc_transto5hd_b32_sync_impl( | ||
| 181 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) | ||
| 182 | +{ | ||
| 183 | + asc_transto5hd_b32_impl(dst, src, repeat, dst_stride, src_stride); | ||
| 184 | + asc_sync_post_process(); | ||
| 185 | +} | ||
| 78 | 186 | ||
| 79 | 187 | ||
| 80 | 188 | ||
| @@ -416,22 +416,6 @@ __simd_callee__ inline vector_bool asc_unpack_upper(vector_bool src); | |||
| 416 | 416 | ||
| 417 | __simd_callee__ inline vector_bool asc_unpack_lower(vector_bool src); | 417 | __simd_callee__ inline vector_bool asc_unpack_lower(vector_bool src); |
| 418 | 418 | ||
| 419 | -__aicore__ inline void asc_set_va_reg(ub_addr8_t addr, __ubuf__ int8_t** src_array); | ||
| 420 | - | ||
| 421 | -__aicore__ inline void asc_set_va_reg(ub_addr8_t addr, __ubuf__ uint8_t** src_array); | ||
| 422 | - | ||
| 423 | -__aicore__ inline void asc_set_va_reg(ub_addr8_t addr, __ubuf__ int16_t** src_array); | ||
| 424 | - | ||
| 425 | -__aicore__ inline void asc_set_va_reg(ub_addr8_t addr, __ubuf__ uint16_t** src_array); | ||
| 426 | - | ||
| 427 | -__aicore__ inline void asc_set_va_reg(ub_addr8_t addr, __ubuf__ half** src_array); | ||
| 428 | - | ||
| 429 | -__aicore__ inline void asc_set_va_reg(ub_addr8_t addr, __ubuf__ int32_t** src_array); | ||
| 430 | - | ||
| 431 | -__aicore__ inline void asc_set_va_reg(ub_addr8_t addr, __ubuf__ uint32_t** src_array); | ||
| 432 | - | ||
| 433 | -__aicore__ inline void asc_set_va_reg(ub_addr8_t addr, __ubuf__ float** src_array); | ||
| 434 | - | ||
| 435 | [[deprecated("NOTICE: asc_squeeze_with_status is deprecated. " | 419 | [[deprecated("NOTICE: asc_squeeze_with_status is deprecated. " |
| 436 | "Please use asc_squeeze_and_storeunalign instead.")]] __simd_callee__ inline void | 420 | "Please use asc_squeeze_and_storeunalign instead.")]] __simd_callee__ inline void |
| 437 | asc_squeeze_with_status(vector_uint8_t& dst, vector_uint8_t src, vector_bool mask); | 421 | asc_squeeze_with_status(vector_uint8_t& dst, vector_uint8_t src, vector_bool mask); |
| @@ -26,6 +26,16 @@ | |||
| 26 | 26 | ||
| 27 | 27 | ||
| 28 | 28 | ||
| 29 | + | ||
| 30 | +// ==========asc_transto5hd(b8/b16/b32)========== | ||
| 31 | +__aicore__ inline void asc_transto5hd_b8( | ||
| 32 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride, bool dst_high_half, | ||
| 33 | + bool src_high_half); | ||
| 34 | +__aicore__ inline void asc_transto5hd_b16( | ||
| 35 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride); | ||
| 36 | +__aicore__ inline void asc_transto5hd_b32( | ||
| 37 | + ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride); | ||
| 38 | + | ||
| 29 | __aicore__ inline void asc_bfloat162float( | 39 | __aicore__ inline void asc_bfloat162float( |
| 30 | __ubuf__ float* dst, __ubuf__ bfloat16_t* src, uint8_t repeat, uint16_t dst_block_stride, uint16_t src_block_stride, | 40 | __ubuf__ float* dst, __ubuf__ bfloat16_t* src, uint8_t repeat, uint16_t dst_block_stride, uint16_t src_block_stride, |
| 31 | uint16_t dst_repeat_stride, uint16_t src_repeat_stride); | 41 | uint16_t dst_repeat_stride, uint16_t src_repeat_stride); |
| @@ -610,7 +610,6 @@ static void test_host_c_api_reg_compute_17() | |||
| 610 | using ::asc_round; | 610 | using ::asc_round; |
| 611 | using ::asc_scatter; | 611 | using ::asc_scatter; |
| 612 | using ::asc_select; | 612 | using ::asc_select; |
| 613 | - using ::asc_set_va_reg; | ||
| 614 | using ::asc_shiftleft; | 613 | using ::asc_shiftleft; |
| 615 | using ::asc_shiftleft_scalar; | 614 | using ::asc_shiftleft_scalar; |
| 616 | using ::asc_shiftright; | 615 | using ::asc_shiftright; |
| @@ -36,8 +36,8 @@ void scatter_vnchwconv_b8_stub( | |||
| 36 | void scatter_vnchwconv_b16_stub( | 36 | void scatter_vnchwconv_b16_stub( |
| 37 | ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) | 37 | ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 38 | { | 38 | { |
| 39 | - EXPECT_EQ(ub_addr8_t::VA1, dst); | 39 | + EXPECT_EQ(ub_addr8_t::VA2, dst); |
| 40 | - EXPECT_EQ(ub_addr8_t::VA3, src); | 40 | + EXPECT_EQ(ub_addr8_t::VA4, src); |
| 41 | EXPECT_EQ(repeat, static_cast<uint8_t>(5)); | 41 | EXPECT_EQ(repeat, static_cast<uint8_t>(5)); |
| 42 | EXPECT_EQ(dst_stride, static_cast<uint16_t>(6)); | 42 | EXPECT_EQ(dst_stride, static_cast<uint16_t>(6)); |
| 43 | EXPECT_EQ(src_stride, static_cast<uint16_t>(7)); | 43 | EXPECT_EQ(src_stride, static_cast<uint16_t>(7)); |
| @@ -47,7 +47,7 @@ void scatter_vnchwconv_b32_stub( | |||
| 47 | ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) | 47 | ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 48 | { | 48 | { |
| 49 | EXPECT_EQ(ub_addr8_t::VA4, dst); | 49 | EXPECT_EQ(ub_addr8_t::VA4, dst); |
| 50 | - EXPECT_EQ(ub_addr8_t::VA5, src); | 50 | + EXPECT_EQ(ub_addr8_t::VA6, src); |
| 51 | EXPECT_EQ(repeat, static_cast<uint8_t>(8)); | 51 | EXPECT_EQ(repeat, static_cast<uint8_t>(8)); |
| 52 | EXPECT_EQ(dst_stride, static_cast<uint16_t>(9)); | 52 | EXPECT_EQ(dst_stride, static_cast<uint16_t>(9)); |
| 53 | EXPECT_EQ(src_stride, static_cast<uint16_t>(10)); | 53 | EXPECT_EQ(src_stride, static_cast<uint16_t>(10)); |
| @@ -94,7 +94,7 @@ TEST_F(TestTransdataTo5HDCAPI, asc_transto5hd_b16_Succ) | |||
| 94 | .times(1) | 94 | .times(1) |
| 95 | .will(invoke(scatter_vnchwconv_b16_stub)); | 95 | .will(invoke(scatter_vnchwconv_b16_stub)); |
| 96 | 96 | ||
| 97 | - asc_transto5hd_b16(ub_addr8_t::VA1, ub_addr8_t::VA3, repeat, dst_stride, src_stride); | 97 | + asc_transto5hd_b16(ub_addr8_t::VA2, ub_addr8_t::VA4, repeat, dst_stride, src_stride); |
| 98 | GlobalMockObject::verify(); | 98 | GlobalMockObject::verify(); |
| 99 | } | 99 | } |
| 100 | 100 | ||
| @@ -107,7 +107,7 @@ TEST_F(TestTransdataTo5HDCAPI, asc_transto5hd_b16_sync_Succ) | |||
| 107 | .times(1) | 107 | .times(1) |
| 108 | .will(invoke(scatter_vnchwconv_b16_stub)); | 108 | .will(invoke(scatter_vnchwconv_b16_stub)); |
| 109 | 109 | ||
| 110 | - asc_transto5hd_b16_sync(ub_addr8_t::VA1, ub_addr8_t::VA3, repeat, dst_stride, src_stride); | 110 | + asc_transto5hd_b16_sync(ub_addr8_t::VA2, ub_addr8_t::VA4, repeat, dst_stride, src_stride); |
| 111 | GlobalMockObject::verify(); | 111 | GlobalMockObject::verify(); |
| 112 | } | 112 | } |
| 113 | 113 | ||
| @@ -120,7 +120,7 @@ TEST_F(TestTransdataTo5HDCAPI, asc_transto5hd_b32_Succ) | |||
| 120 | .times(1) | 120 | .times(1) |
| 121 | .will(invoke(scatter_vnchwconv_b32_stub)); | 121 | .will(invoke(scatter_vnchwconv_b32_stub)); |
| 122 | 122 | ||
| 123 | - asc_transto5hd_b32(ub_addr8_t::VA4, ub_addr8_t::VA5, repeat, dst_stride, src_stride); | 123 | + asc_transto5hd_b32(ub_addr8_t::VA4, ub_addr8_t::VA6, repeat, dst_stride, src_stride); |
| 124 | GlobalMockObject::verify(); | 124 | GlobalMockObject::verify(); |
| 125 | } | 125 | } |
| 126 | 126 | ||
| @@ -133,6 +133,6 @@ TEST_F(TestTransdataTo5HDCAPI, asc_transto5hd_b32_sync_Succ) | |||
| 133 | .times(1) | 133 | .times(1) |
| 134 | .will(invoke(scatter_vnchwconv_b32_stub)); | 134 | .will(invoke(scatter_vnchwconv_b32_stub)); |
| 135 | 135 | ||
| 136 | - asc_transto5hd_b32_sync(ub_addr8_t::VA4, ub_addr8_t::VA5, repeat, dst_stride, src_stride); | 136 | + asc_transto5hd_b32_sync(ub_addr8_t::VA4, ub_addr8_t::VA6, repeat, dst_stride, src_stride); |
| 137 | GlobalMockObject::verify(); | 137 | GlobalMockObject::verify(); |
| 138 | } | 138 | } |
| @@ -36,8 +36,8 @@ void scatter_vnchwconv_b8_stub_repeat( | |||
| 36 | void scatter_vnchwconv_b16_stub_repeat( | 36 | void scatter_vnchwconv_b16_stub_repeat( |
| 37 | ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) | 37 | ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 38 | { | 38 | { |
| 39 | - EXPECT_EQ(ub_addr8_t::VA1, dst); | 39 | + EXPECT_EQ(ub_addr8_t::VA2, dst); |
| 40 | - EXPECT_EQ(ub_addr8_t::VA3, src); | 40 | + EXPECT_EQ(ub_addr8_t::VA4, src); |
| 41 | EXPECT_EQ(repeat, static_cast<uint8_t>(5)); | 41 | EXPECT_EQ(repeat, static_cast<uint8_t>(5)); |
| 42 | EXPECT_EQ(dst_stride, static_cast<uint16_t>(6)); | 42 | EXPECT_EQ(dst_stride, static_cast<uint16_t>(6)); |
| 43 | EXPECT_EQ(src_stride, static_cast<uint16_t>(7)); | 43 | EXPECT_EQ(src_stride, static_cast<uint16_t>(7)); |
| @@ -47,7 +47,7 @@ void scatter_vnchwconv_b32_stub_repeat( | |||
| 47 | ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) | 47 | ub_addr8_t dst, ub_addr8_t src, uint8_t repeat, uint16_t dst_stride, uint16_t src_stride) |
| 48 | { | 48 | { |
| 49 | EXPECT_EQ(ub_addr8_t::VA4, dst); | 49 | EXPECT_EQ(ub_addr8_t::VA4, dst); |
| 50 | - EXPECT_EQ(ub_addr8_t::VA5, src); | 50 | + EXPECT_EQ(ub_addr8_t::VA6, src); |
| 51 | EXPECT_EQ(repeat, static_cast<uint8_t>(8)); | 51 | EXPECT_EQ(repeat, static_cast<uint8_t>(8)); |
| 52 | EXPECT_EQ(dst_stride, static_cast<uint16_t>(9)); | 52 | EXPECT_EQ(dst_stride, static_cast<uint16_t>(9)); |
| 53 | EXPECT_EQ(src_stride, static_cast<uint16_t>(10)); | 53 | EXPECT_EQ(src_stride, static_cast<uint16_t>(10)); |
| @@ -97,7 +97,7 @@ TEST_F(TestTransto5HDCAPI, asc_transto5hd_b16_repeat_Succ) | |||
| 97 | .times(1) | 97 | .times(1) |
| 98 | .will(invoke(scatter_vnchwconv_b16_stub_repeat)); | 98 | .will(invoke(scatter_vnchwconv_b16_stub_repeat)); |
| 99 | 99 | ||
| 100 | - asc_transto5hd_b16(ub_addr8_t::VA1, ub_addr8_t::VA3, repeat, dst_stride, src_stride); | 100 | + asc_transto5hd_b16(ub_addr8_t::VA2, ub_addr8_t::VA4, repeat, dst_stride, src_stride); |
| 101 | GlobalMockObject::verify(); | 101 | GlobalMockObject::verify(); |
| 102 | } | 102 | } |
| 103 | 103 | ||
| @@ -111,7 +111,7 @@ TEST_F(TestTransto5HDCAPI, asc_transto5hd_b16_repeat_sync_Succ) | |||
| 111 | .times(1) | 111 | .times(1) |
| 112 | .will(invoke(scatter_vnchwconv_b16_stub_repeat)); | 112 | .will(invoke(scatter_vnchwconv_b16_stub_repeat)); |
| 113 | 113 | ||
| 114 | - asc_transto5hd_b16_sync(ub_addr8_t::VA1, ub_addr8_t::VA3, repeat, dst_stride, src_stride); | 114 | + asc_transto5hd_b16_sync(ub_addr8_t::VA2, ub_addr8_t::VA4, repeat, dst_stride, src_stride); |
| 115 | GlobalMockObject::verify(); | 115 | GlobalMockObject::verify(); |
| 116 | } | 116 | } |
| 117 | 117 | ||
| @@ -125,7 +125,7 @@ TEST_F(TestTransto5HDCAPI, asc_transto5hd_b32_repeat_Succ) | |||
| 125 | .times(1) | 125 | .times(1) |
| 126 | .will(invoke(scatter_vnchwconv_b32_stub_repeat)); | 126 | .will(invoke(scatter_vnchwconv_b32_stub_repeat)); |
| 127 | 127 | ||
| 128 | - asc_transto5hd_b32(ub_addr8_t::VA4, ub_addr8_t::VA5, repeat, dst_stride, src_stride); | 128 | + asc_transto5hd_b32(ub_addr8_t::VA4, ub_addr8_t::VA6, repeat, dst_stride, src_stride); |
| 129 | GlobalMockObject::verify(); | 129 | GlobalMockObject::verify(); |
| 130 | } | 130 | } |
| 131 | 131 | ||
| @@ -139,6 +139,6 @@ TEST_F(TestTransto5HDCAPI, asc_transto5hd_b32_repeat_sync_Succ) | |||
| 139 | .times(1) | 139 | .times(1) |
| 140 | .will(invoke(scatter_vnchwconv_b32_stub_repeat)); | 140 | .will(invoke(scatter_vnchwconv_b32_stub_repeat)); |
| 141 | 141 | ||
| 142 | - asc_transto5hd_b32_sync(ub_addr8_t::VA4, ub_addr8_t::VA5, repeat, dst_stride, src_stride); | 142 | + asc_transto5hd_b32_sync(ub_addr8_t::VA4, ub_addr8_t::VA6, repeat, dst_stride, src_stride); |
| 143 | GlobalMockObject::verify(); | 143 | GlobalMockObject::verify(); |
| 144 | } | 144 | } |


_sync 确认是否废弃。