【feat】: Support PCIe Through-ge-AtomGit

Mbase/common/op_tiling/op_tiling_rt2.cc+6-0

	@@ -9,6 +9,7 @@
9	*/	9	*/
10		10
11	#include "nlohmann/json.hpp"	11	#include "nlohmann/json.hpp"
		12	+#include "ge_common/ge_common_api_types.h"
12	#include "op_tiling_rt2.h"	13	#include "op_tiling_rt2.h"
13		14
14	#include <mutex>	15	#include <mutex>
	@@ -41,6 +42,7 @@
41	#include "rt_external_mem.h"	42	#include "rt_external_mem.h"
42	#include "exe_graph/runtime/storage_shape.h"	43	#include "exe_graph/runtime/storage_shape.h"
43	#include "graph/ge_local_context.h"	44	#include "graph/ge_local_context.h"
		45	+#include "graph/ge_context.h"
44	#include "mmpa/mmpa_api.h"	46	#include "mmpa/mmpa_api.h"
45	#include "graph/op_kernel_bin.h"	47	#include "graph/op_kernel_bin.h"
46	#include "common/tbe_handle_store/kernel_store.h"	48	#include "common/tbe_handle_store/kernel_store.h"
	@@ -605,6 +607,9 @@ ge::graphStatus RtParseAndTiling(const ge::Operator &op, const char_t *const com
605	GE_ASSERT_SUCCESS(GetDeterministicConfig(op_desc, deterministic, deterministic_level));	607	GE_ASSERT_SUCCESS(GetDeterministicConfig(op_desc, deterministic, deterministic_level));
606	GELOGI("Get deterministic: %d, deterministic level: %d from node: %s", deterministic, deterministic_level,	608	GELOGI("Get deterministic: %d, deterministic level: %d from node: %s", deterministic, deterministic_level,
607	op_desc->GetName().c_str());	609	op_desc->GetName().c_str());
		610	+ bool pcie_through_flag = false;
		611	+ (void)ge::AttrUtils::GetBool(op_desc, ge::ATTR_NAME_PCIE_THROUGH_FLAG, pcie_through_flag);
		612	+ GELOGI("Get pcie_through_flag: %d from node: %s", pcie_through_flag, op_desc->GetName().c_str());
608		613
609	/*	614	/*
610	* 后续切换OpTilingContextBuilder时，出于兼容性考虑（新GE包+老metadef包），建议deterministic_level的设置通过调用纯C弱符号接口	615	* 后续切换OpTilingContextBuilder时，出于兼容性考虑（新GE包+老metadef包），建议deterministic_level的设置通过调用纯C弱符号接口
	@@ -618,6 +623,7 @@ ge::graphStatus RtParseAndTiling(const ge::Operator &op, const char_t *const com
618	.TilingData(tiling_data.get())	623	.TilingData(tiling_data.get())
619	.Deterministic(deterministic)	624	.Deterministic(deterministic)
620	.DeterministicLevel(deterministic_level)	625	.DeterministicLevel(deterministic_level)
		626	+ .SetPcieThroughFlag(pcie_through_flag)
621	.Workspace(reinterpret_cast<gert::ContinuousVector *>(workspace_size.get()))	627	.Workspace(reinterpret_cast<gert::ContinuousVector *>(workspace_size.get()))
622	.SetSpaceRegistryV2(space_registry, static_cast<gert::OppImplVersionTag>(op_desc->GetOppImplVersion()))	628	.SetSpaceRegistryV2(space_registry, static_cast<gert::OppImplVersionTag>(op_desc->GetOppImplVersion()))
623	.Build(op);	629	.Build(op);

Mbase/common/option_supportion_checker/option_supportion_checker.cc+1-0

	@@ -74,6 +74,7 @@ const std::set<std::string> ge_init_global_options = {
74	TILING_SCHEDULE_OPTIMIZE, GRAPH_MAX_PARALLEL_MODEL_NUM, OPTION_BUILD_CONFIG, ENABLE_SINGLE_STREAM,	74	TILING_SCHEDULE_OPTIMIZE, GRAPH_MAX_PARALLEL_MODEL_NUM, OPTION_BUILD_CONFIG, ENABLE_SINGLE_STREAM,
75	OPTION_HOST_SCHEDULING_MAX_THRESHOLD, OPTION_EXEC_GRAPH_EXEC_TIMEOUT, OP_WAIT_TIMEOUT, OP_EXECUTE_TIMEOUT,	75	OPTION_HOST_SCHEDULING_MAX_THRESHOLD, OPTION_EXEC_GRAPH_EXEC_TIMEOUT, OP_WAIT_TIMEOUT, OP_EXECUTE_TIMEOUT,
76	OPTION_EXEC_ENABLE_ENGINE_PARALLEL, "ge.exec.engineParallelConfigPath", OPTION_MOMORY_POOL_THRESHOLD, ALLOW_HF32,	76	OPTION_EXEC_ENABLE_ENGINE_PARALLEL, "ge.exec.engineParallelConfigPath", OPTION_MOMORY_POOL_THRESHOLD, ALLOW_HF32,
		77	+ OPTION_EXEC_DISABLE_PCIE_THROUGH,
77	// TFA2.x	78	// TFA2.x
78	DETERMINISTIC, "ge.deterministicLevel", ATOMIC_CLEAN_POLICY, OP_DEBUG_CONFIG, "op_debug_option",	79	DETERMINISTIC, "ge.deterministicLevel", ATOMIC_CLEAN_POLICY, OP_DEBUG_CONFIG, "op_debug_option",
79	OPTION_EXEC_ENABLE_EXCEPTION_DUMP, CUSTOMIZE_DTYPES, FUSION_SWITCH_FILE, HCOM_PARALLEL, ENABLE_SMALL_CHANNEL,	80	OPTION_EXEC_ENABLE_EXCEPTION_DUMP, CUSTOMIZE_DTYPES, FUSION_SWITCH_FILE, HCOM_PARALLEL, ENABLE_SMALL_CHANNEL,

Mcompiler/graph/manager/graph_manager.cc+44-0

	@@ -145,6 +145,7 @@
145	#include "common/helper/om2/om2_zip_saver.h"	145	#include "common/helper/om2/om2_zip_saver.h"
146	#include "common/om2/rt_var_resource.h"	146	#include "common/om2/rt_var_resource.h"
147	#include "framework/common/helper/om2_package_helper.h"	147	#include "framework/common/helper/om2_package_helper.h"
		148	+#include "platform/platform_info.h"
148		149
149	namespace ge {	150	namespace ge {
150	namespace {	151	namespace {
	@@ -1229,10 +1230,53 @@ Status GraphManager::ProcessNullableOutput(ComputeGraphPtr &compute_graph) const
1229	return SUCCESS;	1230	return SUCCESS;
1230	}	1231	}
1231		1232
		1233	+Status GraphManager::ProcessPcieThrough(ComputeGraphPtr &compute_graph) const {
		1234	+ std::string disable_pcie_through;
		1235	+ if (GetContext().GetOption(OPTION_EXEC_DISABLE_PCIE_THROUGH, disable_pcie_through) == SUCCESS &&
		1236	+ disable_pcie_through == "1") {
		1237	+ GELOGI("pcie through is disabled by option %s, skip ProcessPcieThrough", OPTION_EXEC_DISABLE_PCIE_THROUGH);
		1238	+ return SUCCESS;
		1239	+ }
		1240	+ fe::PlatFormInfos platform_infos;
		1241	+ fe::OptionalInfos optional_infos;
		1242	+ if (fe::PlatformInfoManager::Instance().GetPlatformInfoWithOutSocVersion(platform_infos, optional_infos) != SUCCESS) {
		1243	+ GELOGW("Failed to get platform info, skip ProcessPcieThrough");
		1244	+ return SUCCESS;
		1245	+ }
		1246	+ std::string pcie_support;
		1247	+ if (!platform_infos.GetPlatformResWithLock("SoCInfo", "pcie_through_partial_support", pcie_support) \|\|
		1248	+ pcie_support != "1") {
		1249	+ GELOGI("platform does not support pcie through (pcie_through_partial_support=%s), skip ProcessPcieThrough",
		1250	+ pcie_support.c_str());
		1251	+ return SUCCESS;
		1252	+ }
		1253	+ for (const auto &node : compute_graph->GetAllNodes()) {
		1254	+ if (node == nullptr \|\| node->GetOpDesc() == nullptr) {
		1255	+ continue;
		1256	+ }
		1257	+ auto op_desc = node->GetOpDesc();
		1258	+ const auto space_registry = gert::DefaultOpImplSpaceRegistryV2::GetInstance().GetSpaceRegistry(
		1259	+ static_cast<gert::OppImplVersionTag>(op_desc->GetOppImplVersion()));
		1260	+ if (space_registry == nullptr) {
		1261	+ continue;
		1262	+ }
		1263	+ const auto op_impl = space_registry->GetOpImpl(op_desc->GetType().c_str());
		1264	+ if (op_impl == nullptr) {
		1265	+ continue;
		1266	+ }
		1267	+ GELOGI("IsSupportPcieThrough: %d", op_impl->IsSupportPcieThrough());
		1268	+ if (op_impl->IsSupportPcieThrough()) {
		1269	+ (void)ge::AttrUtils::SetBool(op_desc, ge::ATTR_NAME_PCIE_THROUGH_FLAG, true);
		1270	+ }
		1271	+ }
		1272	+ return SUCCESS;
		1273	+}
		1274	+
1232	Status GraphManager::PreRunOptimizeSubGraph(const GraphNodePtr &graph_node, ge::ComputeGraphPtr &compute_graph,	1275	Status GraphManager::PreRunOptimizeSubGraph(const GraphNodePtr &graph_node, ge::ComputeGraphPtr &compute_graph,
1233	uint64_t session_id) {	1276	uint64_t session_id) {
1234	GE_CHECK_NOTNULL(graph_node);	1277	GE_CHECK_NOTNULL(graph_node);
1235	GE_CHECK_NOTNULL(compute_graph);	1278	GE_CHECK_NOTNULL(compute_graph);
		1279	+ GM_RUN_AND_DUMP_PERF("ProcessPcieThrough", ProcessPcieThrough, compute_graph);
1236	GM_RUN_AND_DUMP_PERF("ProcessNullableOutput", ProcessNullableOutput, compute_graph);	1280	GM_RUN_AND_DUMP_PERF("ProcessNullableOutput", ProcessNullableOutput, compute_graph);
1237	GM_RUN_AND_DUMP_PERF("OptimizeSubgraph", OptimizeSubgraph, graph_node, compute_graph, session_id);	1281	GM_RUN_AND_DUMP_PERF("OptimizeSubgraph", OptimizeSubgraph, graph_node, compute_graph, session_id);
1238		1282

Mcompiler/graph/manager/graph_manager.h+2-0

	@@ -395,6 +395,8 @@ class GraphManager {
395		395
396	Status ProcessNullableOutput(ComputeGraphPtr &compute_graph) const;	396	Status ProcessNullableOutput(ComputeGraphPtr &compute_graph) const;
397		397
		398	+ Status ProcessPcieThrough(ComputeGraphPtr &compute_graph) const;
		399	+
398	bool CheckModelLoad(const GeRootModelPtr &ge_root_model, bool load_flag) const;	400	bool CheckModelLoad(const GeRootModelPtr &ge_root_model, bool load_flag) const;
399		401
400	bool IsGraphNeedBuild(const GraphNodePtr &graph_node) const;	402	bool IsGraphNeedBuild(const GraphNodePtr &graph_node) const;

Mgraph_metadef/exe_graph/lowering/device_tiling_context_builder.cc+9-0

	@@ -81,6 +81,11 @@ DeviceTilingContextBuilder &DeviceTilingContextBuilder::DeterministicLevel(int32
81	return *this;	81	return *this;
82	}	82	}
83		83
		84	+DeviceTilingContextBuilder &DeviceTilingContextBuilder::SetPcieThroughFlag(bool pcie_through_flag) {
		85	+ pcie_through_flag_ = pcie_through_flag;
		86	+ return *this;
		87	+}
		88	+
84	DeviceTilingContextBuilder &DeviceTilingContextBuilder::TilingData(void *tiling_data) {	89	DeviceTilingContextBuilder &DeviceTilingContextBuilder::TilingData(void *tiling_data) {
85	outputs_[TilingContext::kOutputTilingData] = tiling_data;	90	outputs_[TilingContext::kOutputTilingData] = tiling_data;
86	return *this;	91	return *this;
	@@ -174,6 +179,9 @@ ge::graphStatus DeviceTilingContextBuilder::BuildIOTensors(const ge::OpDesc *con
174	// n-m output shapes	179	// n-m output shapes
175	// m + 1 compile info	180	// m + 1 compile info
176	// m + 2 tiling func	181	// m + 2 tiling func
		182	+// m + 3 deterministic
		183	+// m + 4 deterministic level
		184	+// m + 5 pcie through flag
177	// 其中 n为输入个数总和，m为输入输出个数总和	185	// 其中 n为输入个数总和，m为输入输出个数总和
178	ge::graphStatus DeviceTilingContextBuilder::Build(const ge::NodePtr &node, TiledKernelContextHolder &holder) {	186	ge::graphStatus DeviceTilingContextBuilder::Build(const ge::NodePtr &node, TiledKernelContextHolder &holder) {
179	GE_ASSERT_NOTNULL(platform_info_, " Device platform info addr is nullptr.");	187	GE_ASSERT_NOTNULL(platform_info_, " Device platform info addr is nullptr.");
	@@ -187,6 +195,7 @@ ge::graphStatus DeviceTilingContextBuilder::Build(const ge::NodePtr &node, Tiled
187	inputs_.emplace_back(nullptr);	195	inputs_.emplace_back(nullptr);
188	inputs_.emplace_back(reinterpret_cast<void *>(deterministic_));	196	inputs_.emplace_back(reinterpret_cast<void *>(deterministic_));
189	inputs_.emplace_back(reinterpret_cast<void *>(deterministic_level_));	197	inputs_.emplace_back(reinterpret_cast<void *>(deterministic_level_));
		198	+ inputs_.emplace_back(reinterpret_cast<void *>(pcie_through_flag_));
190		199
191	return TiledBuild(node, holder);	200	return TiledBuild(node, holder);
192	}	201	}

Mgraph_metadef/exe_graph/lowering/tiling_context_builder.cc+9-0

	@@ -54,6 +54,11 @@ TilingContextBuilder &TilingContextBuilder::DeterministicLevel(int32_t determini
54	return *this;	54	return *this;
55	}	55	}
56		56
		57	+TilingContextBuilder &TilingContextBuilder::SetPcieThroughFlag(bool pcie_through_flag) {
		58	+ pcie_through_flag_ = pcie_through_flag;
		59	+ return *this;
		60	+}
		61	+
57	TilingContextBuilder &TilingContextBuilder::TilingData(void *tiling_data) {	62	TilingContextBuilder &TilingContextBuilder::TilingData(void *tiling_data) {
58	outputs_[TilingContext::kOutputTilingData] = tiling_data;	63	outputs_[TilingContext::kOutputTilingData] = tiling_data;
59	return *this;	64	return *this;
	@@ -191,12 +196,16 @@ KernelContextHolder TilingContextBuilder::Build(const ge::Operator &op, ge::grap
191	context_inputs.emplace_back(nullptr);	196	context_inputs.emplace_back(nullptr);
192	context_inputs.emplace_back(reinterpret_cast<void *>(deterministic_));	197	context_inputs.emplace_back(reinterpret_cast<void *>(deterministic_));
193	context_inputs.emplace_back(reinterpret_cast<void *>(deterministic_level_));	198	context_inputs.emplace_back(reinterpret_cast<void *>(deterministic_level_));
		199	+ context_inputs.emplace_back(reinterpret_cast<void *>(pcie_through_flag_));
194	return base_builder_.Inputs(context_inputs).Outputs(outputs_).Build(node->GetOpDesc(), ret);	200	return base_builder_.Inputs(context_inputs).Outputs(outputs_).Build(node->GetOpDesc(), ret);
195	}	201	}
196	// 0-n input tensors	202	// 0-n input tensors
197	// n-m output shapes	203	// n-m output shapes
198	// m + 1 compile info	204	// m + 1 compile info
199	// m + 2 tiling func	205	// m + 2 tiling func
		206	+// m + 3 deterministic
		207	+// m + 4 deterministic level
		208	+// m + 5 pcie through flag
200	// 其中 n为输入个数总和，m为输入输出个数总和	209	// 其中 n为输入个数总和，m为输入输出个数总和
201	KernelContextHolder TilingContextBuilder::Build(const ge::Operator &op) {	210	KernelContextHolder TilingContextBuilder::Build(const ge::Operator &op) {
202	ge::Status ret = ge::GRAPH_FAILED;	211	ge::Status ret = ge::GRAPH_FAILED;

Mgraph_metadef/graph/attr/ge_attr_define.cc+3-0

	@@ -1579,4 +1579,7 @@ const std::string ATTR_NAME_SUPER_KERNEL_OPTIONS = "_super_kernel_options";
1579		1579
1580	// inference rule for torch or other framework with symbols	1580	// inference rule for torch or other framework with symbols
1581	const std::string ATTR_NAME_INFER_RULE = "_inference_rule";	1581	const std::string ATTR_NAME_INFER_RULE = "_inference_rule";
		1582	+
		1583	+// for pcie through
		1584	+const std::string ATTR_NAME_PCIE_THROUGH_FLAG = "_pcie_through_flag";
1582	} // namespace ge	1585	} // namespace ge

Mgraph_metadef/register/op_tiling/op_tiling_py.cc+12-1

	@@ -105,9 +105,10 @@ constexpr uint32_t kRightShiftBits = 4;
105	constexpr uint32_t kAndBits = 15;	105	constexpr uint32_t kAndBits = 15;
106	const std::string kHexDigits = "0123456789ABCDEF";	106	const std::string kHexDigits = "0123456789ABCDEF";
107	constexpr size_t kSize = 4UL;	107	constexpr size_t kSize = 4UL;
108	-constexpr size_t kTilingCtxFixedInputSize = 5UL;	108	+constexpr size_t kTilingCtxFixedInputSize = 6UL;
109	constexpr size_t kDeterministicOffset = 3UL;	109	constexpr size_t kDeterministicOffset = 3UL;
110	constexpr size_t kDeterministicLevelOffset = 4UL;	110	constexpr size_t kDeterministicLevelOffset = 4UL;
		111	+constexpr size_t kPcieThroughOffset = 5UL;
111	const std::string kMaxTilingSize = "op_para_size";	112	const std::string kMaxTilingSize = "op_para_size";
112	constexpr size_t kMaxTilingDataSize = 16UL * 1024UL;	113	constexpr size_t kMaxTilingDataSize = 16UL * 1024UL;
113	constexpr size_t kWorkspaceHolerSize = 8UL;	114	constexpr size_t kWorkspaceHolerSize = 8UL;
	@@ -735,6 +736,10 @@ void ParseExtraInfo(const nlohmann::json &extra_info, ge::OpDescPtr &op_desc) {
735	const int32_t deterministic_level = extra_info["deterministic_level"];	736	const int32_t deterministic_level = extra_info["deterministic_level"];
736	(void)ge::AttrUtils::SetInt(op_desc, "deterministic_level", deterministic_level);	737	(void)ge::AttrUtils::SetInt(op_desc, "deterministic_level", deterministic_level);
737	}	738	}
		739	+ if (extra_info.contains("pcie_through_flag")) {
		740	+ const bool pcie_through_flag = extra_info["pcie_through_flag"];
		741	+ (void)ge::AttrUtils::SetBool(op_desc, ge::ATTR_NAME_PCIE_THROUGH_FLAG, pcie_through_flag);
		742	+ }
738	if (extra_info.contains(ge::public_attr::OP_AI_CORE_NUM)) {	743	if (extra_info.contains(ge::public_attr::OP_AI_CORE_NUM)) {
739	const std::string op_aicore_num = extra_info[ge::public_attr::OP_AI_CORE_NUM];	744	const std::string op_aicore_num = extra_info[ge::public_attr::OP_AI_CORE_NUM];
740	GELOGI("Set op_aicore_num from extra info: %s", op_aicore_num.c_str());	745	GELOGI("Set op_aicore_num from extra info: %s", op_aicore_num.c_str());
	@@ -1706,6 +1711,12 @@ gert::KernelContextHolder BuildTilingContext(ContextComponent &context_com, gert
1706	GELOGI("Get deterministic level: %d from node: %s", deterministic_level, context_com.op_desc->GetName().c_str());	1711	GELOGI("Get deterministic level: %d from node: %s", deterministic_level, context_com.op_desc->GetName().c_str());
1707	tiling_context_inputs[context_com.storage_shapes.size() + kDeterministicLevelOffset] =	1712	tiling_context_inputs[context_com.storage_shapes.size() + kDeterministicLevelOffset] =
1708	reinterpret_cast<void *>(deterministic_level);	1713	reinterpret_cast<void *>(deterministic_level);
		1714	+
		1715	+ bool pcie_through_flag = false;
		1716	+ (void)ge::AttrUtils::GetBool(context_com.op_desc, ge::ATTR_NAME_PCIE_THROUGH_FLAG, pcie_through_flag);
		1717	+ tiling_context_inputs[context_com.storage_shapes.size() + kPcieThroughOffset] =
		1718	+ reinterpret_cast<void *>(pcie_through_flag);
		1719	+ GELOGI("Get pcie_through_flag: %d from node: %s", pcie_through_flag, context_com.op_desc->GetName().c_str());
1709	return gert::KernelRunContextBuilder()	1720	return gert::KernelRunContextBuilder()
1710	.Inputs(tiling_context_inputs)	1721	.Inputs(tiling_context_inputs)
1711	.Outputs({nullptr, nullptr, &context_com.atomic_flag, context_com.tiling_data.get(),	1722	.Outputs({nullptr, nullptr, &context_com.atomic_flag, context_com.tiling_data.get(),

Minc/graph_metadef/exe_graph/lowering/device_tiling_context_builder.h+2-0

	@@ -40,6 +40,7 @@ class DeviceTilingContextBuilder {
40	DeviceTilingContextBuilder &CompileInfo(void *compile_info);	40	DeviceTilingContextBuilder &CompileInfo(void *compile_info);
41	DeviceTilingContextBuilder &Deterministic(int32_t deterministic);	41	DeviceTilingContextBuilder &Deterministic(int32_t deterministic);
42	DeviceTilingContextBuilder &DeterministicLevel(int32_t deterministic_level);	42	DeviceTilingContextBuilder &DeterministicLevel(int32_t deterministic_level);
		43	+ DeviceTilingContextBuilder &SetPcieThroughFlag(bool pcie_through_flag);
43	DeviceTilingContextBuilder &PlatformInfo(void *platform_info);	44	DeviceTilingContextBuilder &PlatformInfo(void *platform_info);
44	DeviceTilingContextBuilder &TilingData(void *tiling_data);	45	DeviceTilingContextBuilder &TilingData(void *tiling_data);
45	DeviceTilingContextBuilder &AddrRefreshedInputTensor(const std::map<size_t, AddrRefreshedTensor> &index_to_tensor);	46	DeviceTilingContextBuilder &AddrRefreshedInputTensor(const std::map<size_t, AddrRefreshedTensor> &index_to_tensor);
	@@ -58,6 +59,7 @@ class DeviceTilingContextBuilder {
58	void *platform_info_{nullptr};	59	void *platform_info_{nullptr};
59	int32_t deterministic_{0};	60	int32_t deterministic_{0};
60	int32_t deterministic_level_{0};	61	int32_t deterministic_level_{0};
		62	+ bool pcie_through_flag_{false};
61	uint64_t dev_begin_{0UL};	63	uint64_t dev_begin_{0UL};
62	uint8_t *host_begin_{nullptr};	64	uint8_t *host_begin_{nullptr};
63	size_t max_mem_size_{0UL};	65	size_t max_mem_size_{0UL};

Minc/graph_metadef/exe_graph/lowering/tiling_context_builder.h+2-0

Minc/graph_metadef/external/ge_common/ge_common_api_types.h+1-0

	@@ -61,6 +61,7 @@ const char_t *const OPTION_EXEC_PROFILING_OPTIONS = "ge.exec.profilingOptions";
61	const char_t *const OPTION_EXEC_HCCL_FLAG = "ge.exec.hcclFlag";	61	const char_t *const OPTION_EXEC_HCCL_FLAG = "ge.exec.hcclFlag";
62	const char_t *const OPTION_EXEC_ATOMIC_FLAG = "ge.exec.enable_atomic";	62	const char_t *const OPTION_EXEC_ATOMIC_FLAG = "ge.exec.enable_atomic";
63	const char_t *const OPTION_EXEC_DISABLE_REUSED_MEMORY = "ge.exec.disableReuseMemory";	63	const char_t *const OPTION_EXEC_DISABLE_REUSED_MEMORY = "ge.exec.disableReuseMemory";
		64	+const char_t *const OPTION_EXEC_DISABLE_PCIE_THROUGH = "ge.exec.disable_pcie_through";
64	const char_t *const OPTION_EXEC_ENABLE_TAILING_OPTIMIZATION = "ge.exec.isTailingOptimization";	65	const char_t *const OPTION_EXEC_ENABLE_TAILING_OPTIMIZATION = "ge.exec.isTailingOptimization";
65	// Dynamic input flag. ge.exec.dynamicInput=1, means enable dynaimc input,	66	// Dynamic input flag. ge.exec.dynamicInput=1, means enable dynaimc input,
66	// ge.exec.dynamicGraphExecuteMode, dynamic_execute[default]	67	// ge.exec.dynamicGraphExecuteMode, dynamic_execute[default]

Minc/graph_metadef/graph/debug/ge_attr_define.h+2-0

	@@ -1570,6 +1570,8 @@ GE_FUNC_DEV_VISIBILITY GE_FUNC_HOST_VISIBILITY extern const std::string ATTR_NAM
1570	GE_FUNC_DEV_VISIBILITY GE_FUNC_HOST_VISIBILITY extern const std::string ATTR_NAME_SUPER_KERNEL_OPTIONS;	1570	GE_FUNC_DEV_VISIBILITY GE_FUNC_HOST_VISIBILITY extern const std::string ATTR_NAME_SUPER_KERNEL_OPTIONS;
1571	// inference rule for torch or other framework with symbols	1571	// inference rule for torch or other framework with symbols
1572	GE_FUNC_DEV_VISIBILITY GE_FUNC_HOST_VISIBILITY extern const std::string ATTR_NAME_INFER_RULE;	1572	GE_FUNC_DEV_VISIBILITY GE_FUNC_HOST_VISIBILITY extern const std::string ATTR_NAME_INFER_RULE;
		1573	+// for pcie through
		1574	+GE_FUNC_DEV_VISIBILITY GE_FUNC_HOST_VISIBILITY extern const std::string ATTR_NAME_PCIE_THROUGH_FLAG;
1573	} // namespace ge	1575	} // namespace ge
1574		1576
1575	/lint +e618/	1577	/lint +e618/

Mruntime/v1/graph/load/model_manager/task_info/args_format/args_format_utils.cc+5-0

	@@ -12,6 +12,7 @@
12		12
13	#include "common/op_tiling/op_tiling_rt2.h"	13	#include "common/op_tiling/op_tiling_rt2.h"
14	#include "graph/ge_local_context.h"	14	#include "graph/ge_local_context.h"
		15	+#include "graph/debug/ge_attr_define.h"
15	#include "register/hidden_inputs_func_registry.h"	16	#include "register/hidden_inputs_func_registry.h"
16	#include "graph/args_format_desc.h"	17	#include "graph/args_format_desc.h"
17	#include "exe_graph/lowering/bg_kernel_context_extend.h"	18	#include "exe_graph/lowering/bg_kernel_context_extend.h"
	@@ -146,11 +147,15 @@ Status ArgsFormatUtils::SinkTilingContext(const NodePtr &node, DavinciModel &dav
146	node->GetName().c_str());	147	node->GetName().c_str());
147		148
148	auto context_builder = gert::DeviceTilingContextBuilder();	149	auto context_builder = gert::DeviceTilingContextBuilder();
		150	+ bool pcie_through_flag = false;
		151	+ (void)ge::AttrUtils::GetBool(node->GetOpDesc(), ge::ATTR_NAME_PCIE_THROUGH_FLAG, pcie_through_flag);
		152	+ GELOGI("Get pcie_through_flag:[%d] from node:%s", pcie_through_flag, node->GetName().c_str());
149	Status ret =	153	Status ret =
150	context_builder.PlatformInfo(platform_infos_addr)	154	context_builder.PlatformInfo(platform_infos_addr)
151	.TilingData(device_addr)	155	.TilingData(device_addr)
152	.Deterministic(deterministic)	156	.Deterministic(deterministic)
153	.DeterministicLevel(deterministic_level)	157	.DeterministicLevel(deterministic_level)
		158	+ .SetPcieThroughFlag(pcie_through_flag)
154	.Workspace(ValueToPtr(PtrToValue(device_addr) + aligned_tiling_size))	159	.Workspace(ValueToPtr(PtrToValue(device_addr) + aligned_tiling_size))
155	.AddrRefreshedInputTensor(index_to_tensor)	160	.AddrRefreshedInputTensor(index_to_tensor)
156	.TiledHolder(context_host_begin, context_dev_begin, aligned_tiling_context_size + compute_node_info_size)	161	.TiledHolder(context_host_begin, context_dev_begin, aligned_tiling_context_size + compute_node_info_size)

Mruntime/v2/engine/aicore/converter/aicore_node_converter.cc+17-13

	@@ -132,9 +132,10 @@ RunCfg CollectRunConfig(const ge::NodePtr &node, const LowerInput &lower_input,
132	GELOGE(ge::INTERNAL_ERROR, "platform_info is nullptr! Node: %s.", node->GetName().c_str());	132	GELOGE(ge::INTERNAL_ERROR, "platform_info is nullptr! Node: %s.", node->GetName().c_str());
133	return run_cfg;	133	return run_cfg;
134	}	134	}
135	- auto tiling_ret = bg::Tiling(	135	+ auto tiling_ret =
136	- node, lower_input.input_shapes, output_shapes,	136	+ bg::Tiling(node, lower_input.input_shapes, output_shapes,
137	- {platform_info, *(lower_input.global_data), launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)]});	137	+ {platform_info, *(lower_input.global_data),
		138	+ launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)], lower_input.input_addrs});
138	run_cfg.tiling_input_launch_arg = tiling_ret[static_cast<size_t>(kernel::TilingExOutputIndex::kRtArg)];	139	run_cfg.tiling_input_launch_arg = tiling_ret[static_cast<size_t>(kernel::TilingExOutputIndex::kRtArg)];
139	run_cfg.block_dim = tiling_ret[TilingContext::kOutputBlockDim];	140	run_cfg.block_dim = tiling_ret[TilingContext::kOutputBlockDim];
140	run_cfg.schedule_mode = tiling_ret[TilingContext::kOutputScheduleMode];	141	run_cfg.schedule_mode = tiling_ret[TilingContext::kOutputScheduleMode];
	@@ -820,16 +821,18 @@ static std::vector<bg::DevMemValueHolderPtr> LoweringWithHandleProc(const ge::No
820	return {};	821	return {};
821	}	822	}
822	if (!NodeSupportRollback(node)) {	823	if (!NodeSupportRollback(node)) {
823	- proc_arg.tiling_ret = bg::Tiling(node, lower_input.input_shapes, output_shapes,	824	+ proc_arg.tiling_ret =
824	- {platform_info, *(lower_input.global_data),	825	+ bg::Tiling(node, lower_input.input_shapes, output_shapes,
825	- proc_arg.launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)]});	826	+ {platform_info, *(lower_input.global_data),
		827	+ proc_arg.launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)], lower_input.input_addrs});
826	CHECK_HOLDERS_ALL_OK_RET(proc_arg.tiling_ret, static_cast<size_t>(kernel::TilingExOutputIndex::kNum), return {});	828	CHECK_HOLDERS_ALL_OK_RET(proc_arg.tiling_ret, static_cast<size_t>(kernel::TilingExOutputIndex::kNum), return {});
827	output_addrs = AicoreProcWithHandle(node, lower_input, output_shapes, proc_arg);	829	output_addrs = AicoreProcWithHandle(node, lower_input, output_shapes, proc_arg);
828	} else {	830	} else {
829	GELOGD("Lowering with rollback of aicpu.");	831	GELOGD("Lowering with rollback of aicpu.");
830	- proc_arg.tiling_ret = bg::FallibleTiling(node, lower_input.input_shapes, output_shapes,	832	+ proc_arg.tiling_ret = bg::FallibleTiling(
831	- {platform_info, *(lower_input.global_data),	833	+ node, lower_input.input_shapes, output_shapes,
832	- proc_arg.launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)]});	834	+ {platform_info, *(lower_input.global_data),
		835	+ proc_arg.launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)], lower_input.input_addrs});
833	CHECK_HOLDERS_ALL_OK_RET(proc_arg.tiling_ret,	836	CHECK_HOLDERS_ALL_OK_RET(proc_arg.tiling_ret,
834	static_cast<size_t>(kernel::FallibleTilingExOutputIndex::kFallibleOutputNum), return {});	837	static_cast<size_t>(kernel::FallibleTilingExOutputIndex::kFallibleOutputNum), return {});
835	output_addrs = bg::If<bg::DevMemValueHolder>(	838	output_addrs = bg::If<bg::DevMemValueHolder>(
	@@ -994,7 +997,7 @@ static std::vector<bg::ValueHolderPtr> WithFlagTilingProc(const ge::NodePtr &nod
994	}	997	}
995	return bg::Tiling(node, lower_input.input_shapes, output_shapes,	998	return bg::Tiling(node, lower_input.input_shapes, output_shapes,
996	{platform_info, *(lower_input.global_data),	999	{platform_info, *(lower_input.global_data),
997	- proc_arg.launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)]});	1000	+ proc_arg.launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)], lower_input.input_addrs});
998	}	1001	}
999		1002
1000	static std::vector<bg::DevMemValueHolderPtr> LoweringWithFlagProc(const ge::NodePtr &node,	1003	static std::vector<bg::DevMemValueHolderPtr> LoweringWithFlagProc(const ge::NodePtr &node,
	@@ -1017,9 +1020,10 @@ static std::vector<bg::DevMemValueHolderPtr> LoweringWithFlagProc(const ge::Node
1017	output_addrs = AicoreProcWithFlag(node, lower_input, output_shapes, proc_arg);	1020	output_addrs = AicoreProcWithFlag(node, lower_input, output_shapes, proc_arg);
1018	} else {	1021	} else {
1019	GELOGD("Lowering with rollback of aicpu.");	1022	GELOGD("Lowering with rollback of aicpu.");
1020	- proc_arg.tiling_ret = bg::FallibleTiling(node, lower_input.input_shapes, output_shapes,	1023	+ proc_arg.tiling_ret = bg::FallibleTiling(
1021	- {platform_info, *(lower_input.global_data),	1024	+ node, lower_input.input_shapes, output_shapes,
1022	- proc_arg.launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)]});	1025	+ {platform_info, *(lower_input.global_data),
		1026	+ proc_arg.launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)], lower_input.input_addrs});
1023	CHECK_HOLDERS_ALL_OK_RET(proc_arg.tiling_ret,	1027	CHECK_HOLDERS_ALL_OK_RET(proc_arg.tiling_ret,
1024	static_cast<size_t>(kernel::FallibleTilingExOutputIndex::kFallibleOutputNum), return {});	1028	static_cast<size_t>(kernel::FallibleTilingExOutputIndex::kFallibleOutputNum), return {});
1025	output_addrs = bg::If<bg::DevMemValueHolder>(	1029	output_addrs = bg::If<bg::DevMemValueHolder>(

Mruntime/v2/engine/aicore/converter/autofuse_node_converter.cc+2-1

	@@ -196,7 +196,8 @@ LowerResult LoweringAutofuseNode(const ge::NodePtr &node, const LowerInput &lowe
196	CONVERTER_CHECK_HOLDERS_ALL_OK(launch_arg, static_cast<size_t>(AllocLaunchArgOutputs::kNum));	196	CONVERTER_CHECK_HOLDERS_ALL_OK(launch_arg, static_cast<size_t>(AllocLaunchArgOutputs::kNum));
197	auto tiling_results =	197	auto tiling_results =
198	bg::Tiling(node, input_data_shape_handlers, output_shapes,	198	bg::Tiling(node, input_data_shape_handlers, output_shapes,
199	- {platform_info, *global_data, launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)]});	199	+ {platform_info, *global_data, launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)],
		200	+ lower_input.input_addrs});
200	CONVERTER_CHECK_HOLDERS_ALL_OK(tiling_results, static_cast<size_t>(kernel::TilingExOutputIndex::kNum));	201	CONVERTER_CHECK_HOLDERS_ALL_OK(tiling_results, static_cast<size_t>(kernel::TilingExOutputIndex::kNum));
201		202
202	// launch	203	// launch

Mruntime/v2/graph_builder/bg_tiling.cc+71-3

	@@ -33,6 +33,7 @@
33	#include "graph/utils/op_type_utils.h"	33	#include "graph/utils/op_type_utils.h"
34	#include "exe_graph/lowering/data_dependent_interpreter.h"	34	#include "exe_graph/lowering/data_dependent_interpreter.h"
35	#include "graph/ge_context.h"	35	#include "graph/ge_context.h"
		36	+#include "acl/acl_rt.h"
36	#include "common/op_tiling/op_tiling_rt2.h"	37	#include "common/op_tiling/op_tiling_rt2.h"
37	#include "common/op_tiling/tiling_dfx.h"	38	#include "common/op_tiling/tiling_dfx.h"
38	#include "rt_external_model.h"	39	#include "rt_external_model.h"
	@@ -44,6 +45,39 @@
44	namespace gert {	45	namespace gert {
45	namespace bg {	46	namespace bg {
46	namespace {	47	namespace {
		48	+
		49	+bool IsPcieThroughEnabled() {
		50	+ std::string disable_pcie_through;
		51	+ if (ge::GetContext().GetOption("ge.exec.disable_pcie_through", disable_pcie_through) == ge::GRAPH_SUCCESS &&
		52	+ disable_pcie_through == "1") {
		53	+ GELOGI("pcie through is disabled by option ge.exec.disable_pcie_through");
		54	+ return false;
		55	+ }
		56	+ fe::PlatFormInfos platform_infos;
		57	+ if (fe::PlatformInfoManager::Instance().GetPlatformInstanceByDevice(0U, platform_infos) != 0) {
		58	+ GELOGW("GetPlatformInstanceByDevice failed");
		59	+ return false;
		60	+ }
		61	+ std::string pcie_support;
		62	+ if (!platform_infos.GetPlatformResWithLock("SoCInfo", "pcie_through_partial_support", pcie_support) \|\|
		63	+ pcie_support != "1") {
		64	+ return false;
		65	+ }
		66	+ GELOGD("pcie_support:[%s]", pcie_support.c_str());
		67	+ int32_t device_id = -1;
		68	+ if (aclrtGetDevice(&device_id) != ACL_SUCCESS) {
		69	+ return false;
		70	+ }
		71	+ int64_t connect_type = -1;
		72	+ if (aclrtGetDeviceInfo(static_cast<uint32_t>(device_id), ACL_DEV_ATTR_HD_CONNECT_TYPE, &connect_type) !=
		73	+ ACL_SUCCESS \|\|
		74	+ connect_type != static_cast<int64_t>(ACL_HOST_DEVICE_CONNECT_TYPE_PCIE)) {
		75	+ return false;
		76	+ }
		77	+ GELOGI("device_id: %d, connect_type:%" PRId64 "", device_id, connect_type);
		78	+ return true;
		79	+}
		80	+
47	struct TilingAppendDfxInfoInputs {	81	struct TilingAppendDfxInfoInputs {
48	const std::vector<ValueHolderPtr> &input_shapes;	82	const std::vector<ValueHolderPtr> &input_shapes;
49	const std::vector<ValueHolderPtr> &output_shapes;	83	const std::vector<ValueHolderPtr> &output_shapes;
	@@ -270,6 +304,34 @@ ge::Status BuildTilingDeterministicInput(const ge::NodePtr &node, LoweringGlobal
270	return ge::SUCCESS;	304	return ge::SUCCESS;
271	}	305	}
272		306
		307	+ge::Status BuildTilingPcieThroughInput(const ge::NodePtr &node, std::vector<ValueHolderPtr> &tiling_input,
		308	+ const std::vector<bg::DevMemValueHolderPtr> &input_addrs) {
		309	+ GE_ASSERT_NOTNULL(node);
		310	+ GE_ASSERT_NOTNULL(node->GetOpDesc());
		311	+ thread_local static bool env_enabled = IsPcieThroughEnabled();
		312	+ bool pcie_through_flag = false;
		313	+ const auto space_registry = gert::DefaultOpImplSpaceRegistryV2::GetInstance().GetSpaceRegistry(
		314	+ static_cast<gert::OppImplVersionTag>(node->GetOpDesc()->GetOppImplVersion()));
		315	+ if (space_registry != nullptr) {
		316	+ const auto *op_impl = space_registry->GetOpImpl(node->GetTypePtr());
		317	+ if (op_impl != nullptr && op_impl->IsSupportPcieThrough() && env_enabled) {
		318	+ pcie_through_flag = true;
		319	+ }
		320	+ }
		321	+ GELOGI("pcie_through_flag initial:[%d], node:%s", pcie_through_flag, node->GetName().c_str());
		322	+ if (pcie_through_flag && !input_addrs.empty()) {
		323	+ auto check_holder = bg::ValueHolder::CreateSingleDataOutput("CheckPcieThrough",
		324	+ ConvertDevMemValueHoldersToValueHolders(input_addrs));
		325	+ GE_ASSERT_NOTNULL(check_holder);
		326	+ tiling_input.emplace_back(check_holder);
		327	+ } else {
		328	+ auto pcie_through_holder = bg::ValueHolder::CreateConst(&pcie_through_flag, sizeof(bool));
		329	+ GE_ASSERT_NOTNULL(pcie_through_holder);
		330	+ tiling_input.emplace_back(pcie_through_holder);
		331	+ }
		332	+ return ge::SUCCESS;
		333	+}
		334	+
273	bg::ValueHolderPtr BuildSymbolTilingCacheKey(const std::vector<bg::ValueHolderPtr> &input_shapes,	335	bg::ValueHolderPtr BuildSymbolTilingCacheKey(const std::vector<bg::ValueHolderPtr> &input_shapes,
274	const ge::NodePtr &node, const TilingLowerInput &lower_inputs) {	336	const ge::NodePtr &node, const TilingLowerInput &lower_inputs) {
275	std::vector<bg::ValueHolderPtr> inputs_holders;	337	std::vector<bg::ValueHolderPtr> inputs_holders;
	@@ -625,9 +687,9 @@ ge::Status BuildTilingAppendDfxInfo(const ge::NodePtr &node, std::vector<ValueHo
625	return ge::SUCCESS;	687	return ge::SUCCESS;
626	}	688	}
627		689
628	-/* +--> Tiling <---+-----------------+----------------+------------------------+	690	+/* +--> Tiling <---+-----------------+----------------+------------------------+-------------+
629	- * / \| \ \ \ \	691	+ * / \| \ \ \ \ \
630	- * <input-shapes> <output-shapes> TilingParse PlatformInfo PrepareTilingFrameworkData Deterministic	692	+ * <input-shapes> <output-shapes> TilingParse PlatformInfo PrepareTilingFrameworkData Deterministic PcieThrough
631	* / / \ / \	693	* / / \ / \
632	* space_registry json \ FindTilingFunc (向后可扩展框架内部FwkData输入)	694	* space_registry json \ FindTilingFunc (向后可扩展框架内部FwkData输入)
633	* \ / \	695	* \ / \
	@@ -652,6 +714,7 @@ std::vector<ValueHolderPtr> Tiling(const ge::NodePtr &node, const std::vector<Va
652	GE_ASSERT_SUCCESS(	714	GE_ASSERT_SUCCESS(
653	BuildCacheableTilingFwkDataInputs(node, lower_inputs, 0U, "BuildSymbolTilingCacheKey", inputs_holders));	715	BuildCacheableTilingFwkDataInputs(node, lower_inputs, 0U, "BuildSymbolTilingCacheKey", inputs_holders));
654	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(node, lower_inputs.global_data, inputs_holders));	716	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(node, lower_inputs.global_data, inputs_holders));
		717	+ GE_ASSERT_SUCCESS(BuildTilingPcieThroughInput(node, inputs_holders, lower_inputs.input_addrs));
655	return bg::ValueHolder::CreateDataOutput("CacheableTiling", inputs_holders, tiling_output_num);	718	return bg::ValueHolder::CreateDataOutput("CacheableTiling", inputs_holders, tiling_output_num);
656	}	719	}
657	GE_ASSERT_NOTNULL(node);	720	GE_ASSERT_NOTNULL(node);
	@@ -676,10 +739,12 @@ std::vector<ValueHolderPtr> Tiling(const ge::NodePtr &node, const std::vector<Va
676	GE_ASSERT_SUCCESS(BuildCacheableTilingFwkDataInputs(node, lower_inputs, data_dependency,	739	GE_ASSERT_SUCCESS(BuildCacheableTilingFwkDataInputs(node, lower_inputs, data_dependency,
677	"BuildGeneralTilingCacheKey", tiling_input));	740	"BuildGeneralTilingCacheKey", tiling_input));
678	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(node, lower_inputs.global_data, tiling_input));	741	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(node, lower_inputs.global_data, tiling_input));
		742	+ GE_ASSERT_SUCCESS(BuildTilingPcieThroughInput(node, tiling_input, lower_inputs.input_addrs));
679	tiling_ret = ValueHolder::CreateDataOutput("CacheableTiling", tiling_input, tiling_output_num);	743	tiling_ret = ValueHolder::CreateDataOutput("CacheableTiling", tiling_input, tiling_output_num);
680	} else {	744	} else {
681	GE_ASSERT_SUCCESS(BuildTilingFwkDataInputs(node, lower_inputs, tiling_input));	745	GE_ASSERT_SUCCESS(BuildTilingFwkDataInputs(node, lower_inputs, tiling_input));
682	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(node, lower_inputs.global_data, tiling_input));	746	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(node, lower_inputs.global_data, tiling_input));
		747	+ GE_ASSERT_SUCCESS(BuildTilingPcieThroughInput(node, tiling_input, lower_inputs.input_addrs));
683	tiling_ret = ValueHolder::CreateDataOutput("Tiling", tiling_input, tiling_output_num);	748	tiling_ret = ValueHolder::CreateDataOutput("Tiling", tiling_input, tiling_output_num);
684	}	749	}
685		750
	@@ -730,10 +795,12 @@ std::vector<ValueHolderPtr> FallibleTiling(const ge::NodePtr &node, const std::v
730	GE_ASSERT_SUCCESS(BuildCacheableTilingFwkDataInputs(node, lower_inputs, data_dependency,	795	GE_ASSERT_SUCCESS(BuildCacheableTilingFwkDataInputs(node, lower_inputs, data_dependency,
731	"BuildGeneralTilingCacheKey", tiling_input));	796	"BuildGeneralTilingCacheKey", tiling_input));
732	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(node, lower_inputs.global_data, tiling_input));	797	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(node, lower_inputs.global_data, tiling_input));
		798	+ GE_ASSERT_SUCCESS(BuildTilingPcieThroughInput(node, tiling_input, lower_inputs.input_addrs));
733	tiling_ret = ValueHolder::CreateDataOutput("CacheableFallibleTiling", tiling_input, fallible_output_num);	799	tiling_ret = ValueHolder::CreateDataOutput("CacheableFallibleTiling", tiling_input, fallible_output_num);
734	} else {	800	} else {
735	GE_ASSERT_SUCCESS(BuildTilingFwkDataInputs(node, lower_inputs, tiling_input));	801	GE_ASSERT_SUCCESS(BuildTilingFwkDataInputs(node, lower_inputs, tiling_input));
736	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(node, lower_inputs.global_data, tiling_input));	802	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(node, lower_inputs.global_data, tiling_input));
		803	+ GE_ASSERT_SUCCESS(BuildTilingPcieThroughInput(node, tiling_input, lower_inputs.input_addrs));
737	tiling_ret = ValueHolder::CreateDataOutput("FallibleTiling", tiling_input, fallible_output_num);	804	tiling_ret = ValueHolder::CreateDataOutput("FallibleTiling", tiling_input, fallible_output_num);
738	}	805	}
739		806
	@@ -770,6 +837,7 @@ std::vector<ValueHolderPtr> TilingForAtomic(const ge::NodePtr &atomic_node, cons
770	}	837	}
771	inputs.emplace_back(ValueHolder::CreateSingleDataOutput("PrepareTilingFwkData", {tiling_func, launch_arg}));	838	inputs.emplace_back(ValueHolder::CreateSingleDataOutput("PrepareTilingFwkData", {tiling_func, launch_arg}));
772	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(atomic_node, global_data, inputs));	839	GE_ASSERT_SUCCESS(BuildTilingDeterministicInput(atomic_node, global_data, inputs));
		840	+ GE_ASSERT_SUCCESS(BuildTilingPcieThroughInput(atomic_node, inputs, {}));
773	return ValueHolder::CreateDataOutput("Tiling", inputs, static_cast<size_t>(kernel::TilingExOutputIndex::kNum));	841	return ValueHolder::CreateDataOutput("Tiling", inputs, static_cast<size_t>(kernel::TilingExOutputIndex::kNum));
774	}	842	}
775		843

Mruntime/v2/graph_builder/bg_tiling.h+1-0

	@@ -34,6 +34,7 @@ struct TilingLowerInput {
34	ValueHolderPtr platform_info;	34	ValueHolderPtr platform_info;
35	LoweringGlobalData &global_data;	35	LoweringGlobalData &global_data;
36	ValueHolderPtr launch_arg;	36	ValueHolderPtr launch_arg;
		37	+ const std::vector<bg::DevMemValueHolderPtr> input_addrs;
37	};	38	};
38		39
39	void DebugForArgsInfo(const ge::NodePtr &compute_node, const std::vector<ArgsInfo> &args_infos,	40	void DebugForArgsInfo(const ge::NodePtr &compute_node, const std::vector<ArgsInfo> &args_infos,

Mruntime/v2/graph_builder/optiling_converter.cc+4-3

	@@ -78,9 +78,10 @@ LowerResult LoweringOpTiling(const ge::NodePtr &node, const LowerInput &lower_in
78	GE_ASSERT_TRUE(assembled_platform_info_holders.size() == static_cast<size_t>(bg::AssemblePlatformInfoIndex::kNums));	78	GE_ASSERT_TRUE(assembled_platform_info_holders.size() == static_cast<size_t>(bg::AssemblePlatformInfoIndex::kNums));
79	auto platform_info =	79	auto platform_info =
80	assembled_platform_info_holders[static_cast<size_t>(bg::AssemblePlatformInfoIndex::kPlatformInfo)];	80	assembled_platform_info_holders[static_cast<size_t>(bg::AssemblePlatformInfoIndex::kPlatformInfo)];
81	- auto tiling_ret = bg::Tiling(	81	+ auto tiling_ret =
82	- tiling_node, lower_input.input_shapes, output_shapes,	82	+ bg::Tiling(tiling_node, lower_input.input_shapes, output_shapes,
83	- {platform_info, *(lower_input.global_data), launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)]});	83	+ {platform_info, *(lower_input.global_data),
		84	+ launch_arg[static_cast<size_t>(AllocLaunchArgOutputs::kRtArg)], lower_input.input_addrs});
84	bg::ValueHolder::GetCurrentFrame()->SetCurrentComputeNode(current_node);	85	bg::ValueHolder::GetCurrentFrame()->SetCurrentComputeNode(current_node);
85		86
86	lower_ret.out_shapes = bg::ValueHolder::CreateDataOutput("BuildOpTilingOutputShape", tiling_ret, kOpTilingOutputSize);	87	lower_ret.out_shapes = bg::ValueHolder::CreateDataOutput("BuildOpTilingOutputShape", tiling_ret, kOpTilingOutputSize);

Mruntime/v2/kernel/common_kernel_impl/tiling.cc+57-0

	@@ -9,6 +9,9 @@
9	*/	9	*/
10		10
11	#include "tiling.h"	11	#include "tiling.h"
		12	+#include <vector>
		13	+#include "acl/acl_rt.h"
		14	+#include "register/op_impl_kernel_registry.h"
12	#include "register/kernel_registry.h"	15	#include "register/kernel_registry.h"
13	#include "base/registry/op_impl_space_registry_v2.h"	16	#include "base/registry/op_impl_space_registry_v2.h"
14	#include "graph/utils/math_util.h"	17	#include "graph/utils/math_util.h"
	@@ -24,6 +27,7 @@
24	#include "kernel/kernel_log.h"	27	#include "kernel/kernel_log.h"
25	#include "aicore/launch_kernel/rt_kernel_launch_args_ex.h"	28	#include "aicore/launch_kernel/rt_kernel_launch_args_ex.h"
26	#include "aicore/converter/autofuse_node_converter.h"	29	#include "aicore/converter/autofuse_node_converter.h"
		30	+#include "exe_graph/runtime/gert_tensor_data.h"
27		31
28	namespace gert {	32	namespace gert {
29	namespace kernel {	33	namespace kernel {
	@@ -41,6 +45,52 @@ constexpr size_t kFwkDataOffset =
41	constexpr size_t kTilingCacheSizePerOp = 120UL;	45	constexpr size_t kTilingCacheSizePerOp = 120UL;
42	constexpr size_t kTilingCacheEvictNum = 8UL;	46	constexpr size_t kTilingCacheEvictNum = 8UL;
43		47
		48	+ge::graphStatus CheckPcieThrough(KernelContext *context) {
		49	+ auto *output = context->GetOutputPointer<bool>(0U);
		50	+ GE_ASSERT_NOTNULL(output);
		51	+ *output = false;
		52	+ uint32_t count = 0U;
		53	+ if (aclrtHostGetDevicePointerAddrRange(nullptr, &count) != ACL_SUCCESS \|\| count == 0U) {
		54	+ GELOGI("CheckPcieThrough: aclrtHostGetDevicePointerAddrRange returned count=0 or failed");
		55	+ return ge::GRAPH_SUCCESS;
		56	+ }
		57	+ GELOGI("CheckPcieThrough: pcie addr range count:[%u]", count);
		58	+ std::vector<aclrtAddrRange> ranges(count);
		59	+ if (aclrtHostGetDevicePointerAddrRange(ranges.data(), &count) != ACL_SUCCESS) {
		60	+ GELOGI("CheckPcieThrough: aclrtHostGetDevicePointerAddrRange failed to get ranges");
		61	+ return ge::GRAPH_SUCCESS;
		62	+ }
		63	+ const auto input_num = context->GetInputNum();
		64	+ GELOGD("CheckPcieThrough: input_num:[%zu]", input_num);
		65	+ for (size_t i = 0U; i < input_num; ++i) {
		66	+ auto tensor_data = context->GetInputValue<gert::GertTensorData >(i);
		67	+ if (tensor_data == nullptr) {
		68	+ GELOGI("CheckPcieThrough: input idx:[%zu] tensor_data is nullptr, skip", i);
		69	+ continue;
		70	+ }
		71	+ const auto addr = tensor_data->GetAddr();
		72	+ if (addr == nullptr) {
		73	+ GELOGI("CheckPcieThrough: input idx:[%zu] addr is nullptr, skip", i);
		74	+ continue;
		75	+ }
		76	+ const auto addr_val = reinterpret_cast<uint64_t>(addr);
		77	+ GELOGD("CheckPcieThrough: input idx:[%zu], addr:[%p]", i, addr);
		78	+ for (uint32_t j = 0U; j < count; ++j) {
		79	+ const auto lo = reinterpret_cast<uint64_t>(ranges[j].startAddr);
		80	+ const auto hi = reinterpret_cast<uint64_t>(ranges[j].endAddr);
		81	+ GELOGD("CheckPcieThrough: input:[%zu], addrRange index:[%u], startAddr:[%p], endAddr:[%p]", i, j,
		82	+ ranges[j].startAddr, ranges[j].endAddr);
		83	+ if (addr_val >= lo && addr_val < hi) {
		84	+ GELOGD("CheckPcieThrough: input idx:[%zu] addr is in pcie range, set flag=true", i);
		85	+ *output = true;
		86	+ return ge::GRAPH_SUCCESS;
		87	+ }
		88	+ }
		89	+ }
		90	+ GELOGI("CheckPcieThrough: no input addr in pcie range, flag=false");
		91	+ return ge::GRAPH_SUCCESS;
		92	+}
		93	+
44	std::vector<std::string> TilingAppendWorkSpaceTracer(const KernelContext *context) {	94	std::vector<std::string> TilingAppendWorkSpaceTracer(const KernelContext *context) {
45	auto tiling_ws = context->GetInputPointer<gert::ContinuousVector>(0U);	95	auto tiling_ws = context->GetInputPointer<gert::ContinuousVector>(0U);
46	GE_ASSERT_NOTNULL(tiling_ws);	96	GE_ASSERT_NOTNULL(tiling_ws);
	@@ -236,6 +286,11 @@ ge::graphStatus BuildGeneralTilingCacheKey(const KernelContext *context, HashBuf
236	hash_buf.AddParamToBuf(input_shape->GetOriginShape());	286	hash_buf.AddParamToBuf(input_shape->GetOriginShape());
237	}	287	}
238	}	288	}
		289	+ const auto tiling_context = reinterpret_cast<const TilingContext *>(context);
		290	+ const auto pcie_flag = tiling_context->GetPcieThroughFlag();
		291	+ if (pcie_flag) {
		292	+ hash_buf.AddParamToBuf(pcie_flag);
		293	+ }
239	return ge::GRAPH_SUCCESS;	294	return ge::GRAPH_SUCCESS;
240	}	295	}
241		296
	@@ -862,6 +917,8 @@ ge::graphStatus BuildCacheableTilingFwkDataOutput(const ge::FastNode *node, Kern
862	REGISTER_KERNEL(PrepareCacheableTilingFwkData)	917	REGISTER_KERNEL(PrepareCacheableTilingFwkData)
863	.RunFunc(PrepareCacheableTilingFwkData)	918	.RunFunc(PrepareCacheableTilingFwkData)
864	.OutputsCreator(BuildCacheableTilingFwkDataOutput);	919	.OutputsCreator(BuildCacheableTilingFwkDataOutput);
		920	+
		921	+REGISTER_KERNEL(CheckPcieThrough).RunFunc(CheckPcieThrough);
865	} // namespace kernel	922	} // namespace kernel
866		923
867	} // namespace gert	924	} // namespace gert

Mruntime/v2/kernel/common_kernel_impl/tiling.h+1-0

	@@ -89,6 +89,7 @@ enum class TilingFixedInputIndex {
89	kFwkData,	89	kFwkData,
90	kDeterministic,	90	kDeterministic,
91	kDeterministicLevel,	91	kDeterministicLevel,
		92	+ kPcieThroughFlag,
92	kNum,	93	kNum,
93	};	94	};
94		95

Mtests/depends/ascendcl/src/ascendcl_stub.cc+7-0

	@@ -2020,6 +2020,13 @@ aclError aclDestroyDataBuffer(const aclDataBuffer *dataBuffer) {
2020	return ge::AclApiStub::GetInstance()->aclDestroyDataBuffer(dataBuffer);	2020	return ge::AclApiStub::GetInstance()->aclDestroyDataBuffer(dataBuffer);
2021	}	2021	}
2022		2022
		2023	+aclError aclrtHostGetDevicePointerAddrRange(aclrtAddrRange addrRange, uint32_t count) {
		2024	+ if (count != nullptr) {
		2025	+ *count = 0U;
		2026	+ }
		2027	+ return ACL_SUCCESS;
		2028	+}
		2029	+
2023	#ifdef __cplusplus	2030	#ifdef __cplusplus
2024	}	2031	}
2025	#endif	2032	#endif

Mtests/depends/platform/src/platform_stub.cc+9-0

	@@ -15,8 +15,13 @@
15	namespace {	15	namespace {
16	constexpr const char *kInvlaidSocVersion = "invalid_version";	16	constexpr const char *kInvlaidSocVersion = "invalid_version";
17	constexpr const char *kInvlaidInitSocVersion = "invalid_init_version";	17	constexpr const char *kInvlaidInitSocVersion = "invalid_init_version";
		18	+bool g_pcie_through_partial_support = false;
18	} // namespace	19	} // namespace
19		20
		21	+void SetPcieThroughPartialSupport(bool supported) {
		22	+ g_pcie_through_partial_support = supported;
		23	+}
		24	+
20	fe::PlatformInfoManager &fe::PlatformInfoManager::Instance() {	25	fe::PlatformInfoManager &fe::PlatformInfoManager::Instance() {
21	static fe::PlatformInfoManager pf;	26	static fe::PlatformInfoManager pf;
22	return pf;	27	return pf;
	@@ -152,6 +157,10 @@ bool fe::PlatFormInfos::GetPlatformResWithLock(
152	}	157	}
153		158
154	bool fe::PlatFormInfos::GetPlatformResWithLock(const string &label, const string &key, string &val) {	159	bool fe::PlatFormInfos::GetPlatformResWithLock(const string &label, const string &key, string &val) {
		160	+ if (label == "SoCInfo" && key == "pcie_through_partial_support") {
		161	+ val = g_pcie_through_partial_support ? "1" : "0";
		162	+ return true;
		163	+ }
155	if (label == "DtypeMKN" && key == "Default") {	164	if (label == "DtypeMKN" && key == "Default") {
156	val = "16,16,16";	165	val = "16,16,16";
157	} else if (label == "version" && key == "Short_SoC_Version") {	166	} else if (label == "version" && key == "Short_SoC_Version") {

Mtests/framework/ge_runtime_stub/include/faker/kernel_run_context_facker.h+2-0

	@@ -176,6 +176,7 @@ class TilingContextFaker {
176	TilingContextFaker &Workspace(ContinuousVector *workspace);	176	TilingContextFaker &Workspace(ContinuousVector *workspace);
177	TilingContextFaker &TilingFwkData(void *fwk_data);	177	TilingContextFaker &TilingFwkData(void *fwk_data);
178	TilingContextFaker &Deterministic(void *deterministic);	178	TilingContextFaker &Deterministic(void *deterministic);
		179	+ TilingContextFaker &PcieThroughFlag(bool pcie_through_flag);
179		180
180	KernelRunContextHolder Build() const;	181	KernelRunContextHolder Build() const;
181		182
	@@ -193,6 +194,7 @@ class TilingContextFaker {
193	void *compile_info_ = nullptr;	194	void *compile_info_ = nullptr;
194	void *deterministic_ = nullptr;	195	void *deterministic_ = nullptr;
195	void *deterministic_level_ = nullptr;	196	void *deterministic_level_ = nullptr;
		197	+ bool pcie_through_flag_ = false;
196	};	198	};
197	} // namespace gert	199	} // namespace gert
198	#endif // AIR_CXX_TESTS_UT_GE_RUNTIME_V2_FAKER_KERNEL_RUN_CONTEXT_FACKER_H_	200	#endif // AIR_CXX_TESTS_UT_GE_RUNTIME_V2_FAKER_KERNEL_RUN_CONTEXT_FACKER_H_

Mtests/framework/ge_runtime_stub/src/kernel_run_context_faker.cc+6-0

	@@ -245,6 +245,7 @@ void TilingContextFaker::UpdateInputs() {
245	inputs.push_back(fwk_data_); // kInputsTilingFunc	245	inputs.push_back(fwk_data_); // kInputsTilingFunc
246	inputs.push_back(deterministic_);	246	inputs.push_back(deterministic_);
247	inputs.push_back(deterministic_level_);	247	inputs.push_back(deterministic_level_);
		248	+ inputs.push_back(reinterpret_cast<void *>(pcie_through_flag_));
248	base_faker_.Inputs(std::move(inputs));	249	base_faker_.Inputs(std::move(inputs));
249	}	250	}
250	TilingContextFaker &TilingContextFaker::TilingFwkData(void *fwk_data) {	251	TilingContextFaker &TilingContextFaker::TilingFwkData(void *fwk_data) {
	@@ -257,4 +258,9 @@ TilingContextFaker &TilingContextFaker::Deterministic(void *deterministic) {
257	UpdateInputs();	258	UpdateInputs();
258	return *this;	259	return *this;
259	}	260	}
		261	+TilingContextFaker &TilingContextFaker::PcieThroughFlag(bool pcie_through_flag) {
		262	+ pcie_through_flag_ = pcie_through_flag;
		263	+ UpdateInputs();
		264	+ return *this;
		265	+}
260	} // namespace gert	266	} // namespace gert

Mtests/framework/ge_runtime_stub/src/kernel_stub.cc+1-1

	@@ -21,7 +21,7 @@ namespace {
21	UINT32 FakeTiling(gert::KernelContext *context) {	21	UINT32 FakeTiling(gert::KernelContext *context) {
22	const auto input_num = context->GetInputNum();	22	const auto input_num = context->GetInputNum();
23	GE_ASSERT(input_num > 2);	23	GE_ASSERT(input_num > 2);
24	- auto fwk_data = context->GetInputPointer<kernel::TilingFwkData>(input_num - 3);	24	+ auto fwk_data = context->GetInputPointer<kernel::TilingFwkData>(input_num - 4);
25	GE_ASSERT_NOTNULL(fwk_data);	25	GE_ASSERT_NOTNULL(fwk_data);
26	auto launch_arg = fwk_data->launch_arg;	26	auto launch_arg = fwk_data->launch_arg;
27	GE_ASSERT_NOTNULL(launch_arg);	27	GE_ASSERT_NOTNULL(launch_arg);

Mtests/ge/st/testcase/fast_runtime_v2/allocator_test.cc+1-1

	@@ -40,7 +40,7 @@ namespace {
40	UINT32 FakeTilingWithBigWorkspace(gert::KernelContext *context) {	40	UINT32 FakeTilingWithBigWorkspace(gert::KernelContext *context) {
41	const auto input_num = context->GetInputNum();	41	const auto input_num = context->GetInputNum();
42	GE_ASSERT(input_num > 2);	42	GE_ASSERT(input_num > 2);
43	- auto fwk_data = context->GetInputPointer<kernel::TilingFwkData>(input_num - 3);	43	+ auto fwk_data = context->GetInputPointer<kernel::TilingFwkData>(input_num - 4);
44	GE_ASSERT_NOTNULL(fwk_data);	44	GE_ASSERT_NOTNULL(fwk_data);
45	auto launch_arg = fwk_data->launch_arg;	45	auto launch_arg = fwk_data->launch_arg;
46	GE_ASSERT_NOTNULL(launch_arg);	46	GE_ASSERT_NOTNULL(launch_arg);

Mtests/ge/st/testcase/test_ge_api_v2.cc+16-0

	@@ -2478,4 +2478,20 @@ TEST_F(GeApiV2Test, SessionApis_GraphNotExist_ReportE10062) {
2478	EXPECT_EQ(GEFinalizeV2(), SUCCESS);	2478	EXPECT_EQ(GEFinalizeV2(), SUCCESS);
2479	ReInitGe();	2479	ReInitGe();
2480	}	2480	}
		2481	+
		2482	+TEST_F(GeApiV2Test, InitializeWithDisablePcieThroughOption) {
		2483	+ GEFinalizeV2();
		2484	+ std::map<AscendString, AscendString> options = {{"ge.exec.disable_pcie_through", "1"}};
		2485	+ EXPECT_EQ(GEInitializeV2(options), SUCCESS);
		2486	+ GEFinalizeV2();
		2487	+ ReInitGe();
		2488	+}
		2489	+
		2490	+TEST_F(GeApiV2Test, InitializeWithEnablePcieThroughOption) {
		2491	+ GEFinalizeV2();
		2492	+ std::map<AscendString, AscendString> options = {{"ge.exec.disable_pcie_through", "0"}};
		2493	+ EXPECT_EQ(GEInitializeV2(options), SUCCESS);
		2494	+ GEFinalizeV2();
		2495	+ ReInitGe();
		2496	+}
2481	} // namespace ge	2497	} // namespace ge

Mtests/ge/ut/ge/common/op_tiling_rt2_unittest.cc+33-0

	@@ -64,8 +64,10 @@ class CompileInfoJson : public CompileInfoBase {
64	int32_t expected_deterministic = -1;	64	int32_t expected_deterministic = -1;
65	int32_t expected_deterministic_level = -1;	65	int32_t expected_deterministic_level = -1;
66	bool check_extend_conv_attrs = false;	66	bool check_extend_conv_attrs = false;
		67	+int32_t expected_pcie_through_flag = -1;
67	constexpr const char *kDeterministicAttr = "_deterministic";	68	constexpr const char *kDeterministicAttr = "_deterministic";
68	constexpr const char *kDeterministicLevelAttr = "_deterministic_level";	69	constexpr const char *kDeterministicLevelAttr = "_deterministic_level";
		70	+constexpr const char *kPcieThroughFlagAttr = "_pcie_through_flag";
69		71
70	class RegisterOpTilingRT2UT : public testing::Test {	72	class RegisterOpTilingRT2UT : public testing::Test {
71	protected:	73	protected:
	@@ -78,6 +80,7 @@ class RegisterOpTilingRT2UT : public testing::Test {
78	expected_deterministic = -1;	80	expected_deterministic = -1;
79	expected_deterministic_level = -1;	81	expected_deterministic_level = -1;
80	check_extend_conv_attrs = false;	82	check_extend_conv_attrs = false;
		83	+ expected_pcie_through_flag = -1;
81	ge::GetThreadLocalContext().SetGlobalOption({});	84	ge::GetThreadLocalContext().SetGlobalOption({});
82	ge::AclRuntimeStub::SetErrorResultApiName("");	85	ge::AclRuntimeStub::SetErrorResultApiName("");
83	ge::AclRuntimeStub::Reset();	86	ge::AclRuntimeStub::Reset();
	@@ -135,6 +138,9 @@ ge::graphStatus DummyTiling(TilingContext *tiling_context) {
135	if (expected_deterministic >= 0) {	138	if (expected_deterministic >= 0) {
136	EXPECT_EQ(tiling_context->GetDeterministic(), expected_deterministic);	139	EXPECT_EQ(tiling_context->GetDeterministic(), expected_deterministic);
137	}	140	}
		141	+ if (expected_pcie_through_flag >= 0) {
		142	+ EXPECT_EQ(tiling_context->GetPcieThroughFlag(), static_cast<bool>(expected_pcie_through_flag));
		143	+ }
138	return ge::GRAPH_SUCCESS;	144	return ge::GRAPH_SUCCESS;
139	}	145	}
140		146
	@@ -1441,4 +1447,31 @@ TEST_F(RegisterOpTilingRT2UT, SetDeterministicConfigPropagatesAclFailures) {
1441	ASSERT_EQ(acl_runtime_stub_->GetSysParamSetRecords().size(), 1U);	1447	ASSERT_EQ(acl_runtime_stub_->GetSysParamSetRecords().size(), 1U);
1442	}	1448	}
1443		1449
		1450	+TEST_F(RegisterOpTilingRT2UT, AicoreParseAndTilingWithNodePcieThroughFlag) {
		1451	+ SpaceRegistryFaker::UpdateOpImplToDefaultSpaceRegistry();
		1452	+ auto graph = ShareGraph::ConcatV2ConstDependencyGraph();
		1453	+ auto concatv2_node = graph->FindNode("concatv2");
		1454	+ ASSERT_NE(concatv2_node, nullptr);
		1455	+ (void)ge::AttrUtils::SetStr(concatv2_node->GetOpDesc(), COMPILE_INFO_JSON, "testst");
		1456	+ (void)ge::AttrUtils::SetBool(concatv2_node->GetOpDesc(), kPcieThroughFlagAttr, true);
		1457	+ expected_pcie_through_flag = 1;
		1458	+ utils::OpRunInfo run_info;
		1459	+ auto op = ge::OpDescUtils::CreateOperatorFromNode(concatv2_node);
		1460	+ fe::PlatFormInfos platform_infos;
		1461	+ EXPECT_EQ(AicoreRtParseAndTiling(op, platform_infos, run_info), GRAPH_SUCCESS);
		1462	+}
		1463	+
		1464	+TEST_F(RegisterOpTilingRT2UT, AicoreParseAndTilingWithoutPcieThroughFlag) {
		1465	+ SpaceRegistryFaker::UpdateOpImplToDefaultSpaceRegistry();
		1466	+ auto graph = ShareGraph::ConcatV2ConstDependencyGraph();
		1467	+ auto concatv2_node = graph->FindNode("concatv2");
		1468	+ ASSERT_NE(concatv2_node, nullptr);
		1469	+ (void)ge::AttrUtils::SetStr(concatv2_node->GetOpDesc(), COMPILE_INFO_JSON, "testst");
		1470	+ expected_pcie_through_flag = 0;
		1471	+ utils::OpRunInfo run_info;
		1472	+ auto op = ge::OpDescUtils::CreateOperatorFromNode(concatv2_node);
		1473	+ fe::PlatFormInfos platform_infos;
		1474	+ EXPECT_EQ(AicoreRtParseAndTiling(op, platform_infos, run_info), GRAPH_SUCCESS);
		1475	+}
		1476	+
1444	} // namespace optiling	1477	} // namespace optiling

Mtests/ge/ut/ge/graph/manager/graph_manager_unittest.cc+60-0

	@@ -76,6 +76,8 @@ using namespace std;
76	using namespace testing;	76	using namespace testing;
77	using namespace domi;	77	using namespace domi;
78		78
		79	+extern void SetPcieThroughPartialSupport(bool supported);
		80	+
79	namespace {	81	namespace {
80	const char *kCast = "Cast";	82	const char *kCast = "Cast";
81	const uint32_t kNotAdded = 0;	83	const uint32_t kNotAdded = 0;
	@@ -5983,4 +5985,62 @@ TEST_F(UtestGraphManagerTest, test_ParseHintInputShape_invalid_pattern) {
5983	GetThreadLocalContext().SetGraphOption({});	5985	GetThreadLocalContext().SetGraphOption({});
5984	}	5986	}
5985		5987
		5988	+TEST_F(UtestGraphManagerTest, ProcessPcieThrough_SkipWhenDisabledByOption) {
		5989	+ auto back_options = ge::GetThreadLocalContext().GetAllGlobalOptions();
		5990	+ auto global_options = back_options;
		5991	+ global_options["ge.exec.disable_pcie_through"] = "1";
		5992	+ GetThreadLocalContext().SetGlobalOption(global_options);
		5993	+
		5994	+ auto graph = CreateGraphWithNullOutput();
		5995	+ GraphManager graph_manager;
		5996	+ EXPECT_EQ(graph_manager.ProcessPcieThrough(graph), ge::SUCCESS);
		5997	+
		5998	+ auto cast1_node = graph->FindNode("cast1");
		5999	+ ASSERT_NE(cast1_node, nullptr);
		6000	+ bool pcie_through_flag = true;
		6001	+ EXPECT_FALSE(ge::AttrUtils::GetBool(cast1_node->GetOpDesc(), ge::ATTR_NAME_PCIE_THROUGH_FLAG, pcie_through_flag));
		6002	+
		6003	+ GetThreadLocalContext().SetGlobalOption(back_options);
		6004	+}
		6005	+
		6006	+TEST_F(UtestGraphManagerTest, ProcessPcieThrough_SkipWhenPlatformNotSupport) {
		6007	+ auto graph = CreateGraphWithNullOutput();
		6008	+ GraphManager graph_manager;
		6009	+ EXPECT_EQ(graph_manager.ProcessPcieThrough(graph), ge::SUCCESS);
		6010	+
		6011	+ auto cast1_node = graph->FindNode("cast1");
		6012	+ ASSERT_NE(cast1_node, nullptr);
		6013	+ bool pcie_through_flag = true;
		6014	+ EXPECT_FALSE(ge::AttrUtils::GetBool(cast1_node->GetOpDesc(), ge::ATTR_NAME_PCIE_THROUGH_FLAG, pcie_through_flag));
		6015	+}
		6016	+
		6017	+TEST_F(UtestGraphManagerTest, ProcessPcieThrough_SetsFlagWhenSupported) {
		6018	+ SetPcieThroughPartialSupport(true);
		6019	+ gert::SpaceRegistryFaker::CreateDefaultSpaceRegistryImpl2(true);
		6020	+ auto space_registry = gert::DefaultOpImplSpaceRegistryV2::GetInstance().GetSpaceRegistry();
		6021	+ ASSERT_NE(space_registry, nullptr);
		6022	+ auto op_impl_func = space_registry->CreateOrGetOpImpl("Cast");
		6023	+ ASSERT_NE(op_impl_func, nullptr);
		6024	+ op_impl_func->SetSupportPcieThrough();
		6025	+
		6026	+ auto graph = CreateGraphWithNullOutput();
		6027	+ GraphManager graph_manager;
		6028	+ EXPECT_EQ(graph_manager.ProcessPcieThrough(graph), ge::SUCCESS);
		6029	+
		6030	+ auto cast1_node = graph->FindNode("cast1");
		6031	+ ASSERT_NE(cast1_node, nullptr);
		6032	+ bool pcie_through_flag = false;
		6033	+ EXPECT_TRUE(ge::AttrUtils::GetBool(cast1_node->GetOpDesc(), ge::ATTR_NAME_PCIE_THROUGH_FLAG, pcie_through_flag));
		6034	+ EXPECT_TRUE(pcie_through_flag);
		6035	+
		6036	+ auto cast2_node = graph->FindNode("cast2");
		6037	+ ASSERT_NE(cast2_node, nullptr);
		6038	+ pcie_through_flag = false;
		6039	+ EXPECT_TRUE(ge::AttrUtils::GetBool(cast2_node->GetOpDesc(), ge::ATTR_NAME_PCIE_THROUGH_FLAG, pcie_through_flag));
		6040	+ EXPECT_TRUE(pcie_through_flag);
		6041	+
		6042	+ SetPcieThroughPartialSupport(false);
		6043	+ gert::DefaultOpImplSpaceRegistryV2::GetInstance().SetSpaceRegistry(nullptr);
		6044	+}
		6045	+
5986	} // namespace ge	6046	} // namespace ge

Mtests/ge/ut/ge/runtime/fast_v2/engine/aicore/autofuse_node_unitest.cc+3-3

Mtests/ge/ut/ge/runtime/fast_v2/graph_builder/bg_cacheable_tiling_unittest.cc+16-14

	@@ -252,6 +252,7 @@ class BgCacheableTilingUT : public BgTestAutoCreateFrame {
252	expect_from.emplace_back("PrepareCacheableTilingFwkData");	252	expect_from.emplace_back("PrepareCacheableTilingFwkData");
253	expect_from.emplace_back("InnerData");	253	expect_from.emplace_back("InnerData");
254	expect_from.emplace_back("InnerData");	254	expect_from.emplace_back("InnerData");
		255	+ expect_from.emplace_back("Const");
255	ASSERT_EQ(FastNodeTopoChecker(tiling_rets[0]).StrictConnectFrom(expect_from), "success");	256	ASSERT_EQ(FastNodeTopoChecker(tiling_rets[0]).StrictConnectFrom(expect_from), "success");
256	auto tiling_parse_node = ge::ExecuteGraphUtils::FindFirstNodeMatchType(exe_graph, "TilingParse");	257	auto tiling_parse_node = ge::ExecuteGraphUtils::FindFirstNodeMatchType(exe_graph, "TilingParse");
257	ASSERT_NE(tiling_parse_node, nullptr);	258	ASSERT_NE(tiling_parse_node, nullptr);
	@@ -381,7 +382,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_Ok_TopoCorrectSameNodeWithDifferentOppImplV
381	{"TilingParse", 2},	382	{"TilingParse", 2},
382	{"InnerData", 4},	383	{"InnerData", 4},
383	{"SplitRtStreams", 1},	384	{"SplitRtStreams", 1},
384	- {"Const", 23},	385	+ {"Const", 25},
385	{"CalcTensorSizeFromStorage", 2},	386	{"CalcTensorSizeFromStorage", 2},
386	{"PrepareCacheableTilingFwkData", 2},	387	{"PrepareCacheableTilingFwkData", 2},
387	{"AllocLaunchArg", 2}}),	388	{"AllocLaunchArg", 2}}),
	@@ -437,7 +438,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_TopoCorrect_KnownWorkspace) {
437	{"TilingParse", 1},	438	{"TilingParse", 1},
438	{"InnerData", 3},	439	{"InnerData", 3},
439	{"SplitRtStreams", 1},	440	{"SplitRtStreams", 1},
440	- {"Const", 13},	441	+ {"Const", 14},
441	{"TilingAppendWorkspace", 1},	442	{"TilingAppendWorkspace", 1},
442	{"TilingAppendDfxInfo", 1},	443	{"TilingAppendDfxInfo", 1},
443	{"CalcTensorSizeFromStorage", 1},	444	{"CalcTensorSizeFromStorage", 1},
	@@ -478,7 +479,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_TopoCorrect_MemCheck) {
478	{"TilingParse", 1},	479	{"TilingParse", 1},
479	{"InnerData", 3},	480	{"InnerData", 3},
480	{"SplitRtStreams", 1},	481	{"SplitRtStreams", 1},
481	- {"Const", 13},	482	+ {"Const", 14},
482	{"TilingAppendWorkspace", 1},	483	{"TilingAppendWorkspace", 1},
483	{"TilingAppendDfxInfo", 1},	484	{"TilingAppendDfxInfo", 1},
484	{"CalcTensorSizeFromStorage", 1},	485	{"CalcTensorSizeFromStorage", 1},
	@@ -544,7 +545,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_TopoCorrect_MemCheck2) {
544	{"CacheableTiling", 1},	545	{"CacheableTiling", 1},
545	{"TilingParse", 1},	546	{"TilingParse", 1},
546	{"InnerData", 3},	547	{"InnerData", 3},
547	- {"Const", 12},	548	+ {"Const", 13},
548	{"TilingAppendWorkspace", 1},	549	{"TilingAppendWorkspace", 1},
549	{"TilingAppendDfxInfo", 1},	550	{"TilingAppendDfxInfo", 1},
550	{"CalcTensorSizeFromStorage", 1},	551	{"CalcTensorSizeFromStorage", 1},
	@@ -611,7 +612,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_TopoCorrect_MemCheck3) {
611	{"CacheableTiling", 1},	612	{"CacheableTiling", 1},
612	{"TilingParse", 1},	613	{"TilingParse", 1},
613	{"InnerData", 3},	614	{"InnerData", 3},
614	- {"Const", 12},	615	+ {"Const", 13},
615	{"TilingAppendWorkspace", 1},	616	{"TilingAppendWorkspace", 1},
616	{"TilingAppendDfxInfo", 1},	617	{"TilingAppendDfxInfo", 1},
617	{"CalcTensorSizeFromStorage", 1},	618	{"CalcTensorSizeFromStorage", 1},
	@@ -676,7 +677,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_TopoCorrect_MemCheck4) {
676	{"CacheableTiling", 1},	677	{"CacheableTiling", 1},
677	{"TilingParse", 1},	678	{"TilingParse", 1},
678	{"InnerData", 3},	679	{"InnerData", 3},
679	- {"Const", 12},	680	+ {"Const", 13},
680	{"TilingAppendWorkspace", 1},	681	{"TilingAppendWorkspace", 1},
681	{"TilingAppendDfxInfo", 1},	682	{"TilingAppendDfxInfo", 1},
682	{"CalcTensorSizeFromStorage", 1},	683	{"CalcTensorSizeFromStorage", 1},
	@@ -741,7 +742,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_TopoCorrect_MemCheck5) {
741	{"CacheableTiling", 1},	742	{"CacheableTiling", 1},
742	{"TilingParse", 1},	743	{"TilingParse", 1},
743	{"InnerData", 3},	744	{"InnerData", 3},
744	- {"Const", 12},	745	+ {"Const", 13},
745	{"TilingAppendWorkspace", 1},	746	{"TilingAppendWorkspace", 1},
746	{"TilingAppendDfxInfo", 1},	747	{"TilingAppendDfxInfo", 1},
747	{"CalcTensorSizeFromStorage", 1},	748	{"CalcTensorSizeFromStorage", 1},
	@@ -848,7 +849,7 @@ TEST_F(BgCacheableTilingUT, FallibleTiling_Ok_TopoCorrectWithMemCheck) {
848	{"TilingParse", 1},	849	{"TilingParse", 1},
849	{"InnerData", 3},	850	{"InnerData", 3},
850	{"SplitRtStreams", 1},	851	{"SplitRtStreams", 1},
851	- {"Const", 12},	852	+ {"Const", 13},
852	{"CacheableFallibleTiling", 1},	853	{"CacheableFallibleTiling", 1},
853	{"TilingAppendDfxInfo", 1},	854	{"TilingAppendDfxInfo", 1},
854	{"CalcTensorSizeFromStorage", 1},	855	{"CalcTensorSizeFromStorage", 1},
	@@ -979,7 +980,8 @@ TEST_F(BgCacheableTilingUT, BgAtomicTiling_TopoCorrect) {
979	{"TilingParse"},	980	{"TilingParse"},
980	{"PrepareTilingFwkData"},	981	{"PrepareTilingFwkData"},
981	{"InnerData"},	982	{"InnerData"},
982	- {"InnerData"}}),	983	+ {"InnerData"},
		984	+ {"Const"}}),
983	"success");	985	"success");
984	auto tiling_parse_node = ge::ExecuteGraphUtils::FindFirstNodeMatchType(exe_graph, "TilingParse");	986	auto tiling_parse_node = ge::ExecuteGraphUtils::FindFirstNodeMatchType(exe_graph, "TilingParse");
985	ASSERT_NE(tiling_parse_node, nullptr);	987	ASSERT_NE(tiling_parse_node, nullptr);
	@@ -1726,7 +1728,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_TopoCorrect) {
1726	{"TilingParse", 1},	1728	{"TilingParse", 1},
1727	{"InnerData", 3},	1729	{"InnerData", 3},
1728	{"SplitRtStreams", 1},	1730	{"SplitRtStreams", 1},
1729	- {"Const", 12},	1731	+ {"Const", 13},
1730	{"CalcTensorSizeFromStorage", 1},	1732	{"CalcTensorSizeFromStorage", 1},
1731	{"PrepareCacheableTilingFwkData", 1},	1733	{"PrepareCacheableTilingFwkData", 1},
1732	{"AllocLaunchArg", 1}}),	1734	{"AllocLaunchArg", 1}}),
	@@ -1780,7 +1782,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_TopoCorrect_FallibleTiling_MemCheck) {
1780	{"TilingParse", 1},	1782	{"TilingParse", 1},
1781	{"InnerData", 3},	1783	{"InnerData", 3},
1782	{"SplitRtStreams", 1},	1784	{"SplitRtStreams", 1},
1783	- {"Const", 12},	1785	+ {"Const", 13},
1784	{"CacheableFallibleTiling", 1},	1786	{"CacheableFallibleTiling", 1},
1785	{"TilingAppendDfxInfo", 1},	1787	{"TilingAppendDfxInfo", 1},
1786	{"CalcTensorSizeFromStorage", 1},	1788	{"CalcTensorSizeFromStorage", 1},
	@@ -1825,7 +1827,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_TopoCorrect_FallibleTiling_MemCheck2) {
1825	{"TilingParse", 1},	1827	{"TilingParse", 1},
1826	{"InnerData", 3},	1828	{"InnerData", 3},
1827	{"SplitRtStreams", 1},	1829	{"SplitRtStreams", 1},
1828	- {"Const", 12},	1830	+ {"Const", 13},
1829	{"CacheableFallibleTiling", 1},	1831	{"CacheableFallibleTiling", 1},
1830	{"TilingAppendDfxInfo", 1},	1832	{"TilingAppendDfxInfo", 1},
1831	{"CalcTensorSizeFromStorage", 1},	1833	{"CalcTensorSizeFromStorage", 1},
	@@ -1872,7 +1874,7 @@ TEST_F(BgCacheableTilingUT, BgTiling_TopoCorrect_FallibleTiling_MemCheck3) {
1872	{"TilingParse", 1},	1874	{"TilingParse", 1},
1873	{"InnerData", 3},	1875	{"InnerData", 3},
1874	{"SplitRtStreams", 1},	1876	{"SplitRtStreams", 1},
1875	- {"Const", 12},	1877	+ {"Const", 13},
1876	{"CacheableFallibleTiling", 1},	1878	{"CacheableFallibleTiling", 1},
1877	{"TilingAppendDfxInfo", 1},	1879	{"TilingAppendDfxInfo", 1},
1878	{"CalcTensorSizeFromStorage", 1},	1880	{"CalcTensorSizeFromStorage", 1},
	@@ -1913,7 +1915,7 @@ TEST_F(BgCacheableTilingUT, BgFallibleTiling_OutputsCountCorrect) {
1913	{"SplitRtStreams", 1},	1915	{"SplitRtStreams", 1},
1914	{"CalcTensorSizeFromStorage", 1},	1916	{"CalcTensorSizeFromStorage", 1},
1915	{"TilingAppendDfxInfo", 1},	1917	{"TilingAppendDfxInfo", 1},
1916	- {"Const", 12},	1918	+ {"Const", 13},
1917	{"PrepareCacheableTilingFwkData", 1},	1919	{"PrepareCacheableTilingFwkData", 1},
1918	{"AllocLaunchArg", 1}}),	1920	{"AllocLaunchArg", 1}}),
1919	"success");	1921	"success");

Mtests/ge/ut/ge/runtime/fast_v2/graph_builder/bg_tiling_unittest.cc+29-1

	@@ -113,6 +113,7 @@ class BgTilingUT : public BgTestAutoCreateFrame {
113	expect_from.emplace_back("PrepareTilingFwkData");	113	expect_from.emplace_back("PrepareTilingFwkData");
114	expect_from.emplace_back("InnerData");	114	expect_from.emplace_back("InnerData");
115	expect_from.emplace_back("InnerData");	115	expect_from.emplace_back("InnerData");
		116	+ expect_from.emplace_back("Const");
116	ASSERT_EQ(FastNodeTopoChecker(tiling_rets[0]).StrictConnectFrom(expect_from), "success");	117	ASSERT_EQ(FastNodeTopoChecker(tiling_rets[0]).StrictConnectFrom(expect_from), "success");
117	auto tiling_parse_node = ge::ExecuteGraphUtils::FindFirstNodeMatchType(exe_graph, "TilingParse");	118	auto tiling_parse_node = ge::ExecuteGraphUtils::FindFirstNodeMatchType(exe_graph, "TilingParse");
118	ASSERT_NE(tiling_parse_node, nullptr);	119	ASSERT_NE(tiling_parse_node, nullptr);
	@@ -193,7 +194,7 @@ TEST_F(BgTilingUT, BgTiling_Ok_CachableTilingUnsupported) {
193	{"TilingParse", 1},	194	{"TilingParse", 1},
194	{"InnerData", 3},	195	{"InnerData", 3},
195	{"SplitRtStreams", 1},	196	{"SplitRtStreams", 1},
196	- {"Const", 10},	197	+ {"Const", 11},
197	{"CalcTensorSizeFromStorage", 1},	198	{"CalcTensorSizeFromStorage", 1},
198	{"PrepareTilingFwkData", 1},	199	{"PrepareTilingFwkData", 1},
199	{"AllocLaunchArg", 1}}),	200	{"AllocLaunchArg", 1}}),
	@@ -409,5 +410,32 @@ TEST_F(BgTilingUT, BgTiling_FailedWhenNodeDeterministicNotString) {
409	EXPECT_TRUE(tiling_rets.empty() \|\| (tiling_rets[0] == nullptr));	410	EXPECT_TRUE(tiling_rets.empty() \|\| (tiling_rets[0] == nullptr));
410	}	411	}
411		412
		413	+TEST_F(BgTilingUT, BgTiling_CreatesPcieThroughHolder) {
		414	+ IMPL_OP(FakeAddN).InputsDataDependency({0});
		415	+ SpaceRegistryFaker::CreateDefaultSpaceRegistryImpl2(true);
		416	+
		417	+ constexpr int64_t kInputNum = 2UL;
		418	+ std::vector<ValueHolderPtr> input_shapes;
		419	+ for (int64_t i = 0; i < kInputNum; ++i) {
		420	+ input_shapes.emplace_back(ValueHolder::CreateFeed(i));
		421	+ }
		422	+ auto out_shape = ValueHolder::CreateFeed(2);
		423	+ auto platform = ValueHolder::CreateFeed(3);
		424	+ auto graph = BuildGraphWithManyInputs("FakeAddN", kInputNum);
		425	+ ASSERT_NE(graph, nullptr);
		426	+ auto add_node = graph->FindNode("FakeAddN");
		427	+ ASSERT_NE(add_node, nullptr);
		428	+ AddCompiledJson(add_node);
		429	+
		430	+ auto root_model = GeModelBuilder(graph).BuildGeRootModel();
		431	+ auto global_data = GlobalDataFaker(root_model).FakeWithHandleAiCore("FakeAddN", false).Build();
		432	+ bg::LowerConstDataNode(global_data);
		433	+ auto tiling_rets = Tiling(add_node, input_shapes, {out_shape}, {platform, global_data, fake_launch_arg_});
		434	+ ASSERT_FALSE(tiling_rets.empty());
		435	+ for (const auto &ret : tiling_rets) {
		436	+ ASSERT_NE(ret, nullptr);
		437	+ }
		438	+}
		439	+
412	} // namespace bg	440	} // namespace bg
413	} // namespace gert	441	} // namespace gert

Mtests/ge/ut/ge/runtime/fast_v2/kernel/cacheable_tiling_unittest.cc+24-24

	@@ -191,15 +191,15 @@ TEST_F(CacheableTilingUt, CacheableTiling_Fail_CallTilingFuncFailed) {
191	// 准备Tiling的输出	191	// 准备Tiling的输出
192	auto workspace_sizes_holder = CreateWorkspaceSizesWithDummyData(16UL);	192	auto workspace_sizes_holder = CreateWorkspaceSizesWithDummyData(16UL);
193	ASSERT_NE(workspace_sizes_holder, nullptr);	193	ASSERT_NE(workspace_sizes_holder, nullptr);
194	- auto run_context =	194	+ auto run_context = KernelRunContextFaker()
195	- KernelRunContextFaker()	195	+ .NodeIoNum(2UL, 1UL)
196	- .NodeIoNum(2UL, 1UL)	196	+ .IrInputNum(2UL)
197	- .IrInputNum(2UL)	197	+ .KernelIONum(6UL, static_cast<size_t>(TilingExOutputIndex::kNum))
198	- .KernelIONum(6UL, static_cast<size_t>(TilingExOutputIndex::kNum))	198	+ .Inputs({&in_shape1, &in_shape2, &out_shape, nullptr, nullptr, &cacheable_fwk_data, nullptr,
199	- .Inputs({&in_shape1, &in_shape2, &out_shape, nullptr, nullptr, &cacheable_fwk_data, nullptr, nullptr})	199	+ nullptr, nullptr})
200	- .Outputs({nullptr, nullptr, nullptr, nullptr, workspace_sizes_holder.get(), nullptr, nullptr, nullptr,	200	+ .Outputs({nullptr, nullptr, nullptr, nullptr, workspace_sizes_holder.get(), nullptr, nullptr,
201	- nullptr, nullptr, nullptr, nullptr})	201	+ nullptr, nullptr, nullptr, nullptr, nullptr})
202	- .Build();	202	+ .Build();
203	ASSERT_EQ(kf_cacheable_tiling->run_func(run_context), ge::GRAPH_FAILED);	203	ASSERT_EQ(kf_cacheable_tiling->run_func(run_context), ge::GRAPH_FAILED);
204	// tiling_func调用失败不做缓存	204	// tiling_func调用失败不做缓存
205	HashBuffer hash_buf;	205	HashBuffer hash_buf;
	@@ -240,13 +240,13 @@ TEST_F(CacheableTilingUt, CacheableTiling_Ok_TilingResultAddedAndFetched) {
240	const auto execute_kernel_and_check = [&](KernelRegistry::KernelFunc stub_func) {	240	const auto execute_kernel_and_check = [&](KernelRegistry::KernelFunc stub_func) {
241	const TilingFwkData fwk_data = {.tiling_func = reinterpret_cast<void *>(stub_func), .launch_arg = fake_launch_arg};	241	const TilingFwkData fwk_data = {.tiling_func = reinterpret_cast<void *>(stub_func), .launch_arg = fake_launch_arg};
242	cacheable_fwk_data.fwk_data = fwk_data;	242	cacheable_fwk_data.fwk_data = fwk_data;
243	- auto run_context =	243	+ auto run_context = KernelRunContextFaker()
244	- KernelRunContextFaker()	244	+ .NodeIoNum(2UL, 1UL)
245	- .NodeIoNum(2UL, 1UL)	245	+ .IrInputNum(2UL)
246	- .IrInputNum(2UL)	246	+ .KernelIONum(6UL, static_cast<size_t>(TilingExOutputIndex::kNum))
247	- .KernelIONum(6UL, static_cast<size_t>(TilingExOutputIndex::kNum))	247	+ .Inputs({&in_shape1, &in_shape2, &out_shape, nullptr, nullptr, &cacheable_fwk_data, nullptr,
248	- .Inputs({&in_shape1, &in_shape2, &out_shape, nullptr, nullptr, &cacheable_fwk_data, nullptr, nullptr})	248	+ nullptr, nullptr})
249	- .Build();	249	+ .Build();
250	ASSERT_EQ(kf_cacheable_tiling->outputs_creator(nullptr, run_context), ge::GRAPH_SUCCESS);	250	ASSERT_EQ(kf_cacheable_tiling->outputs_creator(nullptr, run_context), ge::GRAPH_SUCCESS);
251	ASSERT_EQ(kf_cacheable_tiling->run_func(run_context), ge::GRAPH_SUCCESS);	251	ASSERT_EQ(kf_cacheable_tiling->run_func(run_context), ge::GRAPH_SUCCESS);
252	// tiling_func调用成功,缓存Tiling结果,其中workspace中缓存的是调用AlignWorkspaceSizes对齐后的结果	252	// tiling_func调用成功,缓存Tiling结果,其中workspace中缓存的是调用AlignWorkspaceSizes对齐后的结果
	@@ -328,13 +328,13 @@ TEST_F(CacheableTilingUt, CacheableTiling_Ok_DataDependentTilingResultAddedAndFe
328	const auto execute_kernel_and_check = [&](KernelRegistry::KernelFunc stub_func) {	328	const auto execute_kernel_and_check = [&](KernelRegistry::KernelFunc stub_func) {
329	cacheable_fwk_data.fwk_data.tiling_func = reinterpret_cast<void *>(stub_func);	329	cacheable_fwk_data.fwk_data.tiling_func = reinterpret_cast<void *>(stub_func);
330	auto td_output_holder = TilingData::CreateCap(1024UL);	330	auto td_output_holder = TilingData::CreateCap(1024UL);
331	- auto run_context =	331	+ auto run_context = KernelRunContextFaker()
332	- KernelRunContextFaker()	332	+ .NodeIoNum(2UL, 1UL)
333	- .NodeIoNum(2UL, 1UL)	333	+ .IrInputNum(2UL)
334	- .IrInputNum(2UL)	334	+ .KernelIONum(7UL, static_cast<size_t>(TilingExOutputIndex::kNum))
335	- .KernelIONum(7UL, static_cast<size_t>(TilingExOutputIndex::kNum))	335	+ .Inputs({&in_tensor1, &in_tensor2, &out_tensor, nullptr, nullptr, &cacheable_fwk_data,
336	- .Inputs({&in_tensor1, &in_tensor2, &out_tensor, nullptr, nullptr, &cacheable_fwk_data, nullptr, nullptr})	336	+ nullptr, nullptr, nullptr})
337	- .Build();	337	+ .Build();
338		338
339	ASSERT_EQ(kf_cacheable_tiling->outputs_creator(nullptr, run_context), ge::GRAPH_SUCCESS);	339	ASSERT_EQ(kf_cacheable_tiling->outputs_creator(nullptr, run_context), ge::GRAPH_SUCCESS);
340	ASSERT_EQ(kf_cacheable_tiling->run_func(run_context), ge::GRAPH_SUCCESS);	340	ASSERT_EQ(kf_cacheable_tiling->run_func(run_context), ge::GRAPH_SUCCESS);
	@@ -369,7 +369,7 @@ TEST_F(CacheableTilingUt, CacheableFallibleTiling_ok_TilingFuncSucc) {
369	auto context_holder =	369	auto context_holder =
370	KernelRunContextFaker()	370	KernelRunContextFaker()
371	.KernelIONum(2, static_cast<size_t>(kernel::FallibleTilingExOutputIndex::kFallibleOutputNum))	371	.KernelIONum(2, static_cast<size_t>(kernel::FallibleTilingExOutputIndex::kFallibleOutputNum))
372	- .Inputs({&cacheable_fwk_data, nullptr, nullptr})	372	+ .Inputs({&cacheable_fwk_data, nullptr, nullptr, nullptr})
373	.Build();	373	.Build();
374	auto context = context_holder.GetContext<KernelContext>();	374	auto context = context_holder.GetContext<KernelContext>();
375	ASSERT_EQ(kf_cacheable_fallible_tiling->run_func(context), ge::GRAPH_SUCCESS);	375	ASSERT_EQ(kf_cacheable_fallible_tiling->run_func(context), ge::GRAPH_SUCCESS);

Mtests/ge/ut/ge/runtime/fast_v2/kernel/tiling_unittest.cc+62-5

	@@ -101,7 +101,7 @@ UINT32 StubFailedTiling(KernelContext *) {
101	}	101	}
102		102
103	TEST_F(TilingUT, Tiling_Failed_WhenTilingFuncFailed) {	103	TEST_F(TilingUT, Tiling_Failed_WhenTilingFuncFailed) {
104	- auto run_context = BuildKernelRunContext(3, static_cast<size_t>(kernel::TilingExOutputIndex::kNum));	104	+ auto run_context = BuildKernelRunContext(4, static_cast<size_t>(kernel::TilingExOutputIndex::kNum));
105	auto tiling_data = TilingData::CreateCap(10);	105	auto tiling_data = TilingData::CreateCap(10);
106	kernel::TilingFwkData fwk_data = {.tiling_func = reinterpret_cast<void *>(StubFailedTiling),	106	kernel::TilingFwkData fwk_data = {.tiling_func = reinterpret_cast<void *>(StubFailedTiling),
107	.launch_arg = fake_launch_arg};	107	.launch_arg = fake_launch_arg};
	@@ -391,8 +391,8 @@ TEST_F(TilingUT, FallibleTiling_ReturnSuccess_WhenTilingFuncFailed) {
391	.launch_arg = fake_launch_arg};	391	.launch_arg = fake_launch_arg};
392	auto context_holder =	392	auto context_holder =
393	KernelRunContextFaker()	393	KernelRunContextFaker()
394	- .KernelIONum(2, static_cast<size_t>(kernel::FallibleTilingExOutputIndex::kFallibleOutputNum))	394	+ .KernelIONum(4, static_cast<size_t>(kernel::FallibleTilingExOutputIndex::kFallibleOutputNum))
395	- .Inputs({&fwk_data, nullptr, nullptr})	395	+ .Inputs({&fwk_data, nullptr, nullptr, nullptr})
396	.Build();	396	.Build();
397	auto context = context_holder.GetContext<KernelContext>();	397	auto context = context_holder.GetContext<KernelContext>();
398	ASSERT_EQ(kernel::FallibleTiling(context), ge::GRAPH_SUCCESS);	398	ASSERT_EQ(kernel::FallibleTiling(context), ge::GRAPH_SUCCESS);
	@@ -405,8 +405,8 @@ TEST_F(TilingUT, FallibleTiling_ReturnSuccess_WhenTilingFuncSuccess) {
405	.launch_arg = fake_launch_arg};	405	.launch_arg = fake_launch_arg};
406	auto context_holder =	406	auto context_holder =
407	KernelRunContextFaker()	407	KernelRunContextFaker()
408	- .KernelIONum(2, static_cast<size_t>(kernel::FallibleTilingExOutputIndex::kFallibleOutputNum))	408	+ .KernelIONum(4, static_cast<size_t>(kernel::FallibleTilingExOutputIndex::kFallibleOutputNum))
409	- .Inputs({&fwk_data, nullptr, nullptr})	409	+ .Inputs({&fwk_data, nullptr, nullptr, nullptr})
410	.Build();	410	.Build();
411	auto context = context_holder.GetContext<KernelContext>();	411	auto context = context_holder.GetContext<KernelContext>();
412	ASSERT_EQ(kernel::FallibleTiling(context), ge::GRAPH_SUCCESS);	412	ASSERT_EQ(kernel::FallibleTiling(context), ge::GRAPH_SUCCESS);
	@@ -777,4 +777,61 @@ TEST_F(TilingUT, TilingMemCheck_succ_aligned) {
777	ge::DumpStub::GetInstance().Clear();	777	ge::DumpStub::GetInstance().Clear();
778	}	778	}
779		779
		780	+TEST_F(TilingUT, Tiling_WithPcieThroughFlagTrue) {
		781	+ auto workspace_holder = ContinuousVector::Create<size_t>(16);
		782	+ auto workspace = reinterpret_cast<TypedContinuousVector<size_t> *>(workspace_holder.get());
		783	+ kernel::TilingFwkData fwk_data = {.tiling_func = reinterpret_cast<void *>(SuccessTilingFunc),
		784	+ .launch_arg = fake_launch_arg};
		785	+ auto context_holder = TilingContextFaker()
		786	+ .NodeIoNum(2, 1)
		787	+ .TilingFwkData(&fwk_data)
		788	+ .Workspace(reinterpret_cast<ContinuousVector *>(workspace))
		789	+ .PcieThroughFlag(true)
		790	+ .Build();
		791	+ auto context = context_holder.GetContext<KernelContext>();
		792	+ ASSERT_EQ(kernel::Tiling(context), ge::GRAPH_SUCCESS);
		793	+}
		794	+
		795	+TEST_F(TilingUT, Tiling_WithPcieThroughFlagFalse) {
		796	+ auto workspace_holder = ContinuousVector::Create<size_t>(16);
		797	+ auto workspace = reinterpret_cast<TypedContinuousVector<size_t> *>(workspace_holder.get());
		798	+ kernel::TilingFwkData fwk_data = {.tiling_func = reinterpret_cast<void *>(SuccessTilingFunc),
		799	+ .launch_arg = fake_launch_arg};
		800	+ auto context_holder = TilingContextFaker()
		801	+ .NodeIoNum(2, 1)
		802	+ .TilingFwkData(&fwk_data)
		803	+ .Workspace(reinterpret_cast<ContinuousVector *>(workspace))
		804	+ .PcieThroughFlag(false)
		805	+ .Build();
		806	+ auto context = context_holder.GetContext<KernelContext>();
		807	+ ASSERT_EQ(kernel::Tiling(context), ge::GRAPH_SUCCESS);
		808	+}
		809	+
		810	+TEST_F(TilingUT, CheckPcieThrough_RegisteredAndReturnsFalse) {
		811	+ const auto check_pcie_through = KernelRegistry::GetInstance().FindKernelFuncs("CheckPcieThrough");
		812	+ ASSERT_NE(check_pcie_through, nullptr);
		813	+ GertTensorData td1;
		814	+ GertTensorData td2;
		815	+ auto context_holder = KernelRunContextFaker()
		816	+ .KernelIONum(2, 1)
		817	+ .Inputs({reinterpret_cast<void >(&td1), reinterpret_cast<void >(&td2)})
		818	+ .Build();
		819	+ auto context = context_holder.GetContext<KernelContext>();
		820	+ ASSERT_EQ(check_pcie_through->run_func(context), ge::GRAPH_SUCCESS);
		821	+ auto *output = context->GetOutputPointer<bool>(0U);
		822	+ ASSERT_NE(output, nullptr);
		823	+ EXPECT_FALSE(*output);
		824	+}
		825	+
		826	+TEST_F(TilingUT, CheckPcieThrough_ZeroInputsReturnsFalse) {
		827	+ const auto check_pcie_through = KernelRegistry::GetInstance().FindKernelFuncs("CheckPcieThrough");
		828	+ ASSERT_NE(check_pcie_through, nullptr);
		829	+ auto context_holder = KernelRunContextFaker().KernelIONum(0, 1).Build();
		830	+ auto context = context_holder.GetContext<KernelContext>();
		831	+ ASSERT_EQ(check_pcie_through->run_func(context), ge::GRAPH_SUCCESS);
		832	+ auto *output = context->GetOutputPointer<bool>(0U);
		833	+ ASSERT_NE(output, nullptr);
		834	+ EXPECT_FALSE(*output);
		835	+}
		836	+
780	} // namespace gert	837	} // namespace gert

Mtests/ge/ut/ge/runtime/fast_v2/lowering/lower_exe_graph_from_model_test.cc+2-2

	@@ -130,7 +130,7 @@ TEST_F(LowerExeGraphFromModelUT, LowerFromGeModel) {
130	std::map<std::string, size_t> expect_init_graph_nodes{{"AllocLaunchArg", 7},	130	std::map<std::string, size_t> expect_init_graph_nodes{{"AllocLaunchArg", 7},
131	{"AssignWeightMemory", 3},	131	{"AssignWeightMemory", 3},
132	{"BuildTensor", 2},	132	{"BuildTensor", 2},
133	- {"Const", 229},	133	+ {"Const", 236},
134	{"ConstData", 3},	134	{"ConstData", 3},
135	{"Data", 4},	135	{"Data", 4},
136	{"CreateL1Allocator", 1},	136	{"CreateL1Allocator", 1},
	@@ -164,7 +164,7 @@ TEST_F(LowerExeGraphFromModelUT, LowerFromGeModel) {
164	{"FreeBatchHbm", 7},	164	{"FreeBatchHbm", 7},
165	{"FreeMemory", 17},	165	{"FreeMemory", 17},
166	{"InferShape", 9},	166	{"InferShape", 9},
167	- {"InnerData", 151},	167	+ {"InnerData", 158},
168	{"LaunchKernelWithFlag", 7},	168	{"LaunchKernelWithFlag", 7},
169	{"CopyFlowLaunch", 3},	169	{"CopyFlowLaunch", 3},
170	{"OutputData", 1},	170	{"OutputData", 1},

Mtests/graph_metadef/ut/exe_graph/tiling_context_builder_unittest.cc+137-0

	@@ -605,4 +605,141 @@ TEST_F(TilingContextBuilderUT, GetDependInputTensorAddr_Const_Input_Success) {
605	EXPECT_EQ(ret, ge::GRAPH_SUCCESS);	605	EXPECT_EQ(ret, ge::GRAPH_SUCCESS);
606	EXPECT_NE(address, nullptr);	606	EXPECT_NE(address, nullptr);
607	}	607	}
		608	+
		609	+TEST_F(TilingContextBuilderUT, BuildWithPcieThroughFlag) {
		610	+ auto tiling_data = gert::TilingData::CreateCap(1024);
		611	+ auto workspace_size = gert::ContinuousVector::Create<size_t>(16);
		612	+ std::string op_compile_info_json = "{}";
		613	+ fe::PlatFormInfos platform_infos;
		614	+ gert::SpaceRegistryFaker::CreateDefaultSpaceRegistryImpl2();
		615	+ auto space_registry = gert::DefaultOpImplSpaceRegistryV2::GetInstance().GetSpaceRegistry();
		616	+ ASSERT_NE(space_registry, nullptr);
		617	+ auto builder = TilingContextBuilder();
		618	+
		619	+ auto foo_node = ComputeNodeFaker().NameAndType("foo", "Foo").IoNum(1, 2).InputNames({"x"}).Build();
		620	+ auto bar_node = ComputeNodeFaker().NameAndType("bar", "Bar").IoNum(2, 1).InputNames({"x", "y"}).Build();
		621	+ ge::GraphUtils::AddEdge(foo_node->GetOutDataAnchor(0), bar_node->GetInDataAnchor(0));
		622	+ ge::GraphUtils::AddEdge(foo_node->GetOutDataAnchor(1), bar_node->GetInDataAnchor(1));
		623	+ const size_t k_input_anchor = 2U;
		624	+ ge::NodeUtils::AppendInputAnchor(bar_node, k_input_anchor);
		625	+ ge::OpDescPtr op_desc = bar_node->GetOpDesc();
		626	+ ge::GeTensorDesc tensor_desc(ge::GeShape({1}));
		627	+ op_desc->AddOutputDesc("z", tensor_desc);
		628	+ op_desc->MutableInputDesc(1)->SetDataType(ge::DT_INT32);
		629	+ op_desc->MutableInputDesc(1)->SetShape(ge::GeShape({1}));
		630	+ op_desc->MutableInputDesc(1)->SetOriginShape(ge::GeShape({1}));
		631	+ auto op = ge::OpDescUtils::CreateOperatorFromNode(bar_node->shared_from_this());
		632	+ ge::graphStatus ret;
		633	+ auto tiling_context_holder = builder.CompileInfo(const_cast<char *>(op_compile_info_json.c_str()))
		634	+ .PlatformInfo(reinterpret_cast<void *>(&platform_infos))
		635	+ .TilingData(tiling_data.get())
		636	+ .Deterministic(1)
		637	+ .DeterministicLevel(1)
		638	+ .SetPcieThroughFlag(true)
		639	+ .Workspace(reinterpret_cast<gert::ContinuousVector *>(workspace_size.get()))
		640	+ .SetSpaceRegistryV2(space_registry, gert::OppImplVersionTag::kOpp)
		641	+ .Build(op, ret);
		642	+ EXPECT_EQ(ret, ge::GRAPH_SUCCESS);
		643	+ auto tiling_context = reinterpret_cast<TilingContext *>(tiling_context_holder.context_);
		644	+ EXPECT_NE(tiling_context, nullptr);
		645	+ EXPECT_EQ(tiling_context->GetPcieThroughFlag(), true);
		646	+
		647	+ bg::ValueHolder::PopGraphFrame();
		648	+ DefaultOpImplSpaceRegistryV2::GetInstance().SetSpaceRegistry(nullptr);
		649	+}
		650	+
		651	+TEST_F(TilingContextBuilderUT, BuildWithPcieThroughFlagDefault) {
		652	+ auto tiling_data = gert::TilingData::CreateCap(1024);
		653	+ auto workspace_size = gert::ContinuousVector::Create<size_t>(16);
		654	+ std::string op_compile_info_json = "{}";
		655	+ fe::PlatFormInfos platform_infos;
		656	+ gert::SpaceRegistryFaker::CreateDefaultSpaceRegistryImpl2();
		657	+ auto space_registry = gert::DefaultOpImplSpaceRegistryV2::GetInstance().GetSpaceRegistry();
		658	+ ASSERT_NE(space_registry, nullptr);
		659	+ auto builder = TilingContextBuilder();
		660	+
		661	+ auto foo_node = ComputeNodeFaker().NameAndType("foo", "Foo").IoNum(1, 2).InputNames({"x"}).Build();
		662	+ auto bar_node = ComputeNodeFaker().NameAndType("bar", "Bar").IoNum(2, 1).InputNames({"x", "y"}).Build();
		663	+ ge::GraphUtils::AddEdge(foo_node->GetOutDataAnchor(0), bar_node->GetInDataAnchor(0));
		664	+ ge::GraphUtils::AddEdge(foo_node->GetOutDataAnchor(1), bar_node->GetInDataAnchor(1));
		665	+ const size_t k_input_anchor = 2U;
		666	+ ge::NodeUtils::AppendInputAnchor(bar_node, k_input_anchor);
		667	+ ge::OpDescPtr op_desc = bar_node->GetOpDesc();
		668	+ ge::GeTensorDesc tensor_desc(ge::GeShape({1}));
		669	+ op_desc->AddOutputDesc("z", tensor_desc);
		670	+ op_desc->MutableInputDesc(1)->SetDataType(ge::DT_INT32);
		671	+ op_desc->MutableInputDesc(1)->SetShape(ge::GeShape({1}));
		672	+ op_desc->MutableInputDesc(1)->SetOriginShape(ge::GeShape({1}));
		673	+ auto op = ge::OpDescUtils::CreateOperatorFromNode(bar_node->shared_from_this());
		674	+ ge::graphStatus ret;
		675	+ auto tiling_context_holder = builder.CompileInfo(const_cast<char *>(op_compile_info_json.c_str()))
		676	+ .PlatformInfo(reinterpret_cast<void *>(&platform_infos))
		677	+ .TilingData(tiling_data.get())
		678	+ .Workspace(reinterpret_cast<gert::ContinuousVector *>(workspace_size.get()))
		679	+ .SetSpaceRegistryV2(space_registry, gert::OppImplVersionTag::kOpp)
		680	+ .Build(op, ret);
		681	+ EXPECT_EQ(ret, ge::GRAPH_SUCCESS);
		682	+ auto tiling_context = reinterpret_cast<TilingContext *>(tiling_context_holder.context_);
		683	+ EXPECT_NE(tiling_context, nullptr);
		684	+ EXPECT_EQ(tiling_context->GetPcieThroughFlag(), false);
		685	+
		686	+ bg::ValueHolder::PopGraphFrame();
		687	+ DefaultOpImplSpaceRegistryV2::GetInstance().SetSpaceRegistry(nullptr);
		688	+}
		689	+
		690	+TEST_F(TilingContextBuilderUT, BuildDeviceTilingContextWithPcieThroughFlag) {
		691	+ auto graph = ConcatV2ConstDependencyGraph();
		692	+ fe::PlatFormInfos platform_infos;
		693	+ auto node = graph->FindNode("ifa");
		694	+ ASSERT_NE(node, nullptr);
		695	+ auto op_desc = node->GetOpDesc();
		696	+ ASSERT_NE(op_desc, nullptr);
		697	+
		698	+ size_t total_plain_size{0UL};
		699	+ size_t extend_info_size{0UL};
		700	+ bg::BufferPool buffer_pool;
		701	+ auto compute_node_extend_holder = bg::CreateComputeNodeInfo(node, buffer_pool, extend_info_size);
		702	+ ASSERT_NE(compute_node_extend_holder, nullptr);
		703	+
		704	+ const size_t device_tiling_size = gert::DeviceTilingContextBuilder::CalcTotalTiledSize(op_desc);
		705	+ size_t aligned_tiling_context_size = ge::RoundUp(static_cast<uint64_t>(device_tiling_size), sizeof(uintptr_t));
		706	+ aligned_tiling_context_size += extend_info_size;
		707	+ total_plain_size += aligned_tiling_context_size;
		708	+
		709	+ const auto aligned_tiling_size = 1024UL;
		710	+ total_plain_size += aligned_tiling_size;
		711	+
		712	+ const size_t workspace_addr_size = 16 * sizeof(gert::ContinuousVector);
		713	+ total_plain_size += workspace_addr_size;
		714	+
		715	+ auto host_pointer = std::unique_ptr<uint8_t[]>(new uint8_t[total_plain_size]);
		716	+ ASSERT_NE(host_pointer, nullptr);
		717	+ auto device_addr = std::unique_ptr<uint8_t[]>(new uint8_t[total_plain_size]);
		718	+ ASSERT_NE(device_addr, nullptr);
		719	+
		720	+ uint8_t *context_host_begin = &host_pointer[aligned_tiling_size + workspace_addr_size];
		721	+ uint64_t context_dev_begin = ge::PtrToValue(device_addr.get()) + aligned_tiling_size + workspace_addr_size;
		722	+
		723	+ gert::TiledKernelContextHolder tiling_context_holder;
		724	+ tiling_context_holder.compute_node_info_size_ = extend_info_size;
		725	+ tiling_context_holder.host_compute_node_info_ = compute_node_extend_holder.get();
		726	+
		727	+ auto context_builder = gert::DeviceTilingContextBuilder();
		728	+ ge::Status ret = context_builder.PlatformInfo(reinterpret_cast<void *>(&platform_infos))
		729	+ .TilingData(device_addr.get())
		730	+ .Deterministic(0)
		731	+ .DeterministicLevel(1)
		732	+ .SetPcieThroughFlag(true)
		733	+ .CompileInfo(nullptr)
		734	+ .Workspace(ge::ValueToPtr(ge::PtrToValue(device_addr.get()) + aligned_tiling_size))
		735	+ .TiledHolder(context_host_begin, context_dev_begin,
		736	+ total_plain_size - aligned_tiling_size - workspace_addr_size)
		737	+ .Build(node, tiling_context_holder);
		738	+ EXPECT_EQ(memcpy_s(device_addr.get(), total_plain_size, host_pointer.get(), total_plain_size), 0);
		739	+
		740	+ auto device_context = reinterpret_cast<TilingContext *>(tiling_context_holder.dev_context_addr_);
		741	+ EXPECT_NE(device_context, nullptr);
		742	+ EXPECT_EQ(device_context->GetPcieThroughFlag(), true);
		743	+ EXPECT_EQ(ret, ge::SUCCESS);
		744	+}
608	} // namespace gert	745	} // namespace gert

Mtests/graph_metadef/ut/register/testcase/register_unittest.cc+79-0

	@@ -70,6 +70,7 @@ void from_json(const nlohmann::json &j, HcomTopoInfo::TopoInfo &info);
70	} // namespace ge	70	} // namespace ge
71	namespace {	71	namespace {
72	int32_t expected_py_deterministic_level = -1;	72	int32_t expected_py_deterministic_level = -1;
		73	+int32_t expected_py_pcie_through_flag = -1;
73		74
74	REG_OP(AddUt)	75	REG_OP(AddUt)
75	.INPUT(x1, TensorType({DT_FLOAT, DT_FLOAT16, DT_INT32}))	76	.INPUT(x1, TensorType({DT_FLOAT, DT_FLOAT16, DT_INT32}))
	@@ -286,6 +287,9 @@ UINT32 OpTilingStubV6(gert::TilingContext *kernel_context) {
286	if (expected_py_deterministic_level >= 0) {	287	if (expected_py_deterministic_level >= 0) {
287	EXPECT_EQ(kernel_context->GetDeterministicLevel(), expected_py_deterministic_level);	288	EXPECT_EQ(kernel_context->GetDeterministicLevel(), expected_py_deterministic_level);
288	}	289	}
		290	+ if (expected_py_pcie_through_flag >= 0) {
		291	+ EXPECT_EQ(kernel_context->GetPcieThroughFlag(), static_cast<bool>(expected_py_pcie_through_flag));
		292	+ }
289	return ge::GRAPH_SUCCESS;	293	return ge::GRAPH_SUCCESS;
290	}	294	}
291		295
	@@ -329,6 +333,7 @@ class UtestRegister : public testing::Test {
329		333
330	void TearDown() {	334	void TearDown() {
331	expected_py_deterministic_level = -1;	335	expected_py_deterministic_level = -1;
		336	+ expected_py_pcie_through_flag = -1;
332	(void)error_message::GetErrMgrErrorMessage();	337	(void)error_message::GetErrMgrErrorMessage();
333	}	338	}
334	};	339	};
	@@ -4169,3 +4174,77 @@ TEST_F(UtestRegister, IncCov_AscendCPyInterfaceGetTilingDefInfo_NullParams) {
4169	EXPECT_EQ(AscendCPyInterfaceGetTilingDefInfo(nullptr, const_cast<char *>(res_info.c_str()), size), 0);	4174	EXPECT_EQ(AscendCPyInterfaceGetTilingDefInfo(nullptr, const_cast<char *>(res_info.c_str()), size), 0);
4170	unsetenv("ENABLE_RUNTIME_V2");	4175	unsetenv("ENABLE_RUNTIME_V2");
4171	}	4176	}
		4177	+
		4178	+TEST_F(UtestRegister, new_optiling_py_interface_ok_with_pcie_through_flag) {
		4179	+ const nlohmann::json input = R"([
		4180	+{"name": "t0", "dtype": "float16","const_value": [1.1,2.1,3.1,4.1] ,"shape": [4,4,4,4], "ori_shape":[4,4,4,4],"format": "FRACTAL_Z", "sub_format" :32},
		4181	+{"dtype": "int8", "shape": [4,4,4,4], "ori_shape":[4,4,4,4],"format": "ND"}
		4182	+])"_json;
		4183	+ std::string input_str = input.dump();
		4184	+ const nlohmann::json output = R"([
		4185	+{"name": "y_0","dtype": "int8","shape": [9,9,9,9],"ori_shape" :[9,9,9,9],"format": "ND","ori_format":"ND"}])"_json;
		4186	+ std::string output_str = output.dump();
		4187	+ const char *op_type = "TestReluV2";
		4188	+ const char *cmp_info = "";
		4189	+ std::string runinfo(161, 'a');
		4190	+ size_t size = 161;
		4191	+ const char *cmp_info_hash = "";
		4192	+ uint64_t *elapse = nullptr;
		4193	+ const nlohmann::json attrs = R"([
		4194	+{ "name": "op_para_size", "dtype": "int", "value": 50}])"_json;
		4195	+ const nlohmann::json extra_infos = R"([{"pcie_through_flag": true}])"_json;
		4196	+
		4197	+ gert::SpaceRegistryFaker::CreateDefaultSpaceRegistryImpl2();
		4198	+ auto space_registry = gert::DefaultOpImplSpaceRegistryV2::GetInstance().GetSpaceRegistry();
		4199	+ ASSERT_NE(space_registry, nullptr);
		4200	+ auto op_impl_func = space_registry->CreateOrGetOpImpl(op_type);
		4201	+ op_impl_func->tiling = OpTilingStubV6;
		4202	+ op_impl_func->tiling_parse = OpTilingParseStubV5;
		4203	+ op_impl_func->compile_info_creator = CreateCompileInfo;
		4204	+ op_impl_func->compile_info_deleter = DeleteCompileInfo;
		4205	+ op_impl_func->max_tiling_data_size = 50;
		4206	+
		4207	+ expected_py_pcie_through_flag = 1;
		4208	+ EXPECT_EQ(std::string(DoOpTilingForCompile(op_type, cmp_info, cmp_info_hash, input_str.c_str(), output_str.c_str(),
		4209	+ attrs.dump().c_str(), const_cast<char *>(runinfo.c_str()), size, elapse,
		4210	+ extra_infos.dump().c_str())),
		4211	+ "{\"ret_code\":0}");
		4212	+ gert::DefaultOpImplSpaceRegistryV2::GetInstance().SetSpaceRegistry(nullptr);
		4213	+}
		4214	+
		4215	+TEST_F(UtestRegister, new_optiling_py_interface_ok_without_pcie_through_flag) {
		4216	+ const nlohmann::json input = R"([
		4217	+{"name": "t0", "dtype": "float16","const_value": [1.1,2.1,3.1,4.1] ,"shape": [4,4,4,4], "ori_shape":[4,4,4,4],"format": "FRACTAL_Z", "sub_format" :32},
		4218	+{"dtype": "int8", "shape": [4,4,4,4], "ori_shape":[4,4,4,4],"format": "ND"}
		4219	+])"_json;
		4220	+ std::string input_str = input.dump();
		4221	+ const nlohmann::json output = R"([
		4222	+{"name": "y_0","dtype": "int8","shape": [9,9,9,9],"ori_shape" :[9,9,9,9],"format": "ND","ori_format":"ND"}])"_json;
		4223	+ std::string output_str = output.dump();
		4224	+ const char *op_type = "TestReluV2";
		4225	+ const char *cmp_info = "";
		4226	+ std::string runinfo(161, 'a');
		4227	+ size_t size = 161;
		4228	+ const char *cmp_info_hash = "";
		4229	+ uint64_t *elapse = nullptr;
		4230	+ const nlohmann::json attrs = R"([
		4231	+{ "name": "op_para_size", "dtype": "int", "value": 50}])"_json;
		4232	+ const nlohmann::json extra_infos = R"([{}])"_json;
		4233	+
		4234	+ gert::SpaceRegistryFaker::CreateDefaultSpaceRegistryImpl2();
		4235	+ auto space_registry = gert::DefaultOpImplSpaceRegistryV2::GetInstance().GetSpaceRegistry();
		4236	+ ASSERT_NE(space_registry, nullptr);
		4237	+ auto op_impl_func = space_registry->CreateOrGetOpImpl(op_type);
		4238	+ op_impl_func->tiling = OpTilingStubV6;
		4239	+ op_impl_func->tiling_parse = OpTilingParseStubV5;
		4240	+ op_impl_func->compile_info_creator = CreateCompileInfo;
		4241	+ op_impl_func->compile_info_deleter = DeleteCompileInfo;
		4242	+ op_impl_func->max_tiling_data_size = 50;
		4243	+
		4244	+ expected_py_pcie_through_flag = 0;
		4245	+ EXPECT_EQ(std::string(DoOpTilingForCompile(op_type, cmp_info, cmp_info_hash, input_str.c_str(), output_str.c_str(),
		4246	+ attrs.dump().c_str(), const_cast<char *>(runinfo.c_str()), size, elapse,
		4247	+ extra_infos.dump().c_str())),
		4248	+ "{\"ret_code\":0}");
		4249	+ gert::DefaultOpImplSpaceRegistryV2::GetInstance().SetSpaceRegistry(nullptr);
		4250	+}

	@@ -25,6 +25,7 @@ class TilingContextBuilder {
25	TilingContextBuilder &CompileInfo(void *compile_info);	25	TilingContextBuilder &CompileInfo(void *compile_info);
26	TilingContextBuilder &Deterministic(int32_t deterministic);	26	TilingContextBuilder &Deterministic(int32_t deterministic);
27	TilingContextBuilder &DeterministicLevel(int32_t deterministic_level);	27	TilingContextBuilder &DeterministicLevel(int32_t deterministic_level);
		28	+ TilingContextBuilder &SetPcieThroughFlag(bool pcie_through_flag);
28	TilingContextBuilder &PlatformInfo(void *platform_info);	29	TilingContextBuilder &PlatformInfo(void *platform_info);
29	TilingContextBuilder &TilingData(void *tiling_data);	30	TilingContextBuilder &TilingData(void *tiling_data);
30	TilingContextBuilder &Workspace(ContinuousVector *workspace);	31	TilingContextBuilder &Workspace(ContinuousVector *workspace);
	@@ -44,6 +45,7 @@ class TilingContextBuilder {
44	void *platform_info_{nullptr};	45	void *platform_info_{nullptr};
45	int32_t deterministic_;	46	int32_t deterministic_;
46	int32_t deterministic_level_;	47	int32_t deterministic_level_;
		48	+ bool pcie_through_flag_ = false;
47	std::vector<std::unique_ptr<ge::Tensor>> depend_ge_tensor_holders_;	49	std::vector<std::unique_ptr<ge::Tensor>> depend_ge_tensor_holders_;
48	std::vector<std::unique_ptr<uint8_t[]>> rt_tensor_holders_;	50	std::vector<std::unique_ptr<uint8_t[]>> rt_tensor_holders_;
49	std::vector<void *> outputs_{TilingContext::kOutputNum};	51	std::vector<void *> outputs_{TilingContext::kOutputNum};

	@@ -287,7 +287,7 @@ TEST_F(AutofuseNodeUT, symtiling_kernel_test) {
287	const auto workspace_size_t = gert::ContinuousVector::Create<size_t>(16);	287	const auto workspace_size_t = gert::ContinuousVector::Create<size_t>(16);
288	auto autofuse_tiling_context_holder =	288	auto autofuse_tiling_context_holder =
289	gert::KernelRunContextBuilder()	289	gert::KernelRunContextBuilder()
290	- .Inputs({(void *)input_data_num, &shape0, &shape1, &parse_data, fwk_data, nullptr, nullptr})	290	+ .Inputs({(void *)input_data_num, &shape0, &shape1, &parse_data, fwk_data, nullptr, nullptr, nullptr})
291	.Outputs({nullptr, nullptr, nullptr, nullptr, static_cast<void *>(workspace_size_t.get()), nullptr, nullptr,	291	.Outputs({nullptr, nullptr, nullptr, nullptr, static_cast<void *>(workspace_size_t.get()), nullptr, nullptr,
292	nullptr, nullptr, nullptr, nullptr, nullptr})	292	nullptr, nullptr, nullptr, nullptr, nullptr})
293	.Build(op_desc);	293	.Build(op_desc);
	@@ -372,8 +372,8 @@ TEST_F(AutofuseNodeUT, cacheablesymtiling_kernel_test) {
372	const auto cacheable_workspace_size_t = gert::ContinuousVector::Create<size_t>(16);	372	const auto cacheable_workspace_size_t = gert::ContinuousVector::Create<size_t>(16);
373	auto cacheable_tiling_context_holder =	373	auto cacheable_tiling_context_holder =
374	gert::KernelRunContextBuilder()	374	gert::KernelRunContextBuilder()
375	- .Inputs(	375	+ .Inputs({(void *)input_num, &shape0, &shape1, &parse_data, all_sym_num_vector, tiling_fwk_data, nullptr,
376	- {(void *)input_num, &shape0, &shape1, &parse_data, all_sym_num_vector, tiling_fwk_data, nullptr, nullptr})	376	+ nullptr, nullptr})
377	.Outputs({nullptr, nullptr, nullptr, nullptr, static_cast<void *>(cacheable_workspace_size_t.get()), nullptr,	377	.Outputs({nullptr, nullptr, nullptr, nullptr, static_cast<void *>(cacheable_workspace_size_t.get()), nullptr,
378	nullptr, nullptr, nullptr, nullptr, nullptr, nullptr})	378	nullptr, nullptr, nullptr, nullptr, nullptr, nullptr})
379	.Build(op_desc);	379	.Build(op_desc);