* SPDX-License-Identifier: MIT
* Copyright (c) Huawei Technologies Co., Ltd. 2021-2025. All rights reserved.
* Description: URMA opcode header file
* Author: Ouyang Changchun, Yan Fangfang, Qian Guoxin
* Create: 2021-09-26
* Note:
* History: 2021-09-26 Create File
*/
#ifndef URMA_OPCODE_H
#define URMA_OPCODE_H
#include <errno.h>
#define URMA_TOKEN_NONE 0
#define URMA_TOKEN_PLAIN_TEXT 1
#define URMA_TOKEN_SIGNED 2
#define URMA_TOKEN_ALL_ENCRYPTED 3
#define URMA_TOKEN_RESERVED 4
#define URMA_TOKEN_ID_INVALID 0
#define URMA_TOKEN_ID_VALID 1
#define URMA_DSVA_DISABLE 0
#define URMA_DSVA_ENABLE 1
#define URMA_NON_CACHEABLE 0
#define URMA_CACHEABLE 1
* READ, WRITE, and ATOMIC but external access is denied.
* If URMA_ACCESS_LOCAL_ONLY is not set, in addition to having all permissions for local access,
* the configuration of external access permissions is determined by the following three types, and
* it takes effect according to the combination of READ, WRITE, and ATOMIC configured by the user.
*/
#define URMA_ACCESS_LOCAL_ONLY (0x1 << 0)
#define URMA_ACCESS_READ (0x1 << 1)
#define URMA_ACCESS_WRITE (0x1 << 2)
#define URMA_ACCESS_ATOMIC (0x1 << 3)
#define URMA_LOCAL_MEMORY 0
#define URMA_REMOTE_MEMORY 1
#define URMA_SEG_NOMAP 0
#define URMA_SEG_MAPPED 1
#define URMA_ADDR_TYPE_MVA 0
#define URMA_ADDR_TYPE_UBVA 1
#define URMA_COMPLETE_ENABLE 1
#define URMA_COMPLETE_DISABLE 0
#define URMA_COMPLETE_TYPE_JFC 0
#define URMA_COMPLETE_TYPE_CF 1
#define URMA_DEPENDENCY_NONE 0
#define URMA_DEPENDENCY_FIRST \
1
of the current command. */
#define URMA_DEPENDENCY_DELAY \
2
that the preamble depends on is executed successfully. */
#define URMA_NOTIFY_DISABLE 0
#define URMA_NOTIFY_ENABLE 1
#define URMA_NOTIFY_TYPE_JFC 0
#define URMA_NOTIFY_TYPE_RVA 1
#define URMA_INLINE_DISABLE 0
#define URMA_INLINE_ENABLE 1
#define URMA_SOLICITED_DISABLE 0
#define URMA_SOLICITED_ENABLE 1
#define URMA_FENCE_DISABLE 0
#define URMA_FENCE_ENABLE 1
#define URMA_REGULAR 1
#define URMA_IRREGULAR 0
#define URMA_NO_TAG_MATCHING 0
#define URMA_WITH_TAG_MATCHING 1
#define URMA_NONPOST_LS 0
#define URMA_POST_LS 1
#define URMA_NO_SHARE_JFR 0
#define URMA_SHARE_JFR 1
#define URMA_TYPICAL_RNR_RETRY 7
#define URMA_TYPICAL_ERR_TIMEOUT 17
#define URMA_TYPICAL_MIN_RNR_TIMER 12
#define URMA_MAX_PRIORITY 15
typedef enum urma_place_order {
URMA_NO_ORDER = 0,
URMA_RELAX_ORDER,
URMA_STRONG_ORDER
} urma_place_order_t;
typedef enum urma_opcode {
URMA_OPC_WRITE = 0x00,
URMA_OPC_WRITE_IMM = 0x01,
URMA_OPC_WRITE_NOTIFY = 0x02,
URMA_OPC_READ = 0x10,
URMA_OPC_CAS = 0x20,
URMA_OPC_SWAP = 0x21,
URMA_OPC_FADD = 0x22,
URMA_OPC_FSUB = 0x23,
URMA_OPC_FAND = 0x24,
URMA_OPC_FOR = 0x25,
URMA_OPC_FXOR = 0x26,
URMA_OPC_SEND = 0x40,
URMA_OPC_SEND_IMM = 0x41,
URMA_OPC_SEND_INVALIDATE = 0x42,
URMA_OPC_NOP = 0x51,
URMA_OPC_WRITE_ATOMIC = 0x60,
URMA_OPC_LAST
} urma_opcode_t;
typedef int urma_status_t;
#define URMA_SUCCESS 0
#define URMA_EAGAIN EAGAIN
#define URMA_ENOMEM ENOMEM
#define URMA_ENOPERM EPERM
#define URMA_ETIMEOUT ETIMEDOUT
#define URMA_EINVAL EINVAL
#define URMA_EEXIST EEXIST
#define URMA_EINPROGRESS EINPROGRESS
#define URMA_FAIL 0x1000
typedef enum urma_cr_status {
URMA_CR_SUCCESS = 0,
URMA_CR_UNSUPPORTED_OPCODE_ERR,
URMA_CR_LOC_LEN_ERR,
URMA_CR_LOC_OPERATION_ERR,
URMA_CR_LOC_ACCESS_ERR,
URMA_CR_REM_RESP_LEN_ERR,
URMA_CR_REM_UNSUPPORTED_REQ_ERR,
URMA_CR_REM_OPERATION_ERR,
URMA_CR_REM_ACCESS_ABORT_ERR,
URMA_CR_ACK_TIMEOUT_ERR,
URMA_CR_RNR_RETRY_CNT_EXC_ERR,
URMA_CR_WR_FLUSH_ERR,
URMA_CR_WR_SUSPEND_DONE,
URMA_CR_WR_FLUSH_ERR_DONE,
URMA_CR_WR_UNHANDLED,
URMA_CR_LOC_DATA_POISON,
URMA_CR_REM_DATA_POISON,
} urma_cr_status_t;
typedef enum urma_cr_opcode {
URMA_CR_OPC_SEND = 0x00,
URMA_CR_OPC_SEND_WITH_IMM,
URMA_CR_OPC_SEND_WITH_INV,
URMA_CR_OPC_WRITE_WITH_IMM,
} urma_cr_opcode_t;
typedef enum urma_async_event_type {
URMA_EVENT_JFC_ERR,
URMA_EVENT_JFS_ERR,
URMA_EVENT_JFR_ERR,
URMA_EVENT_JFR_LIMIT,
URMA_EVENT_JETTY_ERR,
URMA_EVENT_JETTY_LIMIT,
URMA_EVENT_JETTY_GRP_ERR,
URMA_EVENT_PORT_ACTIVE,
URMA_EVENT_PORT_DOWN,
URMA_EVENT_DEV_FATAL,
URMA_EVENT_EID_CHANGE,
URMA_EVENT_ELR_ERR,
URMA_EVENT_ELR_DONE
} urma_async_event_type_t;
typedef enum urma_jfc_state {
URMA_JFC_STATE_INVALID = 0,
URMA_JFC_STATE_VALID,
URMA_JFC_STATE_ERROR
} urma_jfc_state_t;
typedef enum urma_jetty_state {
URMA_JETTY_STATE_RESET = 0,
URMA_JETTY_STATE_READY,
URMA_JETTY_STATE_SUSPENDED,
URMA_JETTY_STATE_ERROR
} urma_jetty_state_t;
typedef enum urma_jfr_state {
URMA_JFR_STATE_RESET = 0,
URMA_JFR_STATE_READY,
URMA_JFR_STATE_ERROR
} urma_jfr_state_t;
#define URMA_JFS_DEPTH 0x0001
#define URMA_JFS_FLAG 0x0002
#define URMA_JFS_TRANS_MODE 0x0003
#define URMA_JFS_PRIORITY 0x0004
#define URMA_JFS_MAX_SGE 0x0005
#define URMA_JFS_MAX_RSGE 0x0006
#define URMA_JFS_MAX_INLINE_DATA 0x0007
#define URMA_JFS_RNR_RETRY 0x0008
#define URMA_JFS_ERR_TIMEOUT 0x0009
#define URMA_JFS_BIND_JFC 0x000a
#define URMA_JFS_USER_CTX 0x000b
#define URMA_JFS_SQE_BASE_ADDR 0x000c
#define URMA_JFS_ID 0x000d
#define URMA_JFS_DB_ADDR 0x000e
#define URMA_JFS_DB_STATUS 0x000f
#define URMA_JFS_PI 0x0010
#define URMA_JFS_PI_TYPE 0x0011
#define URMA_JFS_CI 0x0012
#define URMA_JFS_FULL_CTX 0x0013
#define URMA_JFR_DEPTH 0x1001
#define URMA_JFR_FLAG 0x1002
#define URMA_JFR_TRANS_MODE 0x1003
#define URMA_JFR_MAX_SGE 0x1004
#define URMA_JFR_MIN_RNR_TIMER 0x1005
#define URMA_JFR_BIND_JFC 0x1006
#define URMA_JFR_TOKEN_VALUE 0x1007
#define URMA_JFR_USER_CTX 0x1008
#define URMA_JFR_RQE_BASE_ADDR 0x1009
#define URMA_JFR_ID 0x100a
#define URMA_JFR_DB_ADDR 0x100b
#define URMA_JFR_DB_STATUS 0x100c
#define URMA_JFR_PI 0x100d
#define URMA_JFR_PI_TYPE 0x100e
#define URMA_JFR_CI 0x100f
#define URMA_JFR_FULL_CTX 0x1010
#define URMA_JFC_DEPTH 0x2001
#define URMA_JFC_CEQN 0x2002
#define URMA_JFC_FLAG 0x2003
#define URMA_JFC_BIND_JFCE 0x2004
#define URMA_JFC_USER_CTX 0x2005
#define URMA_JFC_CQE_BASE_ADDR 0x2006
#define URMA_JFC_ID 0x2007
#define URMA_JFC_DB_ADDR 0x2008
#define URMA_JFC_DB_STATUS 0x2009
#define URMA_JFC_PI 0x200a
#define URMA_JFC_PI_TYPE 0x200b
#define URMA_JFC_CI 0x200c
#define URMA_JFC_FULL_CTX 0x200d
#define URMA_JETTY_ID 0x3001
#define URMA_JETTY_FLAG 0x3002
#define URMA_JETTY_BIND_JFR 0x3003
#define URMA_JETTY_BIND_RX_JFC 0x3004
#define URMA_JETTY_BIND_JTG 0x3005
#define URMA_JETTY_USER_CTX 0x3006
#define URMA_JETTY_FULL_CTX 0x3007
#endif