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refactor: 将AscendC::MicroAPI替换为AscendC::Reg #1175
liu-wei创建于 7月27日
refactor: 将AscendC::MicroAPI替换为AscendC::Reg #1175
已合并
liu-wei创建于 7月27日
从liu-wei/ops-cvmaster_microApi2Reg合入到cann/ops-cvmaster
共 10 个文件变更+486-509
Mdocs/zh/develop/cross_platform_migration_guide.md+25-25
@@ -209,18 +209,18 @@ Ascend 950系列引入了Regbase编程范式，相比传统的Membase（Vector A
209 209 
210**特点**210**特点**
211 211 
212-- 使用`AscendC::MicroAPI`命名空间下的底层API212+- 使用`AscendC::Reg`命名空间下的底层API
213- 直接操作寄存器`RegTensor<T>`而非显式管理UB缓冲队列213- 直接操作寄存器`RegTensor<T>`而非显式管理UB缓冲队列
214- 通过`MaskReg`实现灵活的元素级掩码控制214- 通过`MaskReg`实现灵活的元素级掩码控制
215 215 
216**与Membase编程模型对比**216**与Membase编程模型对比**
217 217 
218-| 特性 | Membase（传统Vector API） | Regbase（MicroAPI） |218+| 特性 | Membase（传统Vector API） | Regbase（Reg） |
219|------|---------------------------|---------------------|219|------|---------------------------|---------------------|
220| 数据载体 | `LocalTensor<T>` + Queue机制 | `RegTensor<T>`寄存器 |220| 数据载体 | `LocalTensor<T>` + Queue机制 | `RegTensor<T>`寄存器 |
221| 内存管理 | 显式Alloc/EnQue/DeQue/Free | 寄存器自动分配 |221| 内存管理 | 显式Alloc/EnQue/DeQue/Free | 寄存器自动分配 |
222| 掩码控制 | 函数参数控制 | `MaskReg`寄存器控制 |222| 掩码控制 | 函数参数控制 | `MaskReg`寄存器控制 |
223-| 数据搬运 | `DataCopy`/`DataCopyPad` | `MicroAPI::DataCopy` + 分发模式 |223+| 数据搬运 | `DataCopy`/`DataCopyPad` | `Reg::DataCopy` + 分发模式 |
224 224 
225**代码示例**225**代码示例**
226 226 
@@ -228,24 +228,24 @@ Ascend 950系列引入了Regbase编程范式，相比传统的Membase（Vector A
228__simd_vf__ __aicore__ void GenIndexBuf(ubuf int32_t* helpAddr, int32_t colFactor)228__simd_vf__ __aicore__ void GenIndexBuf(ubuf int32_t* helpAddr, int32_t colFactor)
229{229{
230 // 声明寄存器张量230 // 声明寄存器张量
231- AscendC::MicroAPI::RegTensor<int32_t> v0;231+ AscendC::Reg::RegTensor<int32_t> v0;
232- AscendC::MicroAPI::RegTensor<int32_t> v1;232+ AscendC::Reg::RegTensor<int32_t> v1;
233- AscendC::MicroAPI::RegTensor<int32_t> vd1;233+ AscendC::Reg::RegTensor<int32_t> vd1;
234 234 
235 // 创建全量掩码235 // 创建全量掩码
236- AscendC::MicroAPI::MaskReg preg =236+ AscendC::Reg::MaskReg preg =
237- AscendC::MicroAPI::CreateMask<int32_t, AscendC::MicroAPI::MaskPattern::ALL>();237+ AscendC::Reg::CreateMask<int32_t, AscendC::Reg::MaskPattern::ALL>();
238 238 
239 // 标量复制到寄存器239 // 标量复制到寄存器
240- AscendC::MicroAPI::Duplicate(v1, colFactor, preg);240+ AscendC::Reg::Duplicate(v1, colFactor, preg);
241 // 生成序列 [0, 1, 2, ...]241 // 生成序列 [0, 1, 2, ...]
242- AscendC::MicroAPI::Arange(v0, 0);242+ AscendC::Reg::Arange(v0, 0);
243 // 向量运算243 // 向量运算
244- AscendC::MicroAPI::Div(vd1, v0, v1, preg);244+ AscendC::Reg::Div(vd1, v0, v1, preg);
245- AscendC::MicroAPI::Mul(vd2, vd1, v1, preg);245+ AscendC::Reg::Mul(vd2, vd1, v1, preg);
246- AscendC::MicroAPI::Sub(vd3, v0, vd2, preg);246+ AscendC::Reg::Sub(vd3, v0, vd2, preg);
247 // 寄存器数据写回UB247 // 寄存器数据写回UB
248- AscendC::MicroAPI::DataCopy(helpAddr, vd3, preg);248+ AscendC::Reg::DataCopy(helpAddr, vd3, preg);
249}249}
250```250```
251 251 
@@ -253,17 +253,17 @@ __simd_vf__ __aicore__ void GenIndexBuf(ubuf int32_t* helpAddr, int32_t colFacto
253// 动态掩码：处理尾部不完整数据253// 动态掩码：处理尾部不完整数据
254__simd_vf__ __aicore__ void GatherProcess(ubuf int8_t* curYAddr, uint16_t repeatTimes, uint16_t computeSize)254__simd_vf__ __aicore__ void GatherProcess(ubuf int8_t* curYAddr, uint16_t repeatTimes, uint16_t computeSize)
255{255{
256- MicroAPI::RegTensor<int8_t> vregTemp;256+ Reg::RegTensor<int8_t> vregTemp;
257- MicroAPI::MaskReg preg;257+ Reg::MaskReg preg;
258 258 
259 for (uint16_t r = 0; r < repeatTimes; r++) {259 for (uint16_t r = 0; r < repeatTimes; r++) {
260 // 根据剩余元素数更新掩码260 // 根据剩余元素数更新掩码
261- preg = MicroAPI::UpdateMask<int8_t>(sreg);261+ preg = Reg::UpdateMask<int8_t>(sreg);
262 // 创建地址偏移寄存器262 // 创建地址偏移寄存器
263- MicroAPI::AddrReg offset = MicroAPI::CreateAddrReg<int8_t>(r, computeSize);263+ Reg::AddrReg offset = Reg::CreateAddrReg<int8_t>(r, computeSize);
264- MicroAPI::DataCopy(vregTemp, curXAddr, offset);264+ Reg::DataCopy(vregTemp, curXAddr, offset);
265 // 带掩码的数据存储265 // 带掩码的数据存储
266- MicroAPI::DataCopy(curYAddr, vregTemp, offset, preg);266+ Reg::DataCopy(curYAddr, vregTemp, offset, preg);
267 }267 }
268}268}
269```269```
@@ -272,16 +272,16 @@ __simd_vf__ __aicore__ void GatherProcess(ubuf int8_t* curYAddr, uint16_t repeat
272// 数据聚合272// 数据聚合
273__VEC_SCOPE_273__VEC_SCOPE_
274{274{
275- MicroAPI::RegTensor<uint32_t> indicesReg;275+ Reg::RegTensor<uint32_t> indicesReg;
276- MicroAPI::RegTensor<int32_t> vd0;276+ Reg::RegTensor<int32_t> vd0;
277 277 
278 for (uint16_t indices = 0; indices < indicesLoopNum; indices++) {278 for (uint16_t indices = 0; indices < indicesLoopNum; indices++) {
279 // 加载索引（E2B分发模式：将标量广播到向量）279 // 加载索引（E2B分发模式：将标量广播到向量）
280- MicroAPI::DataCopy<uint32_t, MicroAPI::LoadDist::DIST_E2B_B32>(indicesReg, indicesAddr);280+ Reg::DataCopy<uint32_t, Reg::LoadDist::DIST_E2B_B32>(indicesReg, indicesAddr);
281 // 根据索引进行Gather数据聚合281 // 根据索引进行Gather数据聚合
282- MicroAPI::DataCopyGather(vd0, curXAddr, indicesReg, preg);282+ Reg::DataCopyGather(vd0, curXAddr, indicesReg, preg);
283 // 数据块拷贝输出283 // 数据块拷贝输出
284- MicroAPI::DataCopy<int32_t, MicroAPI::DataCopyMode::DATA_BLOCK_COPY>(284+ Reg::DataCopy<int32_t, Reg::DataCopyMode::DATA_BLOCK_COPY>(
285 curYAddr, vd0, blockStride, preg);285 curYAddr, vd0, blockStride, preg);
286 }286 }
287}287}
Mimage/nms_with_mask/op_kernel/arch35/nms_with_mask_regbase_base.h+25-25
@@ -41,56 +41,56 @@ static constexpr int32_t VL_SIZE = 256;
41static constexpr int32_t VL_SIZE_FLOAT = 64;41static constexpr int32_t VL_SIZE_FLOAT = 64;
42static constexpr MultiCopyConfig copyConfig = {false, 0, 0, false};42static constexpr MultiCopyConfig copyConfig = {false, 0, 0, false};
43 43 
44-static constexpr MicroAPI::CastTrait castTraitB16ToB32 = {MicroAPI::RegLayout::ZERO, MicroAPI::SatMode::UNKNOWN,44+static constexpr Reg::CastTrait castTraitB16ToB32 = {Reg::RegLayout::ZERO, Reg::SatMode::UNKNOWN,
45- MicroAPI::MaskMergeMode::ZEROING, RoundMode::UNKNOWN};45+ Reg::MaskMergeMode::ZEROING, RoundMode::UNKNOWN};
46 46 
47template <typename T, bool isBroadcast>47template <typename T, bool isBroadcast>
48-__aicore__ inline void CopyInReg(MicroAPI::RegTensor<float>& vregIn, __ubuf__ T* inAddr, MicroAPI::MaskReg& mask)48+__aicore__ inline void CopyInReg(Reg::RegTensor<float>& vregIn, __ubuf__ T* inAddr, Reg::MaskReg& mask)
49{49{
50 if constexpr (sizeof(T) == sizeof(float)) {50 if constexpr (sizeof(T) == sizeof(float)) {
51 if constexpr (isBroadcast) {51 if constexpr (isBroadcast) {
52- MicroAPI::DataCopy<T, MicroAPI::LoadDist::DIST_BRC_B32>(vregIn, inAddr);52+ Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B32>(vregIn, inAddr);
53 } else {53 } else {
54- MicroAPI::DataCopy<T>(vregIn, inAddr);54+ Reg::DataCopy<T>(vregIn, inAddr);
55 }55 }
56 } else {56 } else {
57- MicroAPI::RegTensor<T> vregInB16;57+ Reg::RegTensor<T> vregInB16;
58 if constexpr (isBroadcast) {58 if constexpr (isBroadcast) {
59- MicroAPI::DataCopy<T, MicroAPI::LoadDist::DIST_BRC_B16>(vregInB16, inAddr);59+ Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B16>(vregInB16, inAddr);
60 } else {60 } else {
61- MicroAPI::DataCopy<T, MicroAPI::LoadDist::DIST_UNPACK_B16>(vregInB16, inAddr);61+ Reg::DataCopy<T, Reg::LoadDist::DIST_UNPACK_B16>(vregInB16, inAddr);
62 }62 }
63- MicroAPI::Cast<float, T, castTraitB16ToB32>(vregIn, vregInB16, mask);63+ Reg::Cast<float, T, castTraitB16ToB32>(vregIn, vregInB16, mask);
64 }64 }
65}65}
66 66 
67template <typename T, bool isBroadcast>67template <typename T, bool isBroadcast>
68-__aicore__ inline void CopyInReg(MicroAPI::RegTensor<float>& vregIn, MicroAPI::RegTensor<T>& vregInB16,68+__aicore__ inline void CopyInReg(Reg::RegTensor<float>& vregIn, Reg::RegTensor<T>& vregInB16, __ubuf__ T* inAddr,
69- __ubuf__ T* inAddr, MicroAPI::MaskReg& mask)69+ Reg::MaskReg& mask)
70{70{
71 if constexpr (sizeof(T) == sizeof(float)) {71 if constexpr (sizeof(T) == sizeof(float)) {
72 if constexpr (isBroadcast) {72 if constexpr (isBroadcast) {
73- MicroAPI::DataCopy<T, MicroAPI::LoadDist::DIST_BRC_B32>(vregIn, inAddr);73+ Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B32>(vregIn, inAddr);
74 } else {74 } else {
75- MicroAPI::DataCopy<T>(vregIn, inAddr);75+ Reg::DataCopy<T>(vregIn, inAddr);
76 }76 }
77 } else {77 } else {
78 if constexpr (isBroadcast) {78 if constexpr (isBroadcast) {
79- MicroAPI::DataCopy<T, MicroAPI::LoadDist::DIST_BRC_B16>(vregInB16, inAddr);79+ Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B16>(vregInB16, inAddr);
80 } else {80 } else {
81- MicroAPI::DataCopy<T, MicroAPI::LoadDist::DIST_UNPACK_B16>(vregInB16, inAddr);81+ Reg::DataCopy<T, Reg::LoadDist::DIST_UNPACK_B16>(vregInB16, inAddr);
82 }82 }
83- MicroAPI::Cast<float, T, castTraitB16ToB32>(vregIn, vregInB16, mask);83+ Reg::Cast<float, T, castTraitB16ToB32>(vregIn, vregInB16, mask);
84 }84 }
85}85}
86 86 
87template <typename T, bool isBroadcast>87template <typename T, bool isBroadcast>
88-__aicore__ inline void CopyInRegToFP32(MicroAPI::RegTensor<float>& vregIn, __ubuf__ T* inAddr, MicroAPI::MaskReg& mask)88+__aicore__ inline void CopyInRegToFP32(Reg::RegTensor<float>& vregIn, __ubuf__ T* inAddr, Reg::MaskReg& mask)
89{89{
90 if constexpr (isBroadcast) {90 if constexpr (isBroadcast) {
91- MicroAPI::DataCopy<T, MicroAPI::LoadDist::DIST_BRC_B32>(vregIn, inAddr);91+ Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B32>(vregIn, inAddr);
92 } else {92 } else {
93- MicroAPI::DataCopy<T>(vregIn, inAddr);93+ Reg::DataCopy<T>(vregIn, inAddr);
94 }94 }
95}95}
96 96 
@@ -109,12 +109,12 @@ private:
109 __aicore__ inline void CopyIn(int64_t refGroupIdx, int64_t dstGroupIdx, int32_t refCount, int32_t dstCount);109 __aicore__ inline void CopyIn(int64_t refGroupIdx, int64_t dstGroupIdx, int32_t refCount, int32_t dstCount);
110 __aicore__ inline void ComputeMask(int64_t refGroupIdx, int64_t dstGroupIdx, int32_t refCount, int32_t dstCount);110 __aicore__ inline void ComputeMask(int64_t refGroupIdx, int64_t dstGroupIdx, int32_t refCount, int32_t dstCount);
111 __aicore__ inline void ComputeRefArea(__ubuf__ T* refLocalAddr, __ubuf__ float* refAreaAddr, int32_t refCount);111 __aicore__ inline void ComputeRefArea(__ubuf__ T* refLocalAddr, __ubuf__ float* refAreaAddr, int32_t refCount);
112- __aicore__ inline void CalcIntersection(MicroAPI::MaskReg& pregIou, MicroAPI::RegTensor<float>& sumArea,112+ __aicore__ inline void CalcIntersection(Reg::MaskReg& pregIou, Reg::RegTensor<float>& sumArea,
113- MicroAPI::RegTensor<float>& vregZeros, MicroAPI::RegTensor<float>& refX1,113+ Reg::RegTensor<float>& vregZeros, Reg::RegTensor<float>& refX1,
114- MicroAPI::RegTensor<float>& refY1, MicroAPI::RegTensor<float>& refX2,114+ Reg::RegTensor<float>& refY1, Reg::RegTensor<float>& refX2,
115- MicroAPI::RegTensor<float>& refY2, MicroAPI::RegTensor<float>& dstX1,115+ Reg::RegTensor<float>& refY2, Reg::RegTensor<float>& dstX1,
116- MicroAPI::RegTensor<float>& dstY1, MicroAPI::RegTensor<float>& dstX2,116+ Reg::RegTensor<float>& dstY1, Reg::RegTensor<float>& dstX2,
117- MicroAPI::RegTensor<float>& dstY2, MicroAPI::MaskReg& preg);117+ Reg::RegTensor<float>& dstY2, Reg::MaskReg& preg);
118 template <bool dstIsOddBlock>118 template <bool dstIsOddBlock>
119 __aicore__ inline void ComputeMaskVf(__ubuf__ T* refLocalAddr, __ubuf__ T* dstLocalAddr,119 __aicore__ inline void ComputeMaskVf(__ubuf__ T* refLocalAddr, __ubuf__ T* dstLocalAddr,
120 __ubuf__ float* refAreaAddr, __ubuf__ int32_t* maskUbAddr, int32_t refCount,120 __ubuf__ float* refAreaAddr, __ubuf__ int32_t* maskUbAddr, int32_t refCount,
Mimage/nms_with_mask/op_kernel/arch35/nms_with_mask_regbase_multiprocess.h+130-132
@@ -348,39 +348,38 @@ __aicore__ inline void NMSWithMaskRegbaseMultiProcess<T>::ComputeNMSForDiagonal(
348 uint16_t loopPerRow = Ops::Base::CeilDiv(dstCount, vlSize); // how many loops to iterate per row348 uint16_t loopPerRow = Ops::Base::CeilDiv(dstCount, vlSize); // how many loops to iterate per row
349 __VEC_SCOPE__349 __VEC_SCOPE__
350 {350 {
351- MicroAPI::RegTensor<uint8_t> refTensor;351+ Reg::RegTensor<uint8_t> refTensor;
352- MicroAPI::RegTensor<uint8_t> dstTensor;352+ Reg::RegTensor<uint8_t> dstTensor;
353- MicroAPI::RegTensor<uint8_t> vregZeros;353+ Reg::RegTensor<uint8_t> vregZeros;
354- MicroAPI::RegTensor<uint8_t> outTensor;354+ Reg::RegTensor<uint8_t> outTensor;
355- MicroAPI::MaskReg preg;355+ Reg::MaskReg preg;
356- MicroAPI::MaskReg iouMask;356+ Reg::MaskReg iouMask;
357- MicroAPI::MaskReg removeMask;357+ Reg::MaskReg removeMask;
358- MicroAPI::MaskReg refMask;358+ Reg::MaskReg refMask;
359- MicroAPI::MaskReg trilMask; // preg for lower triangular359+ Reg::MaskReg trilMask; // preg for lower triangular
360- MicroAPI::MaskReg triuMask; // preg for upper triangular360+ Reg::MaskReg triuMask; // preg for upper triangular
361- MicroAPI::MaskReg pregAll = MicroAPI::CreateMask<uint8_t, MicroAPI::MaskPattern::ALL>();361+ Reg::MaskReg pregAll = Reg::CreateMask<uint8_t, Reg::MaskPattern::ALL>();
362- MicroAPI::Duplicate<uint8_t>(vregZeros, 0, pregAll);362+ Reg::Duplicate<uint8_t>(vregZeros, 0, pregAll);
363 for (uint16_t rowIdx = 0; rowIdx < rowNum; rowIdx++) {363 for (uint16_t rowIdx = 0; rowIdx < rowNum; rowIdx++) {
364- MicroAPI::LocalMemBar<MicroAPI::MemType::VEC_STORE, MicroAPI::MemType::VEC_LOAD>();364+ Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_LOAD>();
365 uint32_t rowEleNum = static_cast<uint32_t>(dstCount);365 uint32_t rowEleNum = static_cast<uint32_t>(dstCount);
366 uint32_t trilEleNum = rowIdx + 1;366 uint32_t trilEleNum = rowIdx + 1;
367- MicroAPI::DataCopy<uint8_t, MicroAPI::LoadDist::DIST_BRC_B8>(refTensor, dstMaskAddr + rowIdx);367+ Reg::DataCopy<uint8_t, Reg::LoadDist::DIST_BRC_B8>(refTensor, dstMaskAddr + rowIdx);
368- MicroAPI::CompareScalar<uint8_t, CMPMODE::EQ>(368+ Reg::CompareScalar<uint8_t, CMPMODE::EQ>(
369 refMask, refTensor, 1, pregAll); // refMask表示要么全选要么全不选，基于当前refTensor是否全为1来判断369 refMask, refTensor, 1, pregAll); // refMask表示要么全选要么全不选，基于当前refTensor是否全为1来判断
370 for (uint16_t loopIndex = 0; loopIndex < loopPerRow; loopIndex++) {370 for (uint16_t loopIndex = 0; loopIndex < loopPerRow; loopIndex++) {
371- preg = MicroAPI::UpdateMask<uint8_t>(rowEleNum);371+ preg = Reg::UpdateMask<uint8_t>(rowEleNum);
372- trilMask = MicroAPI::UpdateMask<uint8_t>(trilEleNum);372+ trilMask = Reg::UpdateMask<uint8_t>(trilEleNum);
373- MicroAPI::MaskNot(triuMask, trilMask, pregAll);373+ Reg::MaskNot(triuMask, trilMask, pregAll);
374- MicroAPI::AddrReg offset = MicroAPI::CreateAddrReg<int32_t>(374+ Reg::AddrReg offset = Reg::CreateAddrReg<int32_t>(rowIdx, groupSize_ / BIT_PER_BYTE / sizeof(int32_t),
375- rowIdx, groupSize_ / BIT_PER_BYTE / sizeof(int32_t), loopIndex,375+ loopIndex, vlSize / BIT_PER_BYTE / sizeof(int32_t));
376- vlSize / BIT_PER_BYTE / sizeof(int32_t));
377 // 搬入待比较mask的reg，每一bit表示一个有效值376 // 搬入待比较mask的reg，每一bit表示一个有效值
378- MicroAPI::DataCopy<int32_t, MicroAPI::MaskDist::DIST_NORM>(iouMask, maskUbAddr, offset);377+ Reg::DataCopy<int32_t, Reg::MaskDist::DIST_NORM>(iouMask, maskUbAddr, offset);
379- MicroAPI::DataCopy<uint8_t>(dstTensor, dstMaskAddr + loopIndex * vlSize);378+ Reg::DataCopy<uint8_t>(dstTensor, dstMaskAddr + loopIndex * vlSize);
380- MicroAPI::MaskAnd(removeMask, iouMask, refMask, pregAll);379+ Reg::MaskAnd(removeMask, iouMask, refMask, pregAll);
381- MicroAPI::MaskAnd(removeMask, removeMask, triuMask, pregAll);380+ Reg::MaskAnd(removeMask, removeMask, triuMask, pregAll);
382- MicroAPI::Select<uint8_t>(outTensor, vregZeros, dstTensor, removeMask);381+ Reg::Select<uint8_t>(outTensor, vregZeros, dstTensor, removeMask);
383- MicroAPI::DataCopy<uint8_t>(dstMaskAddr + loopIndex * vlSize, outTensor, preg);382+ Reg::DataCopy<uint8_t>(dstMaskAddr + loopIndex * vlSize, outTensor, preg);
384 }383 }
385 }384 }
386 }385 }
@@ -398,32 +397,31 @@ __aicore__ inline void NMSWithMaskRegbaseMultiProcess<T>::ComputeNMSForNormal(__
398 int32_t dstCountAligned = Ops::Base::CeilAlign(dstCount, alignNum_);397 int32_t dstCountAligned = Ops::Base::CeilAlign(dstCount, alignNum_);
399 __VEC_SCOPE__398 __VEC_SCOPE__
400 {399 {
401- MicroAPI::RegTensor<uint8_t> refTensor;400+ Reg::RegTensor<uint8_t> refTensor;
402- MicroAPI::RegTensor<uint8_t> dstTensor;401+ Reg::RegTensor<uint8_t> dstTensor;
403- MicroAPI::RegTensor<uint8_t> vregZeros;402+ Reg::RegTensor<uint8_t> vregZeros;
404- MicroAPI::RegTensor<uint8_t> outTensor;403+ Reg::RegTensor<uint8_t> outTensor;
405- MicroAPI::MaskReg preg;404+ Reg::MaskReg preg;
406- MicroAPI::MaskReg iouMask;405+ Reg::MaskReg iouMask;
407- MicroAPI::MaskReg removeMask;406+ Reg::MaskReg removeMask;
408- MicroAPI::MaskReg refMask;407+ Reg::MaskReg refMask;
409- MicroAPI::MaskReg pregAll = MicroAPI::CreateMask<uint8_t, MicroAPI::MaskPattern::ALL>();408+ Reg::MaskReg pregAll = Reg::CreateMask<uint8_t, Reg::MaskPattern::ALL>();
410- MicroAPI::Duplicate<uint8_t>(vregZeros, 0, pregAll);409+ Reg::Duplicate<uint8_t>(vregZeros, 0, pregAll);
411 for (uint16_t rowIdx = 0; rowIdx < rowNum; rowIdx++) {410 for (uint16_t rowIdx = 0; rowIdx < rowNum; rowIdx++) {
412 uint32_t rowEleNum = static_cast<uint32_t>(dstCount);411 uint32_t rowEleNum = static_cast<uint32_t>(dstCount);
413- MicroAPI::LocalMemBar<MicroAPI::MemType::VEC_STORE, MicroAPI::MemType::VEC_LOAD>();412+ Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_LOAD>();
414- MicroAPI::DataCopy<uint8_t, MicroAPI::LoadDist::DIST_BRC_B8>(refTensor, refMaskAddr + rowIdx);413+ Reg::DataCopy<uint8_t, Reg::LoadDist::DIST_BRC_B8>(refTensor, refMaskAddr + rowIdx);
415- MicroAPI::CompareScalar<uint8_t, CMPMODE::EQ>(refMask, refTensor, 1, pregAll);414+ Reg::CompareScalar<uint8_t, CMPMODE::EQ>(refMask, refTensor, 1, pregAll);
416 for (uint16_t loopIndex = 0; loopIndex < loopPerRow; loopIndex++) {415 for (uint16_t loopIndex = 0; loopIndex < loopPerRow; loopIndex++) {
417- preg = MicroAPI::UpdateMask<uint8_t>(rowEleNum);416+ preg = Reg::UpdateMask<uint8_t>(rowEleNum);
418- MicroAPI::AddrReg offset = MicroAPI::CreateAddrReg<int32_t>(417+ Reg::AddrReg offset = Reg::CreateAddrReg<int32_t>(rowIdx, groupSize_ / BIT_PER_BYTE / sizeof(int32_t),
419- rowIdx, groupSize_ / BIT_PER_BYTE / sizeof(int32_t), loopIndex,418+ loopIndex, vlSize / BIT_PER_BYTE / sizeof(int32_t));
420- vlSize / BIT_PER_BYTE / sizeof(int32_t));
421 // 搬入待比较mask的reg，每一bit表示一个有效值419 // 搬入待比较mask的reg，每一bit表示一个有效值
422- MicroAPI::DataCopy<int32_t, MicroAPI::MaskDist::DIST_NORM>(iouMask, maskUbAddr, offset);420+ Reg::DataCopy<int32_t, Reg::MaskDist::DIST_NORM>(iouMask, maskUbAddr, offset);
423- MicroAPI::DataCopy<uint8_t>(dstTensor, dstMaskAddr + loopIndex * vlSize);421+ Reg::DataCopy<uint8_t>(dstTensor, dstMaskAddr + loopIndex * vlSize);
424- MicroAPI::MaskAnd(removeMask, iouMask, refMask, pregAll);422+ Reg::MaskAnd(removeMask, iouMask, refMask, pregAll);
425- MicroAPI::Select<uint8_t>(outTensor, vregZeros, dstTensor, removeMask);423+ Reg::Select<uint8_t>(outTensor, vregZeros, dstTensor, removeMask);
426- MicroAPI::DataCopy<uint8_t>(dstMaskAddr + loopIndex * vlSize, outTensor, preg);424+ Reg::DataCopy<uint8_t>(dstMaskAddr + loopIndex * vlSize, outTensor, preg);
427 }425 }
428 }426 }
429 }427 }
@@ -439,52 +437,52 @@ __aicore__ inline void NMSWithMaskRegbaseMultiProcess<T>::ComputeRefArea(__ubuf_
439 uint32_t count = static_cast<uint32_t>(refCount);437 uint32_t count = static_cast<uint32_t>(refCount);
440 __VEC_SCOPE__438 __VEC_SCOPE__
441 {439 {
442- MicroAPI::RegTensor<float> x1;440+ Reg::RegTensor<float> x1;
443- MicroAPI::RegTensor<float> y1;441+ Reg::RegTensor<float> y1;
444- MicroAPI::RegTensor<float> x2;442+ Reg::RegTensor<float> x2;
445- MicroAPI::RegTensor<float> y2;443+ Reg::RegTensor<float> y2;
446- MicroAPI::RegTensor<float> width;444+ Reg::RegTensor<float> width;
447- MicroAPI::RegTensor<float> height;445+ Reg::RegTensor<float> height;
448- MicroAPI::RegTensor<float> area;446+ Reg::RegTensor<float> area;
449- MicroAPI::MaskReg preg;447+ Reg::MaskReg preg;
450 for (uint16_t loopIdx = 0; loopIdx < loopNum; loopIdx++) {448 for (uint16_t loopIdx = 0; loopIdx < loopNum; loopIdx++) {
451- preg = MicroAPI::UpdateMask<float>(count);449+ preg = Reg::UpdateMask<float>(count);
452 CopyInReg<T, false>(y1, refLocalAddr + loopIdx * vlSize, preg);450 CopyInReg<T, false>(y1, refLocalAddr + loopIdx * vlSize, preg);
453 CopyInReg<T, false>(x1, refLocalAddr + loopIdx * vlSize + INDEX_Y1 * refCountAligned, preg);451 CopyInReg<T, false>(x1, refLocalAddr + loopIdx * vlSize + INDEX_Y1 * refCountAligned, preg);
454 CopyInReg<T, false>(y2, refLocalAddr + loopIdx * vlSize + INDEX_X2 * refCountAligned, preg);452 CopyInReg<T, false>(y2, refLocalAddr + loopIdx * vlSize + INDEX_X2 * refCountAligned, preg);
455 CopyInReg<T, false>(x2, refLocalAddr + loopIdx * vlSize + INDEX_Y2 * refCountAligned, preg);453 CopyInReg<T, false>(x2, refLocalAddr + loopIdx * vlSize + INDEX_Y2 * refCountAligned, preg);
456- MicroAPI::Sub(width, x2, x1, preg);454+ Reg::Sub(width, x2, x1, preg);
457- MicroAPI::Sub(height, y2, y1, preg);455+ Reg::Sub(height, y2, y1, preg);
458- MicroAPI::Mul(area, width, height, preg);456+ Reg::Mul(area, width, height, preg);
459- MicroAPI::DataCopy<float, MicroAPI::PostLiteral::POST_MODE_UPDATE>(refAreaAddr, area, vlSize, preg);457+ Reg::DataCopy<float, Reg::PostLiteral::POST_MODE_UPDATE>(refAreaAddr, area, vlSize, preg);
460 }458 }
461 }459 }
462}460}
463 461 
464template <typename T>462template <typename T>
465__aicore__ inline void NMSWithMaskRegbaseMultiProcess<T>::CalcIntersection(463__aicore__ inline void NMSWithMaskRegbaseMultiProcess<T>::CalcIntersection(
466- MicroAPI::MaskReg& pregIou, MicroAPI::RegTensor<float>& sumArea, MicroAPI::RegTensor<float>& vregZeros,464+ Reg::MaskReg& pregIou, Reg::RegTensor<float>& sumArea, Reg::RegTensor<float>& vregZeros,
467- MicroAPI::RegTensor<float>& refX1, MicroAPI::RegTensor<float>& refY1, MicroAPI::RegTensor<float>& refX2,465+ Reg::RegTensor<float>& refX1, Reg::RegTensor<float>& refY1, Reg::RegTensor<float>& refX2,
468- MicroAPI::RegTensor<float>& refY2, MicroAPI::RegTensor<float>& dstX1, MicroAPI::RegTensor<float>& dstY1,466+ Reg::RegTensor<float>& refY2, Reg::RegTensor<float>& dstX1, Reg::RegTensor<float>& dstY1,
469- MicroAPI::RegTensor<float>& dstX2, MicroAPI::RegTensor<float>& dstY2, MicroAPI::MaskReg& preg)467+ Reg::RegTensor<float>& dstX2, Reg::RegTensor<float>& dstY2, Reg::MaskReg& preg)
470{468{
471- MicroAPI::RegTensor<float> minX2;469+ Reg::RegTensor<float> minX2;
472- MicroAPI::RegTensor<float> maxX1;470+ Reg::RegTensor<float> maxX1;
473- MicroAPI::RegTensor<float> minY2;471+ Reg::RegTensor<float> minY2;
474- MicroAPI::RegTensor<float> maxY1;472+ Reg::RegTensor<float> maxY1;
475- MicroAPI::RegTensor<float> intersection;473+ Reg::RegTensor<float> intersection;
476- MicroAPI::Min(minX2, refX2, dstX2, preg);474+ Reg::Min(minX2, refX2, dstX2, preg);
477- MicroAPI::Max(maxX1, refX1, dstX1, preg);475+ Reg::Max(maxX1, refX1, dstX1, preg);
478- MicroAPI::Min(minY2, refY2, dstY2, preg);476+ Reg::Min(minY2, refY2, dstY2, preg);
479- MicroAPI::Max(maxY1, refY1, dstY1, preg);477+ Reg::Max(maxY1, refY1, dstY1, preg);
480- MicroAPI::Sub(minX2, minX2, maxX1, preg);478+ Reg::Sub(minX2, minX2, maxX1, preg);
481- MicroAPI::Sub(minY2, minY2, maxY1, preg);479+ Reg::Sub(minY2, minY2, maxY1, preg);
482- MicroAPI::Max(minX2, minX2, vregZeros, preg);480+ Reg::Max(minX2, minX2, vregZeros, preg);
483- MicroAPI::Max(minY2, minY2, vregZeros, preg);481+ Reg::Max(minY2, minY2, vregZeros, preg);
484- MicroAPI::Mul(intersection, minX2, minY2, preg);482+ Reg::Mul(intersection, minX2, minY2, preg);
485- MicroAPI::Sub(sumArea, sumArea, intersection, preg); // 视sumArea为并集大小483+ Reg::Sub(sumArea, sumArea, intersection, preg); // 视sumArea为并集大小
486- MicroAPI::Muls(sumArea, sumArea, iouThreshold_, preg);484+ Reg::Muls(sumArea, sumArea, iouThreshold_, preg);
487- MicroAPI::Compare<float, CMPMODE::GT>(pregIou, intersection, sumArea, preg);485+ Reg::Compare<float, CMPMODE::GT>(pregIou, intersection, sumArea, preg);
488}486}
489 487 
490template <typename T>488template <typename T>
@@ -506,36 +504,36 @@ __aicore__ inline void NMSWithMaskRegbaseMultiProcess<T>::ComputeMaskVf(__ubuf__
506 uint32_t srcStride = groupSize_ / BIT_PER_BYTE / sizeof(int32_t);504 uint32_t srcStride = groupSize_ / BIT_PER_BYTE / sizeof(int32_t);
507 __VEC_SCOPE__505 __VEC_SCOPE__
508 {506 {
509- MicroAPI::RegTensor<float> refX1;507+ Reg::RegTensor<float> refX1;
510- MicroAPI::RegTensor<float> refY1;508+ Reg::RegTensor<float> refY1;
511- MicroAPI::RegTensor<float> refX2;509+ Reg::RegTensor<float> refX2;
512- MicroAPI::RegTensor<float> refY2;510+ Reg::RegTensor<float> refY2;
513- MicroAPI::RegTensor<float> dstX1;511+ Reg::RegTensor<float> dstX1;
514- MicroAPI::RegTensor<float> dstY1;512+ Reg::RegTensor<float> dstY1;
515- MicroAPI::RegTensor<float> dstX2;513+ Reg::RegTensor<float> dstX2;
516- MicroAPI::RegTensor<float> dstY2;514+ Reg::RegTensor<float> dstY2;
517- MicroAPI::RegTensor<float> dstX3;515+ Reg::RegTensor<float> dstX3;
518- MicroAPI::RegTensor<float> dstY3;516+ Reg::RegTensor<float> dstY3;
519- MicroAPI::RegTensor<float> dstX4;517+ Reg::RegTensor<float> dstX4;
520- MicroAPI::RegTensor<float> dstY4;518+ Reg::RegTensor<float> dstY4;
521- MicroAPI::RegTensor<float> refArea;519+ Reg::RegTensor<float> refArea;
522- MicroAPI::RegTensor<float> dstHeight;520+ Reg::RegTensor<float> dstHeight;
523- MicroAPI::RegTensor<float> dstWidth;521+ Reg::RegTensor<float> dstWidth;
524- MicroAPI::RegTensor<float> dstArea0;522+ Reg::RegTensor<float> dstArea0;
525- MicroAPI::RegTensor<float> dstArea1;523+ Reg::RegTensor<float> dstArea1;
526- MicroAPI::RegTensor<float> sumArea;524+ Reg::RegTensor<float> sumArea;
527- MicroAPI::RegTensor<float> vregZeros;525+ Reg::RegTensor<float> vregZeros;
528- MicroAPI::MaskReg preg0;526+ Reg::MaskReg preg0;
529- MicroAPI::MaskReg preg1;527+ Reg::MaskReg preg1;
530- MicroAPI::MaskReg pregIou0;528+ Reg::MaskReg pregIou0;
531- MicroAPI::MaskReg pregIou1;529+ Reg::MaskReg pregIou1;
532- MicroAPI::MaskReg pregRes0;530+ Reg::MaskReg pregRes0;
533- MicroAPI::MaskReg pregRes1;531+ Reg::MaskReg pregRes1;
534- MicroAPI::MaskReg pregAll = MicroAPI::CreateMask<float, MicroAPI::MaskPattern::ALL>();532+ Reg::MaskReg pregAll = Reg::CreateMask<float, Reg::MaskPattern::ALL>();
535- MicroAPI::Duplicate<float>(vregZeros, 0.0f, pregAll);533+ Reg::Duplicate<float>(vregZeros, 0.0f, pregAll);
536 for (uint16_t dstBlockIdx = 0; dstBlockIdx < rowLoopNum; dstBlockIdx++) {534 for (uint16_t dstBlockIdx = 0; dstBlockIdx < rowLoopNum; dstBlockIdx++) {
537- preg0 = MicroAPI::UpdateMask<float>(dstCountU32);535+ preg0 = Reg::UpdateMask<float>(dstCountU32);
538- preg1 = MicroAPI::UpdateMask<float>(dstCountU32);536+ preg1 = Reg::UpdateMask<float>(dstCountU32);
539 CopyInReg<T, false>(dstY1, dstLocalAddr + dstBlockIdx * vlSize * 2, preg0);537 CopyInReg<T, false>(dstY1, dstLocalAddr + dstBlockIdx * vlSize * 2, preg0);
540 CopyInReg<T, false>(dstX1, dstLocalAddr + dstBlockIdx * vlSize * 2 + INDEX_Y1 * dstCountAligned, preg0);538 CopyInReg<T, false>(dstX1, dstLocalAddr + dstBlockIdx * vlSize * 2 + INDEX_Y1 * dstCountAligned, preg0);
541 CopyInReg<T, false>(dstY2, dstLocalAddr + dstBlockIdx * vlSize * 2 + INDEX_X2 * dstCountAligned, preg0);539 CopyInReg<T, false>(dstY2, dstLocalAddr + dstBlockIdx * vlSize * 2 + INDEX_X2 * dstCountAligned, preg0);
@@ -547,56 +545,56 @@ __aicore__ inline void NMSWithMaskRegbaseMultiProcess<T>::ComputeMaskVf(__ubuf__
547 preg1);545 preg1);
548 CopyInReg<T, false>(dstX4, dstLocalAddr + dstBlockIdx * vlSize * 2 + vlSize + INDEX_Y2 * dstCountAligned,546 CopyInReg<T, false>(dstX4, dstLocalAddr + dstBlockIdx * vlSize * 2 + vlSize + INDEX_Y2 * dstCountAligned,
549 preg1);547 preg1);
550- MicroAPI::Sub(dstWidth, dstX2, dstX1, preg0);548+ Reg::Sub(dstWidth, dstX2, dstX1, preg0);
551- MicroAPI::Sub(dstHeight, dstY2, dstY1, preg0);549+ Reg::Sub(dstHeight, dstY2, dstY1, preg0);
552- MicroAPI::Mul(dstArea0, dstWidth, dstHeight, preg0);550+ Reg::Mul(dstArea0, dstWidth, dstHeight, preg0);
553- MicroAPI::Sub(dstWidth, dstX4, dstX3, preg1);551+ Reg::Sub(dstWidth, dstX4, dstX3, preg1);
554- MicroAPI::Sub(dstHeight, dstY4, dstY3, preg1);552+ Reg::Sub(dstHeight, dstY4, dstY3, preg1);
555- MicroAPI::Mul(dstArea1, dstWidth, dstHeight, preg1);553+ Reg::Mul(dstArea1, dstWidth, dstHeight, preg1);
556 for (uint16_t refIdx = 0; refIdx < rowNum; refIdx++) {554 for (uint16_t refIdx = 0; refIdx < rowNum; refIdx++) {
557 // 要满足16 byte搬出，最终mask存为int32类型；pre过程计算的中间mask大小为groupSize_ *555 // 要满足16 byte搬出，最终mask存为int32类型；pre过程计算的中间mask大小为groupSize_ *
558 // groupSize_，每行对应groupSize_个bit，因此源操作数的偏移量是groupSize_ / BIT_PER_BYTE /556 // groupSize_，每行对应groupSize_个bit，因此源操作数的偏移量是groupSize_ / BIT_PER_BYTE /
559 // sizeof(int32_t)557 // sizeof(int32_t)
560- MicroAPI::AddrReg offsetReg = MicroAPI::CreateAddrReg<int32_t>(dstBlockIdx, dstStride, refIdx,558+ Reg::AddrReg offsetReg = Reg::CreateAddrReg<int32_t>(dstBlockIdx, dstStride, refIdx,
561- srcStride); // 4：16 / sizeof(int32)559+ srcStride); // 4：16 / sizeof(int32)
562 CopyInReg<T, true>(refY1, refLocalAddr + refIdx, pregAll);560 CopyInReg<T, true>(refY1, refLocalAddr + refIdx, pregAll);
563 CopyInReg<T, true>(refX1, refLocalAddr + refIdx + INDEX_Y1 * refCountAligned, pregAll);561 CopyInReg<T, true>(refX1, refLocalAddr + refIdx + INDEX_Y1 * refCountAligned, pregAll);
564 CopyInReg<T, true>(refY2, refLocalAddr + refIdx + INDEX_X2 * refCountAligned, pregAll);562 CopyInReg<T, true>(refY2, refLocalAddr + refIdx + INDEX_X2 * refCountAligned, pregAll);
565 CopyInReg<T, true>(refX2, refLocalAddr + refIdx + INDEX_Y2 * refCountAligned, pregAll);563 CopyInReg<T, true>(refX2, refLocalAddr + refIdx + INDEX_Y2 * refCountAligned, pregAll);
566 CopyInReg<float, true>(refArea, refAreaAddr + refIdx, pregAll);564 CopyInReg<float, true>(refArea, refAreaAddr + refIdx, pregAll);
567- MicroAPI::Add(sumArea, dstArea0, refArea, preg0);565+ Reg::Add(sumArea, dstArea0, refArea, preg0);
568 CalcIntersection(pregIou0, sumArea, vregZeros, refX1, refY1, refX2, refY2, dstX1, dstY1, dstX2, dstY2,566 CalcIntersection(pregIou0, sumArea, vregZeros, refX1, refY1, refX2, refY2, dstX1, dstY1, dstX2, dstY2,
569 preg0);567 preg0);
570- MicroAPI::Add(sumArea, dstArea1, refArea, preg1);568+ Reg::Add(sumArea, dstArea1, refArea, preg1);
571 CalcIntersection(pregIou1, sumArea, vregZeros, refX1, refY1, refX2, refY2, dstX3, dstY3, dstX4, dstY4,569 CalcIntersection(pregIou1, sumArea, vregZeros, refX1, refY1, refX2, refY2, dstX3, dstY3, dstX4, dstY4,
572 preg1);570 preg1);
573 // interleave from b32 maskreg to b16 maskreg571 // interleave from b32 maskreg to b16 maskreg
574- MicroAPI::MaskDeInterleave<half>(pregRes0, pregRes1, pregIou0, pregIou1); // 16B对齐572+ Reg::MaskDeInterleave<half>(pregRes0, pregRes1, pregIou0, pregIou1); // 16B对齐
575 // maskUbAddr + offset573 // maskUbAddr + offset
576- MicroAPI::DataCopy<int32_t, MicroAPI::MaskDist::DIST_PACK>(maskUbAddr, pregRes0, offsetReg);574+ Reg::DataCopy<int32_t, Reg::MaskDist::DIST_PACK>(maskUbAddr, pregRes0, offsetReg);
577 }575 }
578 }576 }
579 if constexpr (dstIsOddBlock) {577 if constexpr (dstIsOddBlock) {
580- preg0 = MicroAPI::UpdateMask<float>(dstCountU32);578+ preg0 = Reg::UpdateMask<float>(dstCountU32);
581 CopyInReg<T, false>(dstY1, dstLocalAddr + rowLoopNum * vlSize * 2, preg0);579 CopyInReg<T, false>(dstY1, dstLocalAddr + rowLoopNum * vlSize * 2, preg0);
582 CopyInReg<T, false>(dstX1, dstLocalAddr + rowLoopNum * vlSize * 2 + INDEX_Y1 * dstCountAligned, preg0);580 CopyInReg<T, false>(dstX1, dstLocalAddr + rowLoopNum * vlSize * 2 + INDEX_Y1 * dstCountAligned, preg0);
583 CopyInReg<T, false>(dstY2, dstLocalAddr + rowLoopNum * vlSize * 2 + INDEX_X2 * dstCountAligned, preg0);581 CopyInReg<T, false>(dstY2, dstLocalAddr + rowLoopNum * vlSize * 2 + INDEX_X2 * dstCountAligned, preg0);
584 CopyInReg<T, false>(dstX2, dstLocalAddr + rowLoopNum * vlSize * 2 + INDEX_Y2 * dstCountAligned, preg0);582 CopyInReg<T, false>(dstX2, dstLocalAddr + rowLoopNum * vlSize * 2 + INDEX_Y2 * dstCountAligned, preg0);
585- MicroAPI::Sub(dstWidth, dstX2, dstX1, preg0);583+ Reg::Sub(dstWidth, dstX2, dstX1, preg0);
586- MicroAPI::Sub(dstHeight, dstY2, dstY1, preg0);584+ Reg::Sub(dstHeight, dstY2, dstY1, preg0);
587- MicroAPI::Mul(dstArea0, dstWidth, dstHeight, preg0);585+ Reg::Mul(dstArea0, dstWidth, dstHeight, preg0);
588 for (uint16_t refIdx = 0; refIdx < rowNum; refIdx++) {586 for (uint16_t refIdx = 0; refIdx < rowNum; refIdx++) {
589 CopyInReg<T, true>(refY1, refLocalAddr + refIdx, pregAll);587 CopyInReg<T, true>(refY1, refLocalAddr + refIdx, pregAll);
590 CopyInReg<T, true>(refX1, refLocalAddr + refIdx + INDEX_Y1 * refCountAligned, pregAll);588 CopyInReg<T, true>(refX1, refLocalAddr + refIdx + INDEX_Y1 * refCountAligned, pregAll);
591 CopyInReg<T, true>(refY2, refLocalAddr + refIdx + INDEX_X2 * refCountAligned, pregAll);589 CopyInReg<T, true>(refY2, refLocalAddr + refIdx + INDEX_X2 * refCountAligned, pregAll);
592 CopyInReg<T, true>(refX2, refLocalAddr + refIdx + INDEX_Y2 * refCountAligned, pregAll);590 CopyInReg<T, true>(refX2, refLocalAddr + refIdx + INDEX_Y2 * refCountAligned, pregAll);
593 CopyInReg<float, true>(refArea, refAreaAddr + refIdx, pregAll);591 CopyInReg<float, true>(refArea, refAreaAddr + refIdx, pregAll);
594- MicroAPI::Add(sumArea, dstArea0, refArea, preg0);592+ Reg::Add(sumArea, dstArea0, refArea, preg0);
595 CalcIntersection(pregIou0, sumArea, vregZeros, refX1, refY1, refX2, refY2, dstX1, dstY1, dstX2, dstY2,593 CalcIntersection(pregIou0, sumArea, vregZeros, refX1, refY1, refX2, refY2, dstX1, dstY1, dstX2, dstY2,
596 preg0);594 preg0);
597 // interleave from b32 maskreg to b16 maskreg595 // interleave from b32 maskreg to b16 maskreg
598- MicroAPI::MaskDeInterleave<half>(pregRes0, pregRes1, pregIou0, pregIou0);596+ Reg::MaskDeInterleave<half>(pregRes0, pregRes1, pregIou0, pregIou0);
599- MicroAPI::DataCopy<int32_t, MicroAPI::MaskDist::DIST_PACK>(597+ Reg::DataCopy<int32_t, Reg::MaskDist::DIST_PACK>(
600 maskUbAddr + rowLoopNum * dstStride + refIdx * srcStride, pregRes0);598 maskUbAddr + rowLoopNum * dstStride + refIdx * srcStride, pregRes0);
601 }599 }
602 }600 }
@@ -604,4 +602,4 @@ __aicore__ inline void NMSWithMaskRegbaseMultiProcess<T>::ComputeMaskVf(__ubuf__
604}602}
605} // namespace NMSWithMaskOp603} // namespace NMSWithMaskOp
606 604 
607-#endif // NMS_WITH_MASK_REGBASE_MULTIPROCESS_H_605+#endif // NMS_WITH_MASK_REGBASE_MULTIPROCESS_H_
Mimage/resize_bilinear_v2/op_kernel/arch35/resize_bilinear_v2_broadcast_nchw.h+5-6
@@ -164,18 +164,17 @@ __aicore__ inline void ResizeBilinearV2BroadcastNCHW<T_DATA>::Compute(LocalTenso
164 164 
165 __VEC_SCOPE__165 __VEC_SCOPE__
166 {166 {
167- MicroAPI::MaskReg preg;167+ Reg::MaskReg preg;
168- MicroAPI::RegTensor<U> regData;168+ Reg::RegTensor<U> regData;
169 169 
170 for (uint16_t ncLoop = 0; ncLoop < (uint16_t)lenNC; ncLoop++) {170 for (uint16_t ncLoop = 0; ncLoop < (uint16_t)lenNC; ncLoop++) {
171 U val = *xAddr;171 U val = *xAddr;
172 __ubuf__ U* yLineAddr = yAddr;172 __ubuf__ U* yLineAddr = yAddr;
173 uint32_t oneLineLen = lineLen;173 uint32_t oneLineLen = lineLen;
174 for (uint16_t inLoop = 0; inLoop < (uint16_t)repeatTimes; inLoop++) {174 for (uint16_t inLoop = 0; inLoop < (uint16_t)repeatTimes; inLoop++) {
175- preg = MicroAPI::UpdateMask<U>(oneLineLen);175+ preg = Reg::UpdateMask<U>(oneLineLen);
176- MicroAPI::Duplicate(regData, val, preg);176+ Reg::Duplicate(regData, val, preg);
177- MicroAPI::DataCopy<U, MicroAPI::PostLiteral::POST_MODE_UPDATE>(yLineAddr, regData, (int32_t)oneRepeat,177+ Reg::DataCopy<U, Reg::PostLiteral::POST_MODE_UPDATE>(yLineAddr, regData, (int32_t)oneRepeat, preg);
178- preg);
179 }178 }
180 179 
181 xAddr++;180 xAddr++;
Mimage/resize_bilinear_v2/op_kernel/arch35/resize_bilinear_v2_c_parallel.h+49-53
@@ -21,7 +21,7 @@
21 21 
22namespace ResizeBilinearV2 {22namespace ResizeBilinearV2 {
23using namespace AscendC;23using namespace AscendC;
24-using AscendC::MicroAPI::RegTensor;24+using AscendC::Reg::RegTensor;
25 25 
26constexpr int32_t POS_NW = 0;26constexpr int32_t POS_NW = 0;
27constexpr int32_t POS_NE = 1;27constexpr int32_t POS_NE = 1;
@@ -55,13 +55,11 @@ protected:
55 55 
56 DataCopyPadExtParams<uint8_t> padParams_ = {false, 0, 0, 0};56 DataCopyPadExtParams<uint8_t> padParams_ = {false, 0, 0, 0};
57 57 
58- constexpr static MicroAPI::CastTrait castTrait0 = {MicroAPI::RegLayout::ZERO, MicroAPI::SatMode::UNKNOWN,58+ constexpr static Reg::CastTrait castTrait0 = {Reg::RegLayout::ZERO, Reg::SatMode::UNKNOWN,
59- MicroAPI::MaskMergeMode::ZEROING,59+ Reg::MaskMergeMode::ZEROING, RoundMode::UNKNOWN}; // bf16 --float
60- RoundMode::UNKNOWN}; // bf16 --float
61 60 
62- constexpr static MicroAPI::CastTrait castTrait1 = {MicroAPI::RegLayout::ZERO, MicroAPI::SatMode::NO_SAT,61+ constexpr static Reg::CastTrait castTrait1 = {Reg::RegLayout::ZERO, Reg::SatMode::NO_SAT,
63- MicroAPI::MaskMergeMode::ZEROING,62+ Reg::MaskMergeMode::ZEROING, RoundMode::CAST_RINT}; // float---bf16
64- RoundMode::CAST_RINT}; // float---bf16
65 63 
66 int64_t nStrideX_;64 int64_t nStrideX_;
67 int64_t hwStrideX_;65 int64_t hwStrideX_;
@@ -199,63 +197,61 @@ __aicore__ inline void ResizeBilinearV2CParallel<T_X, T_Y>::Compute()
199 197 
200 __VEC_SCOPE__198 __VEC_SCOPE__
201 {199 {
202- MicroAPI::MaskReg pregFp32;200+ Reg::MaskReg pregFp32;
203- MicroAPI::MaskReg pregFp16;201+ Reg::MaskReg pregFp16;
204- MicroAPI::RegTensor<T_X> regNW;202+ Reg::RegTensor<T_X> regNW;
205- MicroAPI::RegTensor<T_X> regNE;203+ Reg::RegTensor<T_X> regNE;
206- MicroAPI::RegTensor<T_X> regSW;204+ Reg::RegTensor<T_X> regSW;
207- MicroAPI::RegTensor<T_X> regSE;205+ Reg::RegTensor<T_X> regSE;
208- MicroAPI::RegTensor<T_X> regTmp;206+ Reg::RegTensor<T_X> regTmp;
209- MicroAPI::RegTensor<float> regNWFp32;207+ Reg::RegTensor<float> regNWFp32;
210- MicroAPI::RegTensor<float> regNEFp32;208+ Reg::RegTensor<float> regNEFp32;
211- MicroAPI::RegTensor<float> regSWFp32;209+ Reg::RegTensor<float> regSWFp32;
212- MicroAPI::RegTensor<float> regSEFp32;210+ Reg::RegTensor<float> regSEFp32;
213- MicroAPI::RegTensor<float> regSumTopFp32;211+ Reg::RegTensor<float> regSumTopFp32;
214- MicroAPI::RegTensor<float> regSumBotFp32;212+ Reg::RegTensor<float> regSumBotFp32;
215- MicroAPI::RegTensor<float> regSumFp32;213+ Reg::RegTensor<float> regSumFp32;
216- MicroAPI::RegTensor<T_Y> regRst;214+ Reg::RegTensor<T_Y> regRst;
217 215 
218 for (uint16_t loop = 0; loop < (uint16_t)repeatTimes; loop++) {216 for (uint16_t loop = 0; loop < (uint16_t)repeatTimes; loop++) {
219- pregFp32 = MicroAPI::UpdateMask<float>(totalLen);217+ pregFp32 = Reg::UpdateMask<float>(totalLen);
220- MicroAPI::DataCopy<T_X, MicroAPI::PostLiteral::POST_MODE_UPDATE>(regNW, xAddrNW, (int32_t)oneRepeat);218+ Reg::DataCopy<T_X, Reg::PostLiteral::POST_MODE_UPDATE>(regNW, xAddrNW, (int32_t)oneRepeat);
221- MicroAPI::DataCopy<T_X, MicroAPI::PostLiteral::POST_MODE_UPDATE>(regNE, xAddrNE, (int32_t)oneRepeat);219+ Reg::DataCopy<T_X, Reg::PostLiteral::POST_MODE_UPDATE>(regNE, xAddrNE, (int32_t)oneRepeat);
222- MicroAPI::DataCopy<T_X, MicroAPI::PostLiteral::POST_MODE_UPDATE>(regSW, xAddrSW, (int32_t)oneRepeat);220+ Reg::DataCopy<T_X, Reg::PostLiteral::POST_MODE_UPDATE>(regSW, xAddrSW, (int32_t)oneRepeat);
223- MicroAPI::DataCopy<T_X, MicroAPI::PostLiteral::POST_MODE_UPDATE>(regSE, xAddrSE, (int32_t)oneRepeat);221+ Reg::DataCopy<T_X, Reg::PostLiteral::POST_MODE_UPDATE>(regSE, xAddrSE, (int32_t)oneRepeat);
224 222 
225 if constexpr (sizeof(T_X) == sizeof(int16_t)) {223 if constexpr (sizeof(T_X) == sizeof(int16_t)) {
226- MicroAPI::UnPack((RegTensor<int32_t>&)regTmp, (RegTensor<int16_t>&)regNW);224+ Reg::UnPack((RegTensor<int32_t>&)regTmp, (RegTensor<int16_t>&)regNW);
227- MicroAPI::Cast<float, T_X, castTrait0>(regNWFp32, regTmp, pregFp32);225+ Reg::Cast<float, T_X, castTrait0>(regNWFp32, regTmp, pregFp32);
228- MicroAPI::UnPack((RegTensor<int32_t>&)regTmp, (RegTensor<int16_t>&)regNE);226+ Reg::UnPack((RegTensor<int32_t>&)regTmp, (RegTensor<int16_t>&)regNE);
229- MicroAPI::Cast<float, T_X, castTrait0>(regNEFp32, regTmp, pregFp32);227+ Reg::Cast<float, T_X, castTrait0>(regNEFp32, regTmp, pregFp32);
230- MicroAPI::UnPack((RegTensor<int32_t>&)regTmp, (RegTensor<int16_t>&)regSW);228+ Reg::UnPack((RegTensor<int32_t>&)regTmp, (RegTensor<int16_t>&)regSW);
231- MicroAPI::Cast<float, T_X, castTrait0>(regSWFp32, regTmp, pregFp32);229+ Reg::Cast<float, T_X, castTrait0>(regSWFp32, regTmp, pregFp32);
232- MicroAPI::UnPack((RegTensor<int32_t>&)regTmp, (RegTensor<int16_t>&)regSE);230+ Reg::UnPack((RegTensor<int32_t>&)regTmp, (RegTensor<int16_t>&)regSE);
233- MicroAPI::Cast<float, T_X, castTrait0>(regSEFp32, regTmp, pregFp32);231+ Reg::Cast<float, T_X, castTrait0>(regSEFp32, regTmp, pregFp32);
234 232 
235- MicroAPI::Muls(regNWFp32, regNWFp32, weightNW, pregFp32);233+ Reg::Muls(regNWFp32, regNWFp32, weightNW, pregFp32);
236- MicroAPI::Muls(regNEFp32, regNEFp32, weightNE, pregFp32);234+ Reg::Muls(regNEFp32, regNEFp32, weightNE, pregFp32);
237- MicroAPI::Muls(regSWFp32, regSWFp32, weightSW, pregFp32);235+ Reg::Muls(regSWFp32, regSWFp32, weightSW, pregFp32);
238- MicroAPI::Muls(regSEFp32, regSEFp32, weightSE, pregFp32);236+ Reg::Muls(regSEFp32, regSEFp32, weightSE, pregFp32);
239 } else {237 } else {
240- MicroAPI::Muls(regNWFp32, regNW, weightNW, pregFp32);238+ Reg::Muls(regNWFp32, regNW, weightNW, pregFp32);
241- MicroAPI::Muls(regNEFp32, regNE, weightNE, pregFp32);239+ Reg::Muls(regNEFp32, regNE, weightNE, pregFp32);
242- MicroAPI::Muls(regSWFp32, regSW, weightSW, pregFp32);240+ Reg::Muls(regSWFp32, regSW, weightSW, pregFp32);
243- MicroAPI::Muls(regSEFp32, regSE, weightSE, pregFp32);241+ Reg::Muls(regSEFp32, regSE, weightSE, pregFp32);
244 }242 }
245 243 
246- MicroAPI::Add(regSumTopFp32, regNWFp32, regNEFp32, pregFp32);244+ Reg::Add(regSumTopFp32, regNWFp32, regNEFp32, pregFp32);
247- MicroAPI::Add(regSumBotFp32, regSWFp32, regSEFp32, pregFp32);245+ Reg::Add(regSumBotFp32, regSWFp32, regSEFp32, pregFp32);
248- MicroAPI::Add(regSumFp32, regSumTopFp32, regSumBotFp32, pregFp32);246+ Reg::Add(regSumFp32, regSumTopFp32, regSumBotFp32, pregFp32);
249 247 
250 if constexpr (sizeof(T_Y) == sizeof(int16_t)) {248 if constexpr (sizeof(T_Y) == sizeof(int16_t)) {
251- MicroAPI::Cast<T_Y, float, castTrait1>(regTmp, regSumFp32, pregFp32);249+ Reg::Cast<T_Y, float, castTrait1>(regTmp, regSumFp32, pregFp32);
252- MicroAPI::Pack((RegTensor<uint16_t>&)regRst, (RegTensor<uint32_t>&)regTmp);250+ Reg::Pack((RegTensor<uint16_t>&)regRst, (RegTensor<uint32_t>&)regTmp);
253- MicroAPI::MaskPack(pregFp16, pregFp32);251+ Reg::MaskPack(pregFp16, pregFp32);
254- MicroAPI::DataCopy<T_Y, MicroAPI::PostLiteral::POST_MODE_UPDATE>(yAddr, regRst, (int32_t)oneRepeat,252+ Reg::DataCopy<T_Y, Reg::PostLiteral::POST_MODE_UPDATE>(yAddr, regRst, (int32_t)oneRepeat, pregFp16);
255- pregFp16);
256 } else {253 } else {
257- MicroAPI::DataCopy<T_Y, MicroAPI::PostLiteral::POST_MODE_UPDATE>(yAddr, regSumFp32, (int32_t)oneRepeat,254+ Reg::DataCopy<T_Y, Reg::PostLiteral::POST_MODE_UPDATE>(yAddr, regSumFp32, (int32_t)oneRepeat, pregFp32);
258- pregFp32);
259 }255 }
260 }256 }
261 }257 }
Mimage/resize_bilinear_v2/op_kernel/arch35/resize_bilinear_v2_nc.h+60-62
@@ -20,7 +20,7 @@
20 20 
21namespace ResizeBilinearV2 {21namespace ResizeBilinearV2 {
22using namespace AscendC;22using namespace AscendC;
23-using AscendC::MicroAPI::RegTensor;23+using AscendC::Reg::RegTensor;
24constexpr int32_t BUFF_NUM = 2;24constexpr int32_t BUFF_NUM = 2;
25constexpr int32_t POS_LU = 0;25constexpr int32_t POS_LU = 0;
26constexpr int32_t POS_RU = 1;26constexpr int32_t POS_RU = 1;
@@ -98,13 +98,13 @@ private:
98 int64_t lenDstHw_ = 0;98 int64_t lenDstHw_ = 0;
99 float delta_[POS_TOTAL];99 float delta_[POS_TOTAL];
100 uint32_t oneRepeat_ = Ops::Base::GetVRegSize() / sizeof(float);100 uint32_t oneRepeat_ = Ops::Base::GetVRegSize() / sizeof(float);
101- constexpr static AscendC::MicroAPI::CastTrait castTrait0 = {101+ constexpr static AscendC::Reg::CastTrait castTrait0 = {
102- AscendC::MicroAPI::RegLayout::ZERO, AscendC::MicroAPI::SatMode::UNKNOWN,102+ AscendC::Reg::RegLayout::ZERO, AscendC::Reg::SatMode::UNKNOWN, AscendC::Reg::MaskMergeMode::ZEROING,
103- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::UNKNOWN}; // bf16 --float103+ AscendC::RoundMode::UNKNOWN}; // bf16 --float
104 104 
105- constexpr static AscendC::MicroAPI::CastTrait castTrait1 = {105+ constexpr static AscendC::Reg::CastTrait castTrait1 = {AscendC::Reg::RegLayout::ZERO, AscendC::Reg::SatMode::NO_SAT,
106- AscendC::MicroAPI::RegLayout::ZERO, AscendC::MicroAPI::SatMode::NO_SAT,106+ AscendC::Reg::MaskMergeMode::ZEROING,
107- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_RINT}; // float---bf16107+ AscendC::RoundMode::CAST_RINT}; // float---bf16
108};108};
109 109 
110template <typename Tin, typename Tout>110template <typename Tin, typename Tout>
@@ -208,68 +208,66 @@ __aicore__ inline void ResizeBilinearV2Nc<Tin, Tout>::ComputeDstValueWith4SrcDot
208 float delta_rd = delta_[POS_RD];208 float delta_rd = delta_[POS_RD];
209 __VEC_SCOPE__209 __VEC_SCOPE__
210 {210 {
211- MicroAPI::MaskReg pregFp16;211+ Reg::MaskReg pregFp16;
212- MicroAPI::MaskReg pregFp32;212+ Reg::MaskReg pregFp32;
213- MicroAPI::RegTensor<Tin> reg_srcLu;213+ Reg::RegTensor<Tin> reg_srcLu;
214- MicroAPI::RegTensor<Tin> reg_srcRu;214+ Reg::RegTensor<Tin> reg_srcRu;
215- MicroAPI::RegTensor<Tin> reg_srcLd;215+ Reg::RegTensor<Tin> reg_srcLd;
216- MicroAPI::RegTensor<Tin> reg_srcRd;216+ Reg::RegTensor<Tin> reg_srcRd;
217- MicroAPI::RegTensor<Tin> reg_srcLui32;217+ Reg::RegTensor<Tin> reg_srcLui32;
218- MicroAPI::RegTensor<Tin> reg_srcRui32;218+ Reg::RegTensor<Tin> reg_srcRui32;
219- MicroAPI::RegTensor<Tin> reg_srcLdi32;219+ Reg::RegTensor<Tin> reg_srcLdi32;
220- MicroAPI::RegTensor<Tin> reg_srcRdi32;220+ Reg::RegTensor<Tin> reg_srcRdi32;
221- MicroAPI::RegTensor<Tout> regOutputT2;221+ Reg::RegTensor<Tout> regOutputT2;
222- MicroAPI::RegTensor<Tout> regTmpT2;222+ Reg::RegTensor<Tout> regTmpT2;
223- MicroAPI::RegTensor<float> regSrcLuf32;223+ Reg::RegTensor<float> regSrcLuf32;
224- MicroAPI::RegTensor<float> regSrcRuf32;224+ Reg::RegTensor<float> regSrcRuf32;
225- MicroAPI::RegTensor<float> regSrcLdf32;225+ Reg::RegTensor<float> regSrcLdf32;
226- MicroAPI::RegTensor<float> regSrcRdf32;226+ Reg::RegTensor<float> regSrcRdf32;
227- MicroAPI::RegTensor<float> regDeltaLu;227+ Reg::RegTensor<float> regDeltaLu;
228- MicroAPI::RegTensor<float> regDeltaRu;228+ Reg::RegTensor<float> regDeltaRu;
229- MicroAPI::RegTensor<float> regDeltaLd;229+ Reg::RegTensor<float> regDeltaLd;
230- MicroAPI::RegTensor<float> regDeltaRd;230+ Reg::RegTensor<float> regDeltaRd;
231- MicroAPI::RegTensor<float> regSumUpperF32;231+ Reg::RegTensor<float> regSumUpperF32;
232- MicroAPI::RegTensor<float> regSumDownF32;232+ Reg::RegTensor<float> regSumDownF32;
233- MicroAPI::RegTensor<float> regSumF32;233+ Reg::RegTensor<float> regSumF32;
234 234 
235 for (uint16_t idx = 0; idx < repeatTimes; idx++) {235 for (uint16_t idx = 0; idx < repeatTimes; idx++) {
236- pregFp32 = AscendC::MicroAPI::UpdateMask<float>(totalLen);236+ pregFp32 = AscendC::Reg::UpdateMask<float>(totalLen);
237- MicroAPI::DataCopy<Tin, MicroAPI::PostLiteral::POST_MODE_UPDATE>(reg_srcLu, srcUbLuPrt, oneRepeat_);237+ Reg::DataCopy<Tin, Reg::PostLiteral::POST_MODE_UPDATE>(reg_srcLu, srcUbLuPrt, oneRepeat_);
238- MicroAPI::DataCopy<Tin, MicroAPI::PostLiteral::POST_MODE_UPDATE>(reg_srcRu, srcUbRuPrt, oneRepeat_);238+ Reg::DataCopy<Tin, Reg::PostLiteral::POST_MODE_UPDATE>(reg_srcRu, srcUbRuPrt, oneRepeat_);
239- MicroAPI::DataCopy<Tin, MicroAPI::PostLiteral::POST_MODE_UPDATE>(reg_srcLd, srcUbLdPrt, oneRepeat_);239+ Reg::DataCopy<Tin, Reg::PostLiteral::POST_MODE_UPDATE>(reg_srcLd, srcUbLdPrt, oneRepeat_);
240- MicroAPI::DataCopy<Tin, MicroAPI::PostLiteral::POST_MODE_UPDATE>(reg_srcRd, srcUbRdPrt, oneRepeat_);240+ Reg::DataCopy<Tin, Reg::PostLiteral::POST_MODE_UPDATE>(reg_srcRd, srcUbRdPrt, oneRepeat_);
241 if constexpr (sizeof(Tin) != sizeof(int32_t)) {241 if constexpr (sizeof(Tin) != sizeof(int32_t)) {
242- MicroAPI::UnPack((RegTensor<int32_t>&)reg_srcLui32, (RegTensor<int16_t>&)reg_srcLu);242+ Reg::UnPack((RegTensor<int32_t>&)reg_srcLui32, (RegTensor<int16_t>&)reg_srcLu);
243- MicroAPI::UnPack((RegTensor<int32_t>&)reg_srcRui32, (RegTensor<int16_t>&)reg_srcRu);243+ Reg::UnPack((RegTensor<int32_t>&)reg_srcRui32, (RegTensor<int16_t>&)reg_srcRu);
244- MicroAPI::UnPack((RegTensor<int32_t>&)reg_srcLdi32, (RegTensor<int16_t>&)reg_srcLd);244+ Reg::UnPack((RegTensor<int32_t>&)reg_srcLdi32, (RegTensor<int16_t>&)reg_srcLd);
245- MicroAPI::UnPack((RegTensor<int32_t>&)reg_srcRdi32, (RegTensor<int16_t>&)reg_srcRd);245+ Reg::UnPack((RegTensor<int32_t>&)reg_srcRdi32, (RegTensor<int16_t>&)reg_srcRd);
246- MicroAPI::Cast<float, Tin, castTrait0>(regSrcLuf32, reg_srcLui32, pregFp32);246+ Reg::Cast<float, Tin, castTrait0>(regSrcLuf32, reg_srcLui32, pregFp32);
247- MicroAPI::Cast<float, Tin, castTrait0>(regSrcRuf32, reg_srcRui32, pregFp32);247+ Reg::Cast<float, Tin, castTrait0>(regSrcRuf32, reg_srcRui32, pregFp32);
248- MicroAPI::Cast<float, Tin, castTrait0>(regSrcLdf32, reg_srcLdi32, pregFp32);248+ Reg::Cast<float, Tin, castTrait0>(regSrcLdf32, reg_srcLdi32, pregFp32);
249- MicroAPI::Cast<float, Tin, castTrait0>(regSrcRdf32, reg_srcRdi32, pregFp32);249+ Reg::Cast<float, Tin, castTrait0>(regSrcRdf32, reg_srcRdi32, pregFp32);
250- MicroAPI::Muls(regSrcLuf32, regSrcLuf32, delta_lu, pregFp32);250+ Reg::Muls(regSrcLuf32, regSrcLuf32, delta_lu, pregFp32);
251- MicroAPI::Muls(regSrcRuf32, regSrcRuf32, delta_ru, pregFp32);251+ Reg::Muls(regSrcRuf32, regSrcRuf32, delta_ru, pregFp32);
252- MicroAPI::Muls(regSrcLdf32, regSrcLdf32, delta_ld, pregFp32);252+ Reg::Muls(regSrcLdf32, regSrcLdf32, delta_ld, pregFp32);
253- MicroAPI::Muls(regSrcRdf32, regSrcRdf32, delta_rd, pregFp32);253+ Reg::Muls(regSrcRdf32, regSrcRdf32, delta_rd, pregFp32);
254 } else {254 } else {
255- MicroAPI::Muls(regSrcLuf32, reg_srcLu, delta_lu, pregFp32);255+ Reg::Muls(regSrcLuf32, reg_srcLu, delta_lu, pregFp32);
256- MicroAPI::Muls(regSrcRuf32, reg_srcRu, delta_ru, pregFp32);256+ Reg::Muls(regSrcRuf32, reg_srcRu, delta_ru, pregFp32);
257- MicroAPI::Muls(regSrcLdf32, reg_srcLd, delta_ld, pregFp32);257+ Reg::Muls(regSrcLdf32, reg_srcLd, delta_ld, pregFp32);
258- MicroAPI::Muls(regSrcRdf32, reg_srcRd, delta_rd, pregFp32);258+ Reg::Muls(regSrcRdf32, reg_srcRd, delta_rd, pregFp32);
259 }259 }
260- MicroAPI::Add(regSumUpperF32, regSrcLuf32, regSrcRuf32, pregFp32);260+ Reg::Add(regSumUpperF32, regSrcLuf32, regSrcRuf32, pregFp32);
261- MicroAPI::Add(regSumDownF32, regSrcLdf32, regSrcRdf32, pregFp32);261+ Reg::Add(regSumDownF32, regSrcLdf32, regSrcRdf32, pregFp32);
262- MicroAPI::Add(regSumF32, regSumUpperF32, regSumDownF32, pregFp32);262+ Reg::Add(regSumF32, regSumUpperF32, regSumDownF32, pregFp32);
263 263 
264 if constexpr (sizeof(Tout) == sizeof(int16_t)) {264 if constexpr (sizeof(Tout) == sizeof(int16_t)) {
265- MicroAPI::Cast<Tout, float, castTrait1>(regTmpT2, regSumF32, pregFp32);265+ Reg::Cast<Tout, float, castTrait1>(regTmpT2, regSumF32, pregFp32);
266- MicroAPI::Pack((RegTensor<uint16_t>&)regOutputT2, (RegTensor<uint32_t>&)regTmpT2);266+ Reg::Pack((RegTensor<uint16_t>&)regOutputT2, (RegTensor<uint32_t>&)regTmpT2);
267- MicroAPI::MaskPack(pregFp16, pregFp32);267+ Reg::MaskPack(pregFp16, pregFp32);
268- MicroAPI::DataCopy<Tout, MicroAPI::PostLiteral::POST_MODE_UPDATE>(dstUbPtr, regOutputT2, oneRepeat_,268+ Reg::DataCopy<Tout, Reg::PostLiteral::POST_MODE_UPDATE>(dstUbPtr, regOutputT2, oneRepeat_, pregFp16);
269- pregFp16);
270 } else {269 } else {
271- MicroAPI::DataCopy<Tout, MicroAPI::PostLiteral::POST_MODE_UPDATE>(dstUbPtr, regSumF32, oneRepeat_,270+ Reg::DataCopy<Tout, Reg::PostLiteral::POST_MODE_UPDATE>(dstUbPtr, regSumF32, oneRepeat_, pregFp32);
272- pregFp32);
273 }271 }
274 }272 }
275 }273 }
@@ -346,7 +344,7 @@ __aicore__ inline void ResizeBilinearV2Nc<Tin, Tout>::DivideNhwc()
346 src_offset = base_src_offset + (lenSrcW_ * src_down + src_right) * lenC_ + idx_c +344 src_offset = base_src_offset + (lenSrcW_ * src_down + src_right) * lenC_ + idx_c +
347 point_offset_st.cStart;345 point_offset_st.cStart;
348 DataCopyPadGm2Ub(inQueue3, xGm_, src_offset, process_length);346 DataCopyPadGm2Ub(inQueue3, xGm_, src_offset, process_length);
349- // Step2: compute value throw MicroAPI347+ // Step2: compute value throw Reg
350 LocalTensor<Tout> ubTensorOut = outQueue.AllocTensor<Tout>();348 LocalTensor<Tout> ubTensorOut = outQueue.AllocTensor<Tout>();
351 ComputeDstValueWith4SrcDot(ubTensorOut, process_length);349 ComputeDstValueWith4SrcDot(ubTensorOut, process_length);
352 outQueue.EnQue(ubTensorOut);350 outQueue.EnQue(ubTensorOut);
Mimage/resize_bilinear_v2_grad/op_kernel/arch35/resize_bilinear_v2_grad_c_parallel.h+51-59
@@ -20,7 +20,7 @@
20 20 
21namespace ResizeBilinearV2Grad {21namespace ResizeBilinearV2Grad {
22using namespace AscendC;22using namespace AscendC;
23-using AscendC::MicroAPI::RegTensor;23+using AscendC::Reg::RegTensor;
24constexpr int32_t BUFF_NUM = 2;24constexpr int32_t BUFF_NUM = 2;
25constexpr int32_t POS_LU = 0;25constexpr int32_t POS_LU = 0;
26constexpr int32_t POS_RU = 1;26constexpr int32_t POS_RU = 1;
@@ -89,13 +89,13 @@ private:
89 int64_t dataBuffLen_ = 0;89 int64_t dataBuffLen_ = 0;
90 float delta_[POS_TOTAL];90 float delta_[POS_TOTAL];
91 uint32_t oneRepeat_ = Ops::Base::GetVRegSize() / sizeof(float);91 uint32_t oneRepeat_ = Ops::Base::GetVRegSize() / sizeof(float);
92- constexpr static AscendC::MicroAPI::CastTrait castTrait0 = {92+ constexpr static AscendC::Reg::CastTrait castTrait0 = {
93- AscendC::MicroAPI::RegLayout::ZERO, AscendC::MicroAPI::SatMode::UNKNOWN,93+ AscendC::Reg::RegLayout::ZERO, AscendC::Reg::SatMode::UNKNOWN, AscendC::Reg::MaskMergeMode::ZEROING,
94- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::UNKNOWN}; // bf16 --float94+ AscendC::RoundMode::UNKNOWN}; // bf16 --float
95 95 
96- constexpr static AscendC::MicroAPI::CastTrait castTrait1 = {96+ constexpr static AscendC::Reg::CastTrait castTrait1 = {AscendC::Reg::RegLayout::ZERO, AscendC::Reg::SatMode::NO_SAT,
97- AscendC::MicroAPI::RegLayout::ZERO, AscendC::MicroAPI::SatMode::NO_SAT,97+ AscendC::Reg::MaskMergeMode::ZEROING,
98- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_RINT}; // float---bf1698+ AscendC::RoundMode::CAST_RINT}; // float---bf16
99};99};
100 100 
101template <typename T_GRADS, typename T_OUT>101template <typename T_GRADS, typename T_OUT>
@@ -182,69 +182,61 @@ __aicore__ inline void ResizeBilinearV2GradNc<T_GRADS, T_OUT>::Compute4SrcDotWit
182 182 
183 __VEC_SCOPE__183 __VEC_SCOPE__
184 {184 {
185- MicroAPI::MaskReg pregFp16;185+ Reg::MaskReg pregFp16;
186- MicroAPI::MaskReg pregFp32;186+ Reg::MaskReg pregFp32;
187- MicroAPI::RegTensor<T_GRADS> reg_grads;187+ Reg::RegTensor<T_GRADS> reg_grads;
188- MicroAPI::RegTensor<T_GRADS> reg_grads_i32;188+ Reg::RegTensor<T_GRADS> reg_grads_i32;
189- MicroAPI::RegTensor<float> reg_grads_f32;189+ Reg::RegTensor<float> reg_grads_f32;
190- MicroAPI::RegTensor<float> reg_out_lu;190+ Reg::RegTensor<float> reg_out_lu;
191- MicroAPI::RegTensor<float> reg_out_ru;191+ Reg::RegTensor<float> reg_out_ru;
192- MicroAPI::RegTensor<float> reg_out_ld;192+ Reg::RegTensor<float> reg_out_ld;
193- MicroAPI::RegTensor<float> reg_out_rd;193+ Reg::RegTensor<float> reg_out_rd;
194- MicroAPI::RegTensor<T_OUT> regTmpOutput;194+ Reg::RegTensor<T_OUT> regTmpOutput;
195- MicroAPI::RegTensor<T_OUT> regOutLu;195+ Reg::RegTensor<T_OUT> regOutLu;
196- MicroAPI::RegTensor<T_OUT> regOutRu;196+ Reg::RegTensor<T_OUT> regOutRu;
197- MicroAPI::RegTensor<T_OUT> regOutLd;197+ Reg::RegTensor<T_OUT> regOutLd;
198- MicroAPI::RegTensor<T_OUT> regOutRd;198+ Reg::RegTensor<T_OUT> regOutRd;
199 199 
200 for (uint16_t idx = 0; idx < repeatTimes; idx++) {200 for (uint16_t idx = 0; idx < repeatTimes; idx++) {
201- pregFp32 = AscendC::MicroAPI::UpdateMask<float>(totalLen);201+ pregFp32 = AscendC::Reg::UpdateMask<float>(totalLen);
202- MicroAPI::DataCopy<T_GRADS, MicroAPI::PostLiteral::POST_MODE_UPDATE>(reg_grads, gradsUbPtr, oneRepeat_);202+ Reg::DataCopy<T_GRADS, Reg::PostLiteral::POST_MODE_UPDATE>(reg_grads, gradsUbPtr, oneRepeat_);
203 if constexpr (sizeof(T_GRADS) != sizeof(int32_t)) {203 if constexpr (sizeof(T_GRADS) != sizeof(int32_t)) {
204- MicroAPI::UnPack((RegTensor<int32_t>&)reg_grads_i32, (RegTensor<int16_t>&)reg_grads);204+ Reg::UnPack((RegTensor<int32_t>&)reg_grads_i32, (RegTensor<int16_t>&)reg_grads);
205- MicroAPI::Cast<float, T_GRADS, castTrait0>(reg_grads_f32, reg_grads_i32, pregFp32);205+ Reg::Cast<float, T_GRADS, castTrait0>(reg_grads_f32, reg_grads_i32, pregFp32);
206- MicroAPI::Muls(reg_out_lu, reg_grads_f32, delta_[POS_LU], pregFp32);206+ Reg::Muls(reg_out_lu, reg_grads_f32, delta_[POS_LU], pregFp32);
207- MicroAPI::Muls(reg_out_ru, reg_grads_f32, delta_[POS_RU], pregFp32);207+ Reg::Muls(reg_out_ru, reg_grads_f32, delta_[POS_RU], pregFp32);
208- MicroAPI::Muls(reg_out_ld, reg_grads_f32, delta_[POS_LD], pregFp32);208+ Reg::Muls(reg_out_ld, reg_grads_f32, delta_[POS_LD], pregFp32);
209- MicroAPI::Muls(reg_out_rd, reg_grads_f32, delta_[POS_RD], pregFp32);209+ Reg::Muls(reg_out_rd, reg_grads_f32, delta_[POS_RD], pregFp32);
210 } else {210 } else {
211- MicroAPI::Muls(reg_out_lu, reg_grads, delta_[POS_LU], pregFp32);211+ Reg::Muls(reg_out_lu, reg_grads, delta_[POS_LU], pregFp32);
212- MicroAPI::Muls(reg_out_ru, reg_grads, delta_[POS_RU], pregFp32);212+ Reg::Muls(reg_out_ru, reg_grads, delta_[POS_RU], pregFp32);
213- MicroAPI::Muls(reg_out_ld, reg_grads, delta_[POS_LD], pregFp32);213+ Reg::Muls(reg_out_ld, reg_grads, delta_[POS_LD], pregFp32);
214- MicroAPI::Muls(reg_out_rd, reg_grads, delta_[POS_RD], pregFp32);214+ Reg::Muls(reg_out_rd, reg_grads, delta_[POS_RD], pregFp32);
215 }215 }
216 216 
217 if constexpr (sizeof(T_OUT) == sizeof(int16_t)) {217 if constexpr (sizeof(T_OUT) == sizeof(int16_t)) {
218- MicroAPI::Cast<T_OUT, float, castTrait1>(regTmpOutput, reg_out_lu, pregFp32);218+ Reg::Cast<T_OUT, float, castTrait1>(regTmpOutput, reg_out_lu, pregFp32);
219- MicroAPI::Pack((RegTensor<uint16_t>&)regOutLu, (RegTensor<uint32_t>&)regTmpOutput);219+ Reg::Pack((RegTensor<uint16_t>&)regOutLu, (RegTensor<uint32_t>&)regTmpOutput);
220 220 
221- MicroAPI::Cast<T_OUT, float, castTrait1>(regTmpOutput, reg_out_ru, pregFp32);221+ Reg::Cast<T_OUT, float, castTrait1>(regTmpOutput, reg_out_ru, pregFp32);
222- MicroAPI::Pack((RegTensor<uint16_t>&)regOutRu, (RegTensor<uint32_t>&)regTmpOutput);222+ Reg::Pack((RegTensor<uint16_t>&)regOutRu, (RegTensor<uint32_t>&)regTmpOutput);
223 223 
224- MicroAPI::Cast<T_OUT, float, castTrait1>(regTmpOutput, reg_out_ld, pregFp32);224+ Reg::Cast<T_OUT, float, castTrait1>(regTmpOutput, reg_out_ld, pregFp32);
225- MicroAPI::Pack((RegTensor<uint16_t>&)regOutLd, (RegTensor<uint32_t>&)regTmpOutput);225+ Reg::Pack((RegTensor<uint16_t>&)regOutLd, (RegTensor<uint32_t>&)regTmpOutput);
226 226 
227- MicroAPI::Cast<T_OUT, float, castTrait1>(regTmpOutput, reg_out_rd, pregFp32);227+ Reg::Cast<T_OUT, float, castTrait1>(regTmpOutput, reg_out_rd, pregFp32);
228- MicroAPI::Pack((RegTensor<uint16_t>&)regOutRd, (RegTensor<uint32_t>&)regTmpOutput);228+ Reg::Pack((RegTensor<uint16_t>&)regOutRd, (RegTensor<uint32_t>&)regTmpOutput);
229 229 
230- MicroAPI::MaskPack(pregFp16, pregFp32);230+ Reg::MaskPack(pregFp16, pregFp32);
231- MicroAPI::DataCopy<T_OUT, MicroAPI::PostLiteral::POST_MODE_UPDATE>(outUbPtrLu, regOutLu, oneRepeat_,231+ Reg::DataCopy<T_OUT, Reg::PostLiteral::POST_MODE_UPDATE>(outUbPtrLu, regOutLu, oneRepeat_, pregFp16);
232- pregFp16);232+ Reg::DataCopy<T_OUT, Reg::PostLiteral::POST_MODE_UPDATE>(outUbPtrRu, regOutRu, oneRepeat_, pregFp16);
233- MicroAPI::DataCopy<T_OUT, MicroAPI::PostLiteral::POST_MODE_UPDATE>(outUbPtrRu, regOutRu, oneRepeat_,233+ Reg::DataCopy<T_OUT, Reg::PostLiteral::POST_MODE_UPDATE>(outUbPtrLd, regOutLd, oneRepeat_, pregFp16);
234- pregFp16);234+ Reg::DataCopy<T_OUT, Reg::PostLiteral::POST_MODE_UPDATE>(outUbPtrRd, regOutRd, oneRepeat_, pregFp16);
235- MicroAPI::DataCopy<T_OUT, MicroAPI::PostLiteral::POST_MODE_UPDATE>(outUbPtrLd, regOutLd, oneRepeat_,
236- pregFp16);
237- MicroAPI::DataCopy<T_OUT, MicroAPI::PostLiteral::POST_MODE_UPDATE>(outUbPtrRd, regOutRd, oneRepeat_,
238- pregFp16);
239 } else {235 } else {
240- MicroAPI::DataCopy<T_OUT, MicroAPI::PostLiteral::POST_MODE_UPDATE>(outUbPtrLu, reg_out_lu, oneRepeat_,236+ Reg::DataCopy<T_OUT, Reg::PostLiteral::POST_MODE_UPDATE>(outUbPtrLu, reg_out_lu, oneRepeat_, pregFp32);
241- pregFp32);237+ Reg::DataCopy<T_OUT, Reg::PostLiteral::POST_MODE_UPDATE>(outUbPtrRu, reg_out_ru, oneRepeat_, pregFp32);
242- MicroAPI::DataCopy<T_OUT, MicroAPI::PostLiteral::POST_MODE_UPDATE>(outUbPtrRu, reg_out_ru, oneRepeat_,238+ Reg::DataCopy<T_OUT, Reg::PostLiteral::POST_MODE_UPDATE>(outUbPtrLd, reg_out_ld, oneRepeat_, pregFp32);
243- pregFp32);239+ Reg::DataCopy<T_OUT, Reg::PostLiteral::POST_MODE_UPDATE>(outUbPtrRd, reg_out_rd, oneRepeat_, pregFp32);
244- MicroAPI::DataCopy<T_OUT, MicroAPI::PostLiteral::POST_MODE_UPDATE>(outUbPtrLd, reg_out_ld, oneRepeat_,
245- pregFp32);
246- MicroAPI::DataCopy<T_OUT, MicroAPI::PostLiteral::POST_MODE_UPDATE>(outUbPtrRd, reg_out_rd, oneRepeat_,
247- pregFp32);
248 }240 }
249 }241 }
250 }242 }
@@ -346,7 +338,7 @@ __aicore__ inline void ResizeBilinearV2GradNc<T_GRADS, T_OUT>::ComputeDivideN(Of
346 stOffset.cDataLen = this->Min(ubCFactor_, stOffset.cLength - idx_c);338 stOffset.cDataLen = this->Min(ubCFactor_, stOffset.cLength - idx_c);
347 // Step1: copy data from input gm to ub339 // Step1: copy data from input gm to ub
348 DataCopyPadGm2UbV2(gradsQueue, gradsGm_, stOffset);340 DataCopyPadGm2UbV2(gradsQueue, gradsGm_, stOffset);
349- // Step2: compute value throw MicroAPI341+ // Step2: compute value throw Reg
350 Compute4SrcDotWithGrads(dataBuffLen_);342 Compute4SrcDotWithGrads(dataBuffLen_);
351 // Step3: copy data from ub to output gm343 // Step3: copy data from ub to output gm
352 DataMoveUb2Gm(outQueue, yGm_, stOffset);344 DataMoveUb2Gm(outQueue, yGm_, stOffset);
Mimage/resize_nearest_neighbor_v2/op_kernel/arch35/resize_nearest_neighbor_v2_data_copy_nhwc.h+4-4
@@ -22,10 +22,10 @@
22 22 
23namespace ResizeNearestNeighborV2 {23namespace ResizeNearestNeighborV2 {
24using namespace AscendC;24using namespace AscendC;
25-using AscendC::MicroAPI::AddrReg;25+using AscendC::Reg::AddrReg;
26-using AscendC::MicroAPI::CreateAddrReg;26+using AscendC::Reg::CreateAddrReg;
27-using AscendC::MicroAPI::RegTensor;27+using AscendC::Reg::RegTensor;
28-using AscendC::MicroAPI::UpdateMask;28+using AscendC::Reg::UpdateMask;
29 29 
30template <typename T, int cutNH>30template <typename T, int cutNH>
31class ResizeNearestNeighborV2NHWC {31class ResizeNearestNeighborV2NHWC {
Mimage/resize_nearest_neighbor_v2/op_kernel/arch35/resize_nearest_neighbor_v2_gather.h+40-43
@@ -46,12 +46,12 @@ private:
46 constexpr static int32_t bufferNum = 2;46 constexpr static int32_t bufferNum = 2;
47 constexpr static int64_t NUM_FOUR = 4;47 constexpr static int64_t NUM_FOUR = 4;
48 constexpr static int32_t blockSize = 32;48 constexpr static int32_t blockSize = 32;
49- constexpr static AscendC::MicroAPI::CastTrait castTraitRound = {49+ constexpr static AscendC::Reg::CastTrait castTraitRound = {
50- AscendC::MicroAPI::RegLayout::UNKNOWN, AscendC::MicroAPI::SatMode::NO_SAT,50+ AscendC::Reg::RegLayout::UNKNOWN, AscendC::Reg::SatMode::NO_SAT, AscendC::Reg::MaskMergeMode::ZEROING,
51- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_ROUND};51+ AscendC::RoundMode::CAST_ROUND};
52- constexpr static AscendC::MicroAPI::CastTrait castTraitFloor = {52+ constexpr static AscendC::Reg::CastTrait castTraitFloor = {
53- AscendC::MicroAPI::RegLayout::UNKNOWN, AscendC::MicroAPI::SatMode::NO_SAT,53+ AscendC::Reg::RegLayout::UNKNOWN, AscendC::Reg::SatMode::NO_SAT, AscendC::Reg::MaskMergeMode::ZEROING,
54- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_FLOOR};54+ AscendC::RoundMode::CAST_FLOOR};
55 55 
56private:56private:
57 TPipe pipe;57 TPipe pipe;
@@ -259,21 +259,20 @@ __aicore__ inline void ResizeNearestNeighborV2Gather<T>::ComputeMain(__ubuf__ T*
259{259{
260 __VEC_SCOPE__260 __VEC_SCOPE__
261 {261 {
262- AscendC::MicroAPI::RegTensor<int32_t> idxInitLower;262+ AscendC::Reg::RegTensor<int32_t> idxInitLower;
263- AscendC::MicroAPI::RegTensor<int32_t> idxInitHeigher;263+ AscendC::Reg::RegTensor<int32_t> idxInitHeigher;
264- AscendC::MicroAPI::RegTensor<float> idxLowerF;264+ AscendC::Reg::RegTensor<float> idxLowerF;
265- AscendC::MicroAPI::RegTensor<float> idxHigherF;265+ AscendC::Reg::RegTensor<float> idxHigherF;
266- AscendC::MicroAPI::RegTensor<int32_t> idxLowerI;266+ AscendC::Reg::RegTensor<int32_t> idxLowerI;
267- AscendC::MicroAPI::RegTensor<int32_t> idxHigherI;267+ AscendC::Reg::RegTensor<int32_t> idxHigherI;
268- AscendC::MicroAPI::RegTensor<uint16_t> idxLower;268+ AscendC::Reg::RegTensor<uint16_t> idxLower;
269- AscendC::MicroAPI::RegTensor<uint16_t> idxHigher;269+ AscendC::Reg::RegTensor<uint16_t> idxHigher;
270- AscendC::MicroAPI::RegTensor<T> vDstReg;270+ AscendC::Reg::RegTensor<T> vDstReg;
271- AscendC::MicroAPI::UnalignReg u0;271+ AscendC::Reg::UnalignReg u0;
272 272 
273- AscendC::MicroAPI::MaskReg273+ AscendC::Reg::MaskReg preg32 = AscendC::Reg::CreateMask<uint32_t, AscendC::Reg::MaskPattern::ALL>();
274- preg32 = AscendC::MicroAPI::CreateMask<uint32_t, AscendC::MicroAPI::MaskPattern::ALL>();
275 uint32_t sregLast = num;274 uint32_t sregLast = num;
276- AscendC::MicroAPI::MaskReg preg16 = AscendC::MicroAPI::UpdateMask<uint16_t>(sregLast);275+ AscendC::Reg::MaskReg preg16 = AscendC::Reg::UpdateMask<uint16_t>(sregLast);
277 float sregLow = startIdx;276 float sregLow = startIdx;
278 Arange(idxLowerF, sregLow);277 Arange(idxLowerF, sregLow);
279 Muls(idxLowerF, idxLowerF, wScale_, preg32);278 Muls(idxLowerF, idxLowerF, wScale_, preg32);
@@ -294,14 +293,14 @@ __aicore__ inline void ResizeNearestNeighborV2Gather<T>::ComputeMain(__ubuf__ T*
294 __ubuf__ T* dstUbT = dstAddr;293 __ubuf__ T* dstUbT = dstAddr;
295 for (uint16_t j = 0; j < static_cast<uint16_t>(hNum_); ++j) {294 for (uint16_t j = 0; j < static_cast<uint16_t>(hNum_); ++j) {
296 Adds(idxLowerI, idxInitLower, static_cast<int32_t>(srcWAlign_) * hIdexUb.GetValue(j), preg32);295 Adds(idxLowerI, idxInitLower, static_cast<int32_t>(srcWAlign_) * hIdexUb.GetValue(j), preg32);
297- MicroAPI::Pack<uint16_t, int32_t, AscendC::MicroAPI::HighLowPart::LOWEST>(idxLower, idxLowerI);296+ Reg::Pack<uint16_t, int32_t, AscendC::Reg::HighLowPart::LOWEST>(idxLower, idxLowerI);
298 Adds(idxHigherI, idxInitHeigher, static_cast<int32_t>(srcWAlign_) * hIdexUb.GetValue(j), preg32);297 Adds(idxHigherI, idxInitHeigher, static_cast<int32_t>(srcWAlign_) * hIdexUb.GetValue(j), preg32);
299- MicroAPI::Pack<uint16_t, int32_t, AscendC::MicroAPI::HighLowPart::HIGHEST>(idxHigher, idxHigherI);298+ Reg::Pack<uint16_t, int32_t, AscendC::Reg::HighLowPart::HIGHEST>(idxHigher, idxHigherI);
300 Or(idxLower, idxLower, idxHigher, preg16);299 Or(idxLower, idxLower, idxHigher, preg16);
301 DataCopyGather(vDstReg, srcAddr, idxLower, preg16);300 DataCopyGather(vDstReg, srcAddr, idxLower, preg16);
302 dstUbT = dstAddr + j * wNum_;301 dstUbT = dstAddr + j * wNum_;
303 DataCopyUnAlign(dstUbT, vDstReg, u0, num);302 DataCopyUnAlign(dstUbT, vDstReg, u0, num);
304- AscendC::MicroAPI::DataCopyUnAlignPost(dstUbT, u0, 0);303+ AscendC::Reg::DataCopyUnAlignPost(dstUbT, u0, 0);
305 }304 }
306 }305 }
307}306}
@@ -313,18 +312,17 @@ __aicore__ inline void ResizeNearestNeighborV2Gather<T>::ComputeTail(__ubuf__ T*
313{312{
314 __VEC_SCOPE__313 __VEC_SCOPE__
315 {314 {
316- AscendC::MicroAPI::RegTensor<float> idxLowerF;315+ AscendC::Reg::RegTensor<float> idxLowerF;
317- AscendC::MicroAPI::RegTensor<int32_t> idxLowerI;316+ AscendC::Reg::RegTensor<int32_t> idxLowerI;
318- AscendC::MicroAPI::RegTensor<int32_t> idxInit;317+ AscendC::Reg::RegTensor<int32_t> idxInit;
319- AscendC::MicroAPI::RegTensor<uint16_t> idxLower;318+ AscendC::Reg::RegTensor<uint16_t> idxLower;
320- AscendC::MicroAPI::UnalignReg u0;319+ AscendC::Reg::UnalignReg u0;
321- AscendC::MicroAPI::RegTensor<T> vDstReg;320+ AscendC::Reg::RegTensor<T> vDstReg;
322 321 
323- AscendC::MicroAPI::MaskReg322+ AscendC::Reg::MaskReg mask0 = AscendC::Reg::CreateMask<uint32_t, AscendC::Reg::MaskPattern::ALL>();
324- mask0 = AscendC::MicroAPI::CreateMask<uint32_t, AscendC::MicroAPI::MaskPattern::ALL>();
325 uint32_t sregTail = wTail_;323 uint32_t sregTail = wTail_;
326 float sregLow = startIdx;324 float sregLow = startIdx;
327- AscendC::MicroAPI::MaskReg mask1 = AscendC::MicroAPI::UpdateMask<uint16_t>(sregTail);325+ AscendC::Reg::MaskReg mask1 = AscendC::Reg::UpdateMask<uint16_t>(sregTail);
328 // init w direction index326 // init w direction index
329 Arange(idxLowerF, sregLow);327 Arange(idxLowerF, sregLow);
330 Muls(idxLowerF, idxLowerF, wScale_, mask0);328 Muls(idxLowerF, idxLowerF, wScale_, mask0);
@@ -338,11 +336,11 @@ __aicore__ inline void ResizeNearestNeighborV2Gather<T>::ComputeTail(__ubuf__ T*
338 __ubuf__ T* dstUbT = dstAddr;336 __ubuf__ T* dstUbT = dstAddr;
339 for (uint16_t i = 0; i < static_cast<uint16_t>(hNum_); ++i) {337 for (uint16_t i = 0; i < static_cast<uint16_t>(hNum_); ++i) {
340 Adds(idxLowerI, idxInit, srcWAlign_ * hIdexUb.GetValue(i), mask0);338 Adds(idxLowerI, idxInit, srcWAlign_ * hIdexUb.GetValue(i), mask0);
341- MicroAPI::Pack<uint16_t, int32_t, AscendC::MicroAPI::HighLowPart::LOWEST>(idxLower, idxLowerI);339+ Reg::Pack<uint16_t, int32_t, AscendC::Reg::HighLowPart::LOWEST>(idxLower, idxLowerI);
342 DataCopyGather(vDstReg, srcAddr, idxLower, mask1);340 DataCopyGather(vDstReg, srcAddr, idxLower, mask1);
343 dstUbT = dstAddr + i * wNum_;341 dstUbT = dstAddr + i * wNum_;
344 DataCopyUnAlign(dstUbT, vDstReg, u0, wTail_);342 DataCopyUnAlign(dstUbT, vDstReg, u0, wTail_);
345- AscendC::MicroAPI::DataCopyUnAlignPost(dstUbT, u0, 0);343+ AscendC::Reg::DataCopyUnAlignPost(dstUbT, u0, 0);
346 }344 }
347 }345 }
348}346}
@@ -354,16 +352,15 @@ __aicore__ inline void ResizeNearestNeighborV2Gather<T>::Compute32(__ubuf__ T* d
354{352{
355 __VEC_SCOPE__353 __VEC_SCOPE__
356 {354 {
357- AscendC::MicroAPI::RegTensor<float> idxFloat;355+ AscendC::Reg::RegTensor<float> idxFloat;
358- AscendC::MicroAPI::RegTensor<int32_t> idxInt32;356+ AscendC::Reg::RegTensor<int32_t> idxInt32;
359- AscendC::MicroAPI::RegTensor<int32_t> idxInit;357+ AscendC::Reg::RegTensor<int32_t> idxInit;
360- AscendC::MicroAPI::RegTensor<T> vDstReg;358+ AscendC::Reg::RegTensor<T> vDstReg;
361- AscendC::MicroAPI::UnalignReg u0;359+ AscendC::Reg::UnalignReg u0;
362 360 
363 uint32_t sregTail = num;361 uint32_t sregTail = num;
364- AscendC::MicroAPI::MaskReg362+ AscendC::Reg::MaskReg mask0 = AscendC::Reg::CreateMask<uint32_t, AscendC::Reg::MaskPattern::ALL>();
365- mask0 = AscendC::MicroAPI::CreateMask<uint32_t, AscendC::MicroAPI::MaskPattern::ALL>();363+ AscendC::Reg::MaskReg mask1 = AscendC::Reg::UpdateMask<uint32_t>(sregTail);
366- AscendC::MicroAPI::MaskReg mask1 = AscendC::MicroAPI::UpdateMask<uint32_t>(sregTail);
367 364 
368 float sregLow = startIdx;365 float sregLow = startIdx;
369 Arange(idxFloat, sregLow);366 Arange(idxFloat, sregLow);
@@ -378,10 +375,10 @@ __aicore__ inline void ResizeNearestNeighborV2Gather<T>::Compute32(__ubuf__ T* d
378 __ubuf__ T* dstUbT = dstAddr;375 __ubuf__ T* dstUbT = dstAddr;
379 for (uint16_t i = 0; i < static_cast<uint16_t>(hNum_); ++i) {376 for (uint16_t i = 0; i < static_cast<uint16_t>(hNum_); ++i) {
380 Adds(idxInt32, idxInit, static_cast<int32_t>(srcWAlign_) * hIdexUb.GetValue(i), mask0);377 Adds(idxInt32, idxInit, static_cast<int32_t>(srcWAlign_) * hIdexUb.GetValue(i), mask0);
381- DataCopyGather(vDstReg, srcAddr, (AscendC::MicroAPI::RegTensor<uint32_t>&)idxInt32, mask1);378+ DataCopyGather(vDstReg, srcAddr, (AscendC::Reg::RegTensor<uint32_t>&)idxInt32, mask1);
382 dstUbT = dstAddr + i * wNum_;379 dstUbT = dstAddr + i * wNum_;
383 DataCopyUnAlign(dstUbT, vDstReg, u0, num);380 DataCopyUnAlign(dstUbT, vDstReg, u0, num);
384- AscendC::MicroAPI::DataCopyUnAlignPost(dstUbT, u0, 0);381+ AscendC::Reg::DataCopyUnAlignPost(dstUbT, u0, 0);
385 }382 }
386 }383 }
387}384}
Mimage/resize_nearest_neighbor_v2/op_kernel/arch35/resize_nearest_neighbor_v2_nchw_gather.h+97-100
@@ -22,10 +22,10 @@
22 22 
23namespace ResizeNearestNeighborV2 {23namespace ResizeNearestNeighborV2 {
24using namespace AscendC;24using namespace AscendC;
25-using AscendC::MicroAPI::AddrReg;25+using AscendC::Reg::AddrReg;
26-using AscendC::MicroAPI::CreateAddrReg;26+using AscendC::Reg::CreateAddrReg;
27-using AscendC::MicroAPI::RegTensor;27+using AscendC::Reg::RegTensor;
28-using AscendC::MicroAPI::UpdateMask;28+using AscendC::Reg::UpdateMask;
29 29 
30template <typename T, typename T1, int schId, bool alignCorners>30template <typename T, typename T1, int schId, bool alignCorners>
31class ResizeGather {31class ResizeGather {
@@ -57,15 +57,15 @@ private:
57 __aicore__ inline void ComputeHids(LocalTensor<T1>& idxHUb, int64_t hFactor);57 __aicore__ inline void ComputeHids(LocalTensor<T1>& idxHUb, int64_t hFactor);
58 constexpr static int32_t bufferNum = 2;58 constexpr static int32_t bufferNum = 2;
59 59 
60- constexpr static AscendC::MicroAPI::CastTrait castTraitRound = {60+ constexpr static AscendC::Reg::CastTrait castTraitRound = {
61- AscendC::MicroAPI::RegLayout::UNKNOWN, AscendC::MicroAPI::SatMode::NO_SAT,61+ AscendC::Reg::RegLayout::UNKNOWN, AscendC::Reg::SatMode::NO_SAT, AscendC::Reg::MaskMergeMode::ZEROING,
62- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_ROUND};62+ AscendC::RoundMode::CAST_ROUND};
63- constexpr static AscendC::MicroAPI::CastTrait castTraitFloor = {63+ constexpr static AscendC::Reg::CastTrait castTraitFloor = {
64- AscendC::MicroAPI::RegLayout::UNKNOWN, AscendC::MicroAPI::SatMode::NO_SAT,64+ AscendC::Reg::RegLayout::UNKNOWN, AscendC::Reg::SatMode::NO_SAT, AscendC::Reg::MaskMergeMode::ZEROING,
65- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_FLOOR};65+ AscendC::RoundMode::CAST_FLOOR};
66- constexpr static AscendC::MicroAPI::CastTrait castInt32ToF = {66+ constexpr static AscendC::Reg::CastTrait castInt32ToF = {
67- AscendC::MicroAPI::RegLayout::UNKNOWN, AscendC::MicroAPI::SatMode::UNKNOWN,67+ AscendC::Reg::RegLayout::UNKNOWN, AscendC::Reg::SatMode::UNKNOWN, AscendC::Reg::MaskMergeMode::ZEROING,
68- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_FLOOR};68+ AscendC::RoundMode::CAST_FLOOR};
69 69 
70private:70private:
71 TPipe pipe;71 TPipe pipe;
@@ -207,33 +207,32 @@ __aicore__ inline void ResizeGather<T, T1, schId, alignCorners>::GatherOutput(Lo
207 uint32_t hwNum1 = dstLen;207 uint32_t hwNum1 = dstLen;
208 __VEC_SCOPE__208 __VEC_SCOPE__
209 {209 {
210- AscendC::MicroAPI::RegTensor<T1> startReg;210+ AscendC::Reg::RegTensor<T1> startReg;
211- AscendC::MicroAPI::RegTensor<T1> idxRegT;211+ AscendC::Reg::RegTensor<T1> idxRegT;
212- AscendC::MicroAPI::RegTensor<T> dstReg;212+ AscendC::Reg::RegTensor<T> dstReg;
213- AscendC::MicroAPI::MaskReg preg;213+ AscendC::Reg::MaskReg preg;
214 // 先处理第一行的hw214 // 先处理第一行的hw
215 Duplicate<T1>(startReg, srcHwNum);215 Duplicate<T1>(startReg, srcHwNum);
216 for (uint16_t j = 0; j < times; j++) {216 for (uint16_t j = 0; j < times; j++) {
217- preg = AscendC::MicroAPI::UpdateMask<T>(hwNum);217+ preg = AscendC::Reg::UpdateMask<T>(hwNum);
218- AscendC::MicroAPI::AddrReg srcIdxOffset = AscendC::MicroAPI::CreateAddrReg<T1>(j, vfLen);218+ AscendC::Reg::AddrReg srcIdxOffset = AscendC::Reg::CreateAddrReg<T1>(j, vfLen);
219- AscendC::MicroAPI::DataCopy(idxRegT, idxUbAddr, srcIdxOffset);219+ AscendC::Reg::DataCopy(idxRegT, idxUbAddr, srcIdxOffset);
220- AscendC::MicroAPI::Sub(idxRegT, idxRegT, startReg, preg);220+ AscendC::Reg::Sub(idxRegT, idxRegT, startReg, preg);
221 DataCopyGather(dstReg, srcUbAddr, idxRegT, preg);221 DataCopyGather(dstReg, srcUbAddr, idxRegT, preg);
222- AscendC::MicroAPI::DataCopy(dstUbAddr, dstReg, srcIdxOffset, preg);222+ AscendC::Reg::DataCopy(dstUbAddr, dstReg, srcIdxOffset, preg);
223 }223 }
224 // 从第二行开始处理224 // 从第二行开始处理
225 for (uint16_t nc = 0; nc < timesNc; nc++) {225 for (uint16_t nc = 0; nc < timesNc; nc++) {
226 for (uint16_t jj = 0; jj < times; jj++) {226 for (uint16_t jj = 0; jj < times; jj++) {
227- preg = AscendC::MicroAPI::UpdateMask<T>(hwNum1);227+ preg = AscendC::Reg::UpdateMask<T>(hwNum1);
228- AscendC::MicroAPI::AddrReg srcIdxOffset = AscendC::MicroAPI::CreateAddrReg<T1>(jj, vfLen);228+ AscendC::Reg::AddrReg srcIdxOffset = AscendC::Reg::CreateAddrReg<T1>(jj, vfLen);
229- AscendC::MicroAPI::DataCopy(idxRegT, idxUbAddr, srcIdxOffset);229+ AscendC::Reg::DataCopy(idxRegT, idxUbAddr, srcIdxOffset);
230- AscendC::MicroAPI::Sub(idxRegT, idxRegT, startReg, preg);230+ AscendC::Reg::Sub(idxRegT, idxRegT, startReg, preg);
231 for (uint16_t i = 0; i < ubFactorTimes; i++) {231 for (uint16_t i = 0; i < ubFactorTimes; i++) {
232- AscendC::MicroAPI::AddrReg outOffset = AscendC::MicroAPI::CreateAddrReg<T>(jj, vfLen, i,232+ AscendC::Reg::AddrReg outOffset = AscendC::Reg::CreateAddrReg<T>(jj, vfLen, i, dstHwAlign);
233- dstHwAlign);
234 Adds(idxRegT, idxRegT, srcLenNum, preg);233 Adds(idxRegT, idxRegT, srcLenNum, preg);
235 DataCopyGather(dstReg, srcUbAddr, idxRegT, preg);234 DataCopyGather(dstReg, srcUbAddr, idxRegT, preg);
236- AscendC::MicroAPI::DataCopy(dstUbAddr1, dstReg, outOffset, preg);235+ AscendC::Reg::DataCopy(dstUbAddr1, dstReg, outOffset, preg);
237 }236 }
238 }237 }
239 }238 }
@@ -278,15 +277,15 @@ __aicore__ inline void ResizeGather<T, T1, schId, alignCorners>::ComputeDataCopy
278 uint32_t onceSize = num;277 uint32_t onceSize = num;
279 __VEC_SCOPE__278 __VEC_SCOPE__
280 {279 {
281- AscendC::MicroAPI::RegTensor<T1> idxRegT;280+ AscendC::Reg::RegTensor<T1> idxRegT;
282- AscendC::MicroAPI::RegTensor<T> dstReg;281+ AscendC::Reg::RegTensor<T> dstReg;
283- AscendC::MicroAPI::MaskReg preg;282+ AscendC::Reg::MaskReg preg;
284 for (uint16_t j = 0; j < times; j++) {283 for (uint16_t j = 0; j < times; j++) {
285- preg = AscendC::MicroAPI::UpdateMask<T>(onceSize);284+ preg = AscendC::Reg::UpdateMask<T>(onceSize);
286- AscendC::MicroAPI::AddrReg srcIdxOffset = AscendC::MicroAPI::CreateAddrReg<T1>(j, vfLen);285+ AscendC::Reg::AddrReg srcIdxOffset = AscendC::Reg::CreateAddrReg<T1>(j, vfLen);
287- AscendC::MicroAPI::DataCopy(idxRegT, idxUbAddr, srcIdxOffset);286+ AscendC::Reg::DataCopy(idxRegT, idxUbAddr, srcIdxOffset);
288 DataCopyGather(dstReg, srcUbAddr, idxRegT, preg);287 DataCopyGather(dstReg, srcUbAddr, idxRegT, preg);
289- AscendC::MicroAPI::DataCopy(dstUbAddr, dstReg, srcIdxOffset, preg);288+ AscendC::Reg::DataCopy(dstUbAddr, dstReg, srcIdxOffset, preg);
290 }289 }
291 }290 }
292}291}
@@ -308,25 +307,24 @@ __aicore__ inline void ResizeGather<T, T1, schId, alignCorners>::ComputeHids(Loc
308 307 
309 __VEC_SCOPE__308 __VEC_SCOPE__
310 {309 {
311- AscendC::MicroAPI::RegTensor<int32_t> idxInt32Reg;310+ AscendC::Reg::RegTensor<int32_t> idxInt32Reg;
312- AscendC::MicroAPI::MaskReg pregB32 = AscendC::MicroAPI::UpdateMask<uint32_t>(numH);311+ AscendC::Reg::MaskReg pregB32 = AscendC::Reg::UpdateMask<uint32_t>(numH);
313- AscendC::MicroAPI::MaskReg pregRemainB32;312+ AscendC::Reg::MaskReg pregRemainB32;
314 Arange(idxInt32Reg, 0);313 Arange(idxInt32Reg, 0);
315 if constexpr (sizeof(T1) == sizeof(int32_t)) {314 if constexpr (sizeof(T1) == sizeof(int32_t)) {
316- DataCopy(idxUbAddr, (MicroAPI::RegTensor<T1>&)idxInt32Reg, pregB32);315+ DataCopy(idxUbAddr, (Reg::RegTensor<T1>&)idxInt32Reg, pregB32);
317 } else {316 } else {
318- DataCopy<T1, AscendC::MicroAPI::StoreDist::DIST_PACK_B32>(idxUbAddr, (MicroAPI::RegTensor<T1>&)idxInt32Reg,317+ DataCopy<T1, AscendC::Reg::StoreDist::DIST_PACK_B32>(idxUbAddr, (Reg::RegTensor<T1>&)idxInt32Reg, pregB32);
319- pregB32);
320 }318 }
321 for (uint16_t i = 0; i < times; i++) {319 for (uint16_t i = 0; i < times; i++) {
322- pregRemainB32 = AscendC::MicroAPI::UpdateMask<int32_t>(remainNum);320+ pregRemainB32 = AscendC::Reg::UpdateMask<int32_t>(remainNum);
323 Adds(idxInt32Reg, idxInt32Reg, 64, pregRemainB32);321 Adds(idxInt32Reg, idxInt32Reg, 64, pregRemainB32);
324- AscendC::MicroAPI::AddrReg dstOffset = AscendC::MicroAPI::CreateAddrReg<T1>(i, 64);322+ AscendC::Reg::AddrReg dstOffset = AscendC::Reg::CreateAddrReg<T1>(i, 64);
325 if constexpr (sizeof(T1) == sizeof(int32_t)) {323 if constexpr (sizeof(T1) == sizeof(int32_t)) {
326- DataCopy(idxUbRemainAddr, (MicroAPI::RegTensor<T1>&)idxInt32Reg, dstOffset, pregRemainB32);324+ DataCopy(idxUbRemainAddr, (Reg::RegTensor<T1>&)idxInt32Reg, dstOffset, pregRemainB32);
327 } else {325 } else {
328- DataCopy<T1, AscendC::MicroAPI::StoreDist::DIST_PACK_B32>(326+ DataCopy<T1, AscendC::Reg::StoreDist::DIST_PACK_B32>(idxUbRemainAddr, (Reg::RegTensor<T1>&)idxInt32Reg,
329- idxUbRemainAddr, (MicroAPI::RegTensor<T1>&)idxInt32Reg, dstOffset, pregRemainB32);327+ dstOffset, pregRemainB32);
330 }328 }
331 }329 }
332 }330 }
@@ -351,25 +349,25 @@ __aicore__ inline void ComputeHOrWids(LocalTensor<T1>& idxUb, float bias, float
351 remainNum = dstSize - vfLenb32;349 remainNum = dstSize - vfLenb32;
352 times = CeilDivision(remainNum, vfLenb32);350 times = CeilDivision(remainNum, vfLenb32);
353 }351 }
354- constexpr static AscendC::MicroAPI::CastTrait castTraitRound = {352+ constexpr static AscendC::Reg::CastTrait castTraitRound = {
355- AscendC::MicroAPI::RegLayout::UNKNOWN, AscendC::MicroAPI::SatMode::NO_SAT,353+ AscendC::Reg::RegLayout::UNKNOWN, AscendC::Reg::SatMode::NO_SAT, AscendC::Reg::MaskMergeMode::ZEROING,
356- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_ROUND};354+ AscendC::RoundMode::CAST_ROUND};
357- constexpr static AscendC::MicroAPI::CastTrait castTraitFloor = {355+ constexpr static AscendC::Reg::CastTrait castTraitFloor = {
358- AscendC::MicroAPI::RegLayout::UNKNOWN, AscendC::MicroAPI::SatMode::NO_SAT,356+ AscendC::Reg::RegLayout::UNKNOWN, AscendC::Reg::SatMode::NO_SAT, AscendC::Reg::MaskMergeMode::ZEROING,
359- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_FLOOR};357+ AscendC::RoundMode::CAST_FLOOR};
360- constexpr static AscendC::MicroAPI::CastTrait castInt32ToF = {358+ constexpr static AscendC::Reg::CastTrait castInt32ToF = {
361- AscendC::MicroAPI::RegLayout::UNKNOWN, AscendC::MicroAPI::SatMode::UNKNOWN,359+ AscendC::Reg::RegLayout::UNKNOWN, AscendC::Reg::SatMode::UNKNOWN, AscendC::Reg::MaskMergeMode::ZEROING,
362- AscendC::MicroAPI::MaskMergeMode::ZEROING, AscendC::RoundMode::CAST_FLOOR};360+ AscendC::RoundMode::CAST_FLOOR};
363 361 
364 __VEC_SCOPE__362 __VEC_SCOPE__
365 {363 {
366- AscendC::MicroAPI::RegTensor<float> idxInt32Reg;364+ AscendC::Reg::RegTensor<float> idxInt32Reg;
367- AscendC::MicroAPI::RegTensor<float> hIdxF;365+ AscendC::Reg::RegTensor<float> hIdxF;
368 366 
369- AscendC::MicroAPI::RegTensor<int32_t> hIdxInt32;367+ AscendC::Reg::RegTensor<int32_t> hIdxInt32;
370- AscendC::MicroAPI::RegTensor<int32_t> hIdxInt32C;368+ AscendC::Reg::RegTensor<int32_t> hIdxInt32C;
371- AscendC::MicroAPI::MaskReg pregB32 = AscendC::MicroAPI::UpdateMask<uint32_t>(oneTimeNum);369+ AscendC::Reg::MaskReg pregB32 = AscendC::Reg::UpdateMask<uint32_t>(oneTimeNum);
372- AscendC::MicroAPI::MaskReg pregRemainB32;370+ AscendC::Reg::MaskReg pregRemainB32;
373 Arange(idxInt32Reg, 0.0f);371 Arange(idxInt32Reg, 0.0f);
374 372 
375 Adds(hIdxF, idxInt32Reg, bias, pregB32);373 Adds(hIdxF, idxInt32Reg, bias, pregB32);
@@ -386,13 +384,12 @@ __aicore__ inline void ComputeHOrWids(LocalTensor<T1>& idxUb, float bias, float
386 Muls(hIdxInt32C, hIdxInt32C, srcW, pregB32);384 Muls(hIdxInt32C, hIdxInt32C, srcW, pregB32);
387 }385 }
388 if constexpr (sizeof(T1) == sizeof(int32_t)) {386 if constexpr (sizeof(T1) == sizeof(int32_t)) {
389- DataCopy(idxUbAddr, (MicroAPI::RegTensor<T1>&)hIdxInt32C, pregB32);387+ DataCopy(idxUbAddr, (Reg::RegTensor<T1>&)hIdxInt32C, pregB32);
390 } else {388 } else {
391- DataCopy<T1, AscendC::MicroAPI::StoreDist::DIST_PACK_B32>(idxUbAddr, (MicroAPI::RegTensor<T1>&)hIdxInt32C,389+ DataCopy<T1, AscendC::Reg::StoreDist::DIST_PACK_B32>(idxUbAddr, (Reg::RegTensor<T1>&)hIdxInt32C, pregB32);
392- pregB32);
393 }390 }
394 for (uint16_t i = 0; i < times; i++) {391 for (uint16_t i = 0; i < times; i++) {
395- pregRemainB32 = AscendC::MicroAPI::UpdateMask<int32_t>(remainNum);392+ pregRemainB32 = AscendC::Reg::UpdateMask<int32_t>(remainNum);
396 Adds(idxInt32Reg, idxInt32Reg, 64.0f, pregRemainB32);393 Adds(idxInt32Reg, idxInt32Reg, 64.0f, pregRemainB32);
397 Adds(hIdxF, idxInt32Reg, bias, pregRemainB32);394 Adds(hIdxF, idxInt32Reg, bias, pregRemainB32);
398 Muls(hIdxF, hIdxF, scale, pregRemainB32);395 Muls(hIdxF, hIdxF, scale, pregRemainB32);
@@ -405,12 +402,12 @@ __aicore__ inline void ComputeHOrWids(LocalTensor<T1>& idxUb, float bias, float
405 if constexpr (isH) {402 if constexpr (isH) {
406 Muls(hIdxInt32C, hIdxInt32C, srcW, pregRemainB32);403 Muls(hIdxInt32C, hIdxInt32C, srcW, pregRemainB32);
407 }404 }
408- AscendC::MicroAPI::AddrReg dstOffset = AscendC::MicroAPI::CreateAddrReg<T1>(i, 64);405+ AscendC::Reg::AddrReg dstOffset = AscendC::Reg::CreateAddrReg<T1>(i, 64);
409 if constexpr (sizeof(T1) == sizeof(int32_t)) {406 if constexpr (sizeof(T1) == sizeof(int32_t)) {
410- DataCopy(idxUbRemainAddr, (MicroAPI::RegTensor<T1>&)hIdxInt32C, dstOffset, pregRemainB32);407+ DataCopy(idxUbRemainAddr, (Reg::RegTensor<T1>&)hIdxInt32C, dstOffset, pregRemainB32);
411 } else {408 } else {
412- DataCopy<T1, AscendC::MicroAPI::StoreDist::DIST_PACK_B32>(409+ DataCopy<T1, AscendC::Reg::StoreDist::DIST_PACK_B32>(idxUbRemainAddr, (Reg::RegTensor<T1>&)hIdxInt32C,
413- idxUbRemainAddr, (MicroAPI::RegTensor<T1>&)hIdxInt32C, dstOffset, pregRemainB32);410+ dstOffset, pregRemainB32);
414 }411 }
415 }412 }
416 }413 }
@@ -436,22 +433,22 @@ __aicore__ inline void ResizeGather<T, T1, schId, alignCorners>::ComputeOriHIdx(
436 int64_t hiStartData = hiStart;433 int64_t hiStartData = hiStart;
437 __VEC_SCOPE__434 __VEC_SCOPE__
438 {435 {
439- AscendC::MicroAPI::RegTensor<int32_t> hiStartReg;436+ AscendC::Reg::RegTensor<int32_t> hiStartReg;
440- AscendC::MicroAPI::RegTensor<int32_t> idxInt32Reg;437+ AscendC::Reg::RegTensor<int32_t> idxInt32Reg;
441- AscendC::MicroAPI::RegTensor<float> hIdxF;438+ AscendC::Reg::RegTensor<float> hIdxF;
442- AscendC::MicroAPI::RegTensor<int32_t> idxInt32OriReg;439+ AscendC::Reg::RegTensor<int32_t> idxInt32OriReg;
443- AscendC::MicroAPI::RegTensor<int32_t> idxInt32OriWReg;440+ AscendC::Reg::RegTensor<int32_t> idxInt32OriWReg;
444- AscendC::MicroAPI::MaskReg preg;441+ AscendC::Reg::MaskReg preg;
445 Duplicate<int32_t>(hiStartReg, hiStartData);442 Duplicate<int32_t>(hiStartReg, hiStartData);
446 443 
447 for (uint16_t i = 0; i < hTimes; i++) {444 for (uint16_t i = 0; i < hTimes; i++) {
448- preg = AscendC::MicroAPI::UpdateMask<int32_t>(size);445+ preg = AscendC::Reg::UpdateMask<int32_t>(size);
449- AscendC::MicroAPI::AddrReg srcIdxOffset = AscendC::MicroAPI::CreateAddrReg<T1>(i, vfLenB32);446+ AscendC::Reg::AddrReg srcIdxOffset = AscendC::Reg::CreateAddrReg<T1>(i, vfLenB32);
450 if constexpr (sizeof(T1) == sizeof(int32_t)) {447 if constexpr (sizeof(T1) == sizeof(int32_t)) {
451- DataCopy((MicroAPI::RegTensor<T1>&)idxInt32Reg, idxHubAddr, srcIdxOffset);448+ DataCopy((Reg::RegTensor<T1>&)idxInt32Reg, idxHubAddr, srcIdxOffset);
452 } else {449 } else {
453- DataCopy<T1, MicroAPI::LoadDist::DIST_UNPACK_B16>((MicroAPI::RegTensor<T1>&)idxInt32Reg, idxHubAddr,450+ DataCopy<T1, Reg::LoadDist::DIST_UNPACK_B16>((Reg::RegTensor<T1>&)idxInt32Reg, idxHubAddr,
454- srcIdxOffset);451+ srcIdxOffset);
455 }452 }
456 //453 //
457 Adds(idxInt32Reg, idxInt32Reg, hoStartData, preg); // 输出位置454 Adds(idxInt32Reg, idxInt32Reg, hoStartData, preg); // 输出位置
@@ -468,10 +465,10 @@ __aicore__ inline void ResizeGather<T, T1, schId, alignCorners>::ComputeOriHIdx(
468 Sub(idxInt32OriReg, idxInt32OriReg, hiStartReg, preg);465 Sub(idxInt32OriReg, idxInt32OriReg, hiStartReg, preg);
469 Muls(idxInt32OriWReg, idxInt32OriReg, wSize, preg);466 Muls(idxInt32OriWReg, idxInt32OriReg, wSize, preg);
470 if constexpr (sizeof(T1) == sizeof(int32_t)) {467 if constexpr (sizeof(T1) == sizeof(int32_t)) {
471- DataCopy(idxH1UbAddr, (MicroAPI::RegTensor<T1>&)idxInt32OriWReg, srcIdxOffset, preg);468+ DataCopy(idxH1UbAddr, (Reg::RegTensor<T1>&)idxInt32OriWReg, srcIdxOffset, preg);
472 } else {469 } else {
473- DataCopy<T1, AscendC::MicroAPI::StoreDist::DIST_PACK_B32>(470+ DataCopy<T1, AscendC::Reg::StoreDist::DIST_PACK_B32>(idxH1UbAddr, (Reg::RegTensor<T1>&)idxInt32OriWReg,
474- idxH1UbAddr, (MicroAPI::RegTensor<T1>&)idxInt32OriWReg, srcIdxOffset, preg);471+ srcIdxOffset, preg);
475 }472 }
476 }473 }
477 }474 }
@@ -501,17 +498,17 @@ __aicore__ inline void ResizeGather<T, T1, schId, alignCorners>::ComputeOriHWidx
501 498 
502 __VEC_SCOPE__499 __VEC_SCOPE__
503 {500 {
504- AscendC::MicroAPI::RegTensor<T1> idxWReg;501+ AscendC::Reg::RegTensor<T1> idxWReg;
505- AscendC::MicroAPI::RegTensor<T1> addsReg;502+ AscendC::Reg::RegTensor<T1> addsReg;
506- AscendC::MicroAPI::MaskReg preg = AscendC::MicroAPI::UpdateMask<T1>(tail);503+ AscendC::Reg::MaskReg preg = AscendC::Reg::UpdateMask<T1>(tail);
507- AscendC::MicroAPI::MaskReg pregB32 = AscendC::MicroAPI::CreateMask<T1, AscendC::MicroAPI::MaskPattern::ALL>();504+ AscendC::Reg::MaskReg pregB32 = AscendC::Reg::CreateMask<T1, AscendC::Reg::MaskPattern::ALL>();
508 505 
509 for (uint16_t i = 0; i < onceHTimes; i++) {506 for (uint16_t i = 0; i < onceHTimes; i++) {
510 T1 hIdx = idxH1Ub.GetValue(i);507 T1 hIdx = idxH1Ub.GetValue(i);
511- AscendC::MicroAPI::AddrReg outIdxOffset1 = AscendC::MicroAPI::CreateAddrReg<T1>(i, dstWSize);508+ AscendC::Reg::AddrReg outIdxOffset1 = AscendC::Reg::CreateAddrReg<T1>(i, dstWSize);
512 for (uint16_t j = 0; j < static_cast<uint16_t>(wTimes); j++) {509 for (uint16_t j = 0; j < static_cast<uint16_t>(wTimes); j++) {
513- AscendC::MicroAPI::AddrReg srcIdxOffset = AscendC::MicroAPI::CreateAddrReg<T1>(j, vfLen);510+ AscendC::Reg::AddrReg srcIdxOffset = AscendC::Reg::CreateAddrReg<T1>(j, vfLen);
514- AscendC::MicroAPI::AddrReg outIdxOffset = AscendC::MicroAPI::CreateAddrReg<T1>(i, dstWSize, j, vfLen);511+ AscendC::Reg::AddrReg outIdxOffset = AscendC::Reg::CreateAddrReg<T1>(i, dstWSize, j, vfLen);
515 DataCopy(idxWReg, idxWubAddr, srcIdxOffset);512 DataCopy(idxWReg, idxWubAddr, srcIdxOffset);
516 Adds(addsReg, idxWReg, hIdx, pregB32);513 Adds(addsReg, idxWReg, hIdx, pregB32);
517 DataCopy(idxHwUbAddr, addsReg, outIdxOffset, pregB32);514 DataCopy(idxHwUbAddr, addsReg, outIdxOffset, pregB32);
@@ -590,21 +587,21 @@ __aicore__ inline void ResizeGather<T, T1, schId, alignCorners>::ComputeHWids(Lo
590 uint32_t wAlign = dstWSizeAlgin;587 uint32_t wAlign = dstWSizeAlgin;
591 __VEC_SCOPE__588 __VEC_SCOPE__
592 {589 {
593- AscendC::MicroAPI::RegTensor<T1> wIdxReg;590+ AscendC::Reg::RegTensor<T1> wIdxReg;
594- AscendC::MicroAPI::RegTensor<T1> idxReg;591+ AscendC::Reg::RegTensor<T1> idxReg;
595 592 
596- AscendC::MicroAPI::RegTensor<int32_t> hIdxInt32;593+ AscendC::Reg::RegTensor<int32_t> hIdxInt32;
597- AscendC::MicroAPI::RegTensor<int32_t> hIdxInt32C;594+ AscendC::Reg::RegTensor<int32_t> hIdxInt32C;
598- AscendC::MicroAPI::MaskReg pregB32 = AscendC::MicroAPI::CreateMask<T1, AscendC::MicroAPI::MaskPattern::ALL>();595+ AscendC::Reg::MaskReg pregB32 = AscendC::Reg::CreateMask<T1, AscendC::Reg::MaskPattern::ALL>();
599- AscendC::MicroAPI::MaskReg pregTail = AscendC::MicroAPI::UpdateMask<T1>(tail);596+ AscendC::Reg::MaskReg pregTail = AscendC::Reg::UpdateMask<T1>(tail);
600 for (uint16_t i = 0; i < static_cast<uint16_t>(hSize); i++) {597 for (uint16_t i = 0; i < static_cast<uint16_t>(hSize); i++) {
601 T1 hIdx = idxHUb.GetValue(i);598 T1 hIdx = idxHUb.GetValue(i);
602- AscendC::MicroAPI::AddrReg outIdxOffset = AscendC::MicroAPI::CreateAddrReg<T1>(i, wAlign);599+ AscendC::Reg::AddrReg outIdxOffset = AscendC::Reg::CreateAddrReg<T1>(i, wAlign);
603 for (uint16_t j = 0; j < static_cast<uint16_t>(wTimes); j++) {600 for (uint16_t j = 0; j < static_cast<uint16_t>(wTimes); j++) {
604- AscendC::MicroAPI::AddrReg srcIdxOffset = AscendC::MicroAPI::CreateAddrReg<T1>(j, vfLen);601+ AscendC::Reg::AddrReg srcIdxOffset = AscendC::Reg::CreateAddrReg<T1>(j, vfLen);
605 DataCopy(wIdxReg, idxWUbAddr, srcIdxOffset);602 DataCopy(wIdxReg, idxWUbAddr, srcIdxOffset);
606 Adds(idxReg, wIdxReg, hIdx, pregB32);603 Adds(idxReg, wIdxReg, hIdx, pregB32);
607- AscendC::MicroAPI::AddrReg srcOutOffset = AscendC::MicroAPI::CreateAddrReg<T1>(i, wAlign, j, vfLen);604+ AscendC::Reg::AddrReg srcOutOffset = AscendC::Reg::CreateAddrReg<T1>(i, wAlign, j, vfLen);
608 DataCopy(idxUbAddr, idxReg, srcOutOffset, pregB32);605 DataCopy(idxUbAddr, idxReg, srcOutOffset, pregB32);
609 }606 }
610 for (uint16_t jj = 0; jj < tailTimes; jj++) {607 for (uint16_t jj = 0; jj < tailTimes; jj++) {