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refactor: 迁移 arch35 算子 Reg API、修正拼写并规范化日志文案 #5135
esok11创建于 4 天前
refactor: 迁移 arch35 算子 Reg API、修正拼写并规范化日志文案 #5135
已合并
esok11创建于 4 天前
从esok11/ops-mathf082601合入到cann/ops-mathmaster
共 45 个文件变更+1196-1207
Mconversion/broadcast_to/examples/test_geir_broadcast_to.cpp+3-3
@@ -232,7 +232,7 @@ int main(int argc, char* argv[])
232 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};232 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
233 Status ret = ge::GEInitialize(global_options);233 Status ret = ge::GEInitialize(global_options);
234 if (ret != SUCCESS) {234 if (ret != SUCCESS) {
235- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());235+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
236 return FAILED;236 return FAILED;
237 }237 }
238 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());238 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -283,7 +283,7 @@ int main(int argc, char* argv[])
283 std::vector<ge::Tensor> output;283 std::vector<ge::Tensor> output;
284 ret = session->RunGraph(graph_id, input, output);284 ret = session->RunGraph(graph_id, input, output);
285 if (ret != SUCCESS) {285 if (ret != SUCCESS) {
286- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());286+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
287 delete session;287 delete session;
288 GEFinalize();288 GEFinalize();
289 return FAILED;289 return FAILED;
@@ -301,7 +301,7 @@ int main(int argc, char* argv[])
301 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());301 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
302 ret = ge::GEFinalize();302 ret = ge::GEFinalize();
303 if (ret != SUCCESS) {303 if (ret != SUCCESS) {
304- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());304+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
305 return FAILED;305 return FAILED;
306 }306 }
307 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());307 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mconversion/broadcast_to/op_host/arch35/broadcast_to_tiling_base.cpp+3-3
@@ -217,7 +217,7 @@ ge::graphStatus GetShapeInfo(const gert::TilingContext* context, gert::Shape& in
217 OP_LOGE_FOR_INVALID_SHAPES_WITH_REASON(context->GetNodeName(), "x and y", shapeMsg.c_str(), reasonMsg.c_str());217 OP_LOGE_FOR_INVALID_SHAPES_WITH_REASON(context->GetNodeName(), "x and y", shapeMsg.c_str(), reasonMsg.c_str());
218 return ge::GRAPH_FAILED;218 return ge::GRAPH_FAILED;
219 }219 }
220- OP_LOGI(context->GetNodeName(), "The input and output is: %s and %s", Shape2String(inShape).c_str(),220+ OP_LOGI(context->GetNodeName(), "The input and output are: %s and %s", Shape2String(inShape).c_str(),
221 Shape2String(outShape).c_str());221 Shape2String(outShape).c_str());
222 222 
223 if (DeleteOneSizeAxis(context, inShape, outShape) != ge::GRAPH_SUCCESS) {223 if (DeleteOneSizeAxis(context, inShape, outShape) != ge::GRAPH_SUCCESS) {
@@ -226,7 +226,7 @@ ge::graphStatus GetShapeInfo(const gert::TilingContext* context, gert::Shape& in
226 OP_LOGE_FOR_INVALID_SHAPES_WITH_REASON(context->GetNodeName(), "x and y", shapeMsg.c_str(), reasonMsg.c_str());226 OP_LOGE_FOR_INVALID_SHAPES_WITH_REASON(context->GetNodeName(), "x and y", shapeMsg.c_str(), reasonMsg.c_str());
227 return ge::GRAPH_FAILED;227 return ge::GRAPH_FAILED;
228 }228 }
229- OP_LOGI(context->GetNodeName(), "The reshaped input and output is: %s and %s", Shape2String(inShape).c_str(),229+ OP_LOGI(context->GetNodeName(), "The reshaped input and output are: %s and %s", Shape2String(inShape).c_str(),
230 Shape2String(outShape).c_str());230 Shape2String(outShape).c_str());
231 231 
232 if (MergeAxis(context, inShape, outShape) != ge::GRAPH_SUCCESS) {232 if (MergeAxis(context, inShape, outShape) != ge::GRAPH_SUCCESS) {
@@ -235,7 +235,7 @@ ge::graphStatus GetShapeInfo(const gert::TilingContext* context, gert::Shape& in
235 OP_LOGE_FOR_INVALID_SHAPES_WITH_REASON(context->GetNodeName(), "x and y", shapeMsg.c_str(), reasonMsg.c_str());235 OP_LOGE_FOR_INVALID_SHAPES_WITH_REASON(context->GetNodeName(), "x and y", shapeMsg.c_str(), reasonMsg.c_str());
236 return ge::GRAPH_FAILED;236 return ge::GRAPH_FAILED;
237 }237 }
238- OP_LOGI(context->GetNodeName(), "The merged input and output is: %s and %s", Shape2String(inShape).c_str(),238+ OP_LOGI(context->GetNodeName(), "The merged input and output are: %s and %s", Shape2String(inShape).c_str(),
239 Shape2String(outShape).c_str());239 Shape2String(outShape).c_str());
240 240 
241 return ge::GRAPH_SUCCESS;241 return ge::GRAPH_SUCCESS;
Mconversion/broadcast_to/op_kernel/arch35/broadcast_to_with_dma.h+3-3
@@ -24,7 +24,7 @@ using namespace AscendC;
24 24 
25constexpr uint8_t bufferNum = 1;25constexpr uint8_t bufferNum = 1;
26constexpr int32_t queDepth = 1;26constexpr int32_t queDepth = 1;
27-constexpr MultiCopyConfig copyCfg{false, 0, 0, false};27+constexpr NdDmaConfig copyCfg{false, 0, 0, false};
28 28 
29template <typename T, typename U, uint8_t maxDim = 4>29template <typename T, typename U, uint8_t maxDim = 4>
30class BrcToWithNDDMA : public BrcToBase<U> {30class BrcToWithNDDMA : public BrcToBase<U> {
@@ -53,8 +53,8 @@ private:
53 int64_t gmOutOffset;53 int64_t gmOutOffset;
54 int64_t inBlockOffset = 0;54 int64_t inBlockOffset = 0;
55 int64_t outBlockOffset = 0;55 int64_t outBlockOffset = 0;
56- AscendC::MultiCopyLoopInfo<maxDim> copyLpInfo;56+ AscendC::NdDmaLoopInfo<maxDim> copyLpInfo;
57- AscendC::MultiCopyParams<T, maxDim> mCopyParams;57+ AscendC::NdDmaParams<T, maxDim> mCopyParams;
58 AscendC::DataCopyExtParams copyParams{1, 0, 0, 0, 0};58 AscendC::DataCopyExtParams copyParams{1, 0, 0, 0, 0};
59 uint32_t outLen = sizeof(T);59 uint32_t outLen = sizeof(T);
60 uint8_t copySwitch = 1; // to avoid repeat copy in for U is broadcast axis60 uint8_t copySwitch = 1; // to avoid repeat copy in for U is broadcast axis
Mconversion/broadcast_to/op_kernel/arch35/broadcast_to_with_single_axis.h+1-1
@@ -28,7 +28,7 @@
28namespace BrcSA {28namespace BrcSA {
29using namespace AscendC;29using namespace AscendC;
30 30 
31-constexpr MultiCopyConfig copyCfg{false, 0, 0, false};31+constexpr NdDmaConfig copyCfg{false, 0, 0, false};
32 32 
33template <typename T, bool IsBrc>33template <typename T, bool IsBrc>
34class BroadcastSingleAxis {34class BroadcastSingleAxis {
Mconversion/broadcast_to/op_kernel/arch35/broadcast_to_with_tailAxis.h+6-7
@@ -23,7 +23,6 @@ namespace BrcTo {
23using namespace AscendC;23using namespace AscendC;
24 24 
25using AscendC::Reg::CreateMask;25using AscendC::Reg::CreateMask;
26-using AscendC::Reg::DataCopy;
27using AscendC::Reg::MaskReg;26using AscendC::Reg::MaskReg;
28using AscendC::Reg::RegTensor;27using AscendC::Reg::RegTensor;
29using AscendC::Reg::UpdateMask;28using AscendC::Reg::UpdateMask;
@@ -176,8 +175,8 @@ template <typename T, typename U>
176__aicore__ inline void BrcToWithTailAxis<T, U>::VFBrcTo(LocalTensor<T> outTensor, LocalTensor<T> inTensor,175__aicore__ inline void BrcToWithTailAxis<T, U>::VFBrcTo(LocalTensor<T> outTensor, LocalTensor<T> inTensor,
177 int64_t inputOffset, int64_t elemIdx, uint32_t brcCnt)176 int64_t inputOffset, int64_t elemIdx, uint32_t brcCnt)
178{177{
179- __local_mem__ T* inputAddr = (__local_mem__ T*)inTensor.GetPhyAddr();178+ __ubuf__ T* inputAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
180- __local_mem__ T* outputAddr = (__local_mem__ T*)outTensor.GetPhyAddr();179+ __ubuf__ T* outputAddr = (__ubuf__ T*)outTensor.GetPhyAddr();
181 180 
182 uint32_t VL_CNT = Ops::Base::GetVRegSize() / sizeof(T);181 uint32_t VL_CNT = Ops::Base::GetVRegSize() / sizeof(T);
183 uint16_t brcLoopCnt = Ops::Base::CeilDiv(brcCnt, VL_CNT);182 uint16_t brcLoopCnt = Ops::Base::CeilDiv(brcCnt, VL_CNT);
@@ -195,17 +194,17 @@ __aicore__ inline void BrcToWithTailAxis<T, U>::VFBrcTo(LocalTensor<T> outTensor
195 MaskReg pregGather;194 MaskReg pregGather;
196 MaskReg pregLoopB;195 MaskReg pregLoopB;
197 196 
198- DataCopy(tmpIn, inputAddr + inputOffset);197+ Reg::LoadAlign(tmpIn, inputAddr + inputOffset);
199 uint32_t sregTmp = uint32_t(elemIdx * sizeof(T));198 uint32_t sregTmp = uint32_t(elemIdx * sizeof(T));
200 pregTmp = UpdateMask<uint8_t>(sregTmp);199 pregTmp = UpdateMask<uint8_t>(sregTmp);
201- AscendC::Reg::MaskSel(pregGather, pregAllFB8, pregAllB8, pregTmp);200+ AscendC::Reg::Select(pregGather, pregAllFB8, pregAllB8, pregTmp);
202- GatherMask((Reg::RegTensor<uint8_t>&)tmpOut, (Reg::RegTensor<uint8_t>&)tmpIn, pregGather);201+ AscendC::Reg::Squeeze((Reg::RegTensor<uint8_t>&)tmpOut, (Reg::RegTensor<uint8_t>&)tmpIn, pregGather);
203 Duplicate(tmpOut, tmpOut, pregAll);202 Duplicate(tmpOut, tmpOut, pregAll);
204 203 
205 uint32_t sregB = brcCnt;204 uint32_t sregB = brcCnt;
206 for (uint16_t vIdx = 0; vIdx < brcLoopCnt; vIdx++) {205 for (uint16_t vIdx = 0; vIdx < brcLoopCnt; vIdx++) {
207 pregLoopB = AscendC::Reg::UpdateMask<T>(sregB);206 pregLoopB = AscendC::Reg::UpdateMask<T>(sregB);
208- AscendC::Reg::DataCopy(outputAddr + outputOffset, tmpOut, pregLoopB);207+ AscendC::Reg::StoreAlign(outputAddr + outputOffset, tmpOut, pregLoopB);
209 outputOffset += VL_CNT;208 outputOffset += VL_CNT;
210 }209 }
211 }210 }
Mconversion/broadcast_to/op_kernel/arch35/broadcast_to_with_ub.h+46-47
@@ -25,7 +25,6 @@ namespace BrcTo {
25using namespace AscendC;25using namespace AscendC;
26 26 
27using AscendC::Reg::CreateMask;27using AscendC::Reg::CreateMask;
28-using AscendC::Reg::DataCopy;
29using AscendC::Reg::MaskReg;28using AscendC::Reg::MaskReg;
30using AscendC::Reg::RegTensor;29using AscendC::Reg::RegTensor;
31using AscendC::Reg::UpdateMask;30using AscendC::Reg::UpdateMask;
@@ -49,9 +48,9 @@ private:
49 __aicore__ inline void CalcInnerShape();48 __aicore__ inline void CalcInnerShape();
50 __aicore__ inline void SetOutputParams(uint32_t uLen);49 __aicore__ inline void SetOutputParams(uint32_t uLen);
51 __aicore__ inline void SetInputParams(uint32_t uLen);50 __aicore__ inline void SetInputParams(uint32_t uLen);
52- __aicore__ inline void VFBroadcastOneElemLB(__local_mem__ T* inputAddr, __local_mem__ T* outputAddr);51+ __aicore__ inline void VFBroadcastOneElemLB(__ubuf__ T* inputAddr, __ubuf__ T* outputAddr);
53- __aicore__ inline void VFBroadcastOneElemLBB64(__local_mem__ T* inputAddr, __local_mem__ T* outputAddr);52+ __aicore__ inline void VFBroadcastOneElemLBB64(__ubuf__ T* inputAddr, __ubuf__ T* outputAddr);
54- __aicore__ inline void VFBroadcastOneElemOB(__local_mem__ T* outputAddr);53+ __aicore__ inline void VFBroadcastOneElemOB(__ubuf__ T* outputAddr);
55 __aicore__ inline void VFInnerBroadcastToB(LocalTensor<T>& outputTensor, LocalTensor<T>& inputTensor);54 __aicore__ inline void VFInnerBroadcastToB(LocalTensor<T>& outputTensor, LocalTensor<T>& inputTensor);
56 __aicore__ inline void VFInnerBroadcastToA(LocalTensor<T>& outputTensor, LocalTensor<T>& inputTensor);55 __aicore__ inline void VFInnerBroadcastToA(LocalTensor<T>& outputTensor, LocalTensor<T>& inputTensor);
57 __aicore__ inline void VFInnerBrcLastDimLEBlock(LocalTensor<T>& outputTensor, LocalTensor<T>& inputTensor);56 __aicore__ inline void VFInnerBrcLastDimLEBlock(LocalTensor<T>& outputTensor, LocalTensor<T>& inputTensor);
@@ -153,8 +152,8 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::SetInputParams(uint3
153}152}
154 153 
155template <typename T, typename U, bool isLastDimSmall>154template <typename T, typename U, bool isLastDimSmall>
156-__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemLB(__local_mem__ T* inputAddr,155+__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemLB(__ubuf__ T* inputAddr,
157- __local_mem__ T* outputAddr)156+ __ubuf__ T* outputAddr)
158{157{
159 uint32_t axis3OutOffset = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt);158 uint32_t axis3OutOffset = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt);
160 uint32_t axis1OutOffset = innerAxis2 * innerAxis3 * axis3OutOffset;159 uint32_t axis1OutOffset = innerAxis2 * innerAxis3 * axis3OutOffset;
@@ -172,15 +171,15 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemLB
172 for (uint16_t axis3Idx = 0; axis3Idx < static_cast<uint16_t>(innerAxis3); axis3Idx++) {171 for (uint16_t axis3Idx = 0; axis3Idx < static_cast<uint16_t>(innerAxis3); axis3Idx++) {
173 auto aregI = Reg::CreateAddrReg<T>(axis1Idx, innerAxis3, axis3Idx, 1);172 auto aregI = Reg::CreateAddrReg<T>(axis1Idx, innerAxis3, axis3Idx, 1);
174 if constexpr (sizeof(T) == sizeof(uint8_t)) {173 if constexpr (sizeof(T) == sizeof(uint8_t)) {
175- DataCopy<T, Reg::LoadDist::DIST_BRC_B8>(tmpIn, inputAddr, aregI);174+ Reg::LoadAlign<T, Reg::LoadDist::DIST_BRC_B8>(tmpIn, inputAddr, aregI);
176 } else if constexpr (sizeof(T) == sizeof(uint16_t)) {175 } else if constexpr (sizeof(T) == sizeof(uint16_t)) {
177- DataCopy<T, Reg::LoadDist::DIST_BRC_B16>(tmpIn, inputAddr, aregI);176+ Reg::LoadAlign<T, Reg::LoadDist::DIST_BRC_B16>(tmpIn, inputAddr, aregI);
178 } else {177 } else {
179- DataCopy<T, Reg::LoadDist::DIST_BRC_B32>(tmpIn, inputAddr, aregI);178+ Reg::LoadAlign<T, Reg::LoadDist::DIST_BRC_B32>(tmpIn, inputAddr, aregI);
180 }179 }
181 auto aregO = Reg::CreateAddrReg<T>(axis4LpIdx, axis4Offset, axis1Idx, axis1OutOffset, axis3Idx,180 auto aregO = Reg::CreateAddrReg<T>(axis4LpIdx, axis4Offset, axis1Idx, axis1OutOffset, axis3Idx,
182 axis3OutOffset);181 axis3OutOffset);
183- DataCopy(outputAddr, tmpIn, aregO, mask);182+ Reg::StoreAlign(outputAddr, tmpIn, aregO, mask);
184 }183 }
185 }184 }
186 }185 }
@@ -188,8 +187,8 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemLB
188}187}
189 188 
190template <typename T, typename U, bool isLastDimSmall>189template <typename T, typename U, bool isLastDimSmall>
191-__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemLBB64(__local_mem__ T* inputAddr,190+__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemLBB64(__ubuf__ T* inputAddr,
192- __local_mem__ T* outputAddr)191+ __ubuf__ T* outputAddr)
193{192{
194 uint32_t axis1InOffset = innerAxis3 * nTwo;193 uint32_t axis1InOffset = innerAxis3 * nTwo;
195 uint32_t axis3OutOffset = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt) * nTwo;194 uint32_t axis3OutOffset = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt) * nTwo;
@@ -197,8 +196,8 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemLB
197 uint16_t axis4LpCnt = Ops::Base::CeilDiv(innerAxis4, VL_CNT);196 uint16_t axis4LpCnt = Ops::Base::CeilDiv(innerAxis4, VL_CNT);
198 uint16_t axis4Offset = VL_CNT * nTwo;197 uint16_t axis4Offset = VL_CNT * nTwo;
199 uint32_t maskValue = axis3OutOffset;198 uint32_t maskValue = axis3OutOffset;
200- auto reInAddr = reinterpret_cast<__local_mem__ RT*>(inputAddr);199+ auto reInAddr = reinterpret_cast<__ubuf__ RT*>(inputAddr);
201- auto reOutAddr = reinterpret_cast<__local_mem__ RT*>(outputAddr);200+ auto reOutAddr = reinterpret_cast<__ubuf__ RT*>(outputAddr);
202 201 
203 __VEC_SCOPE__202 __VEC_SCOPE__
204 {203 {
@@ -212,12 +211,12 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemLB
212 for (uint16_t axis1Idx = 0; axis1Idx < static_cast<uint16_t>(innerAxis1); axis1Idx++) {211 for (uint16_t axis1Idx = 0; axis1Idx < static_cast<uint16_t>(innerAxis1); axis1Idx++) {
213 for (uint16_t axis3Idx = 0; axis3Idx < static_cast<uint16_t>(innerAxis3); axis3Idx++) {212 for (uint16_t axis3Idx = 0; axis3Idx < static_cast<uint16_t>(innerAxis3); axis3Idx++) {
214 auto regI = Reg::CreateAddrReg<RT>(axis1Idx, axis1InOffset, axis3Idx, nTwo);213 auto regI = Reg::CreateAddrReg<RT>(axis1Idx, axis1InOffset, axis3Idx, nTwo);
215- DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn, reInAddr, regI);214+ Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn, reInAddr, regI);
216- DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn1, reInAddr + 1, regI);215+ Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn1, reInAddr + 1, regI);
217 Reg::Interleave(tmpOut, tmpOut1, tmpIn, tmpIn1);216 Reg::Interleave(tmpOut, tmpOut1, tmpIn, tmpIn1);
218 auto aregO = Reg::CreateAddrReg<RT>(axis4LpIdx, axis4Offset, axis1Idx, axis1OutOffset, axis3Idx,217 auto aregO = Reg::CreateAddrReg<RT>(axis4LpIdx, axis4Offset, axis1Idx, axis1OutOffset, axis3Idx,
219 axis3OutOffset);218 axis3OutOffset);
220- DataCopy(reOutAddr, tmpOut, aregO, mask);219+ Reg::StoreAlign(reOutAddr, tmpOut, aregO, mask);
221 }220 }
222 }221 }
223 }222 }
@@ -225,7 +224,7 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemLB
225}224}
226 225 
227template <typename T, typename U, bool isLastDimSmall>226template <typename T, typename U, bool isLastDimSmall>
228-__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemOB(__local_mem__ T* outputAddr)227+__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemOB(__ubuf__ T* outputAddr)
229{228{
230 uint32_t axis4BA = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt);229 uint32_t axis4BA = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt);
231 uint32_t axis2Offset = innerAxis3 * axis4BA;230 uint32_t axis2Offset = innerAxis3 * axis4BA;
@@ -238,7 +237,7 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemOB
238 iAxis34Size *= nTwo;237 iAxis34Size *= nTwo;
239 }238 }
240 uint32_t axis1OutOffset = innerAxis2 * axis2Offset;239 uint32_t axis1OutOffset = innerAxis2 * axis2Offset;
241- auto reOutAddr = reinterpret_cast<__local_mem__ RT*>(outputAddr);240+ auto reOutAddr = reinterpret_cast<__ubuf__ RT*>(outputAddr);
242 // ABA241 // ABA
243 __VEC_SCOPE__242 __VEC_SCOPE__
244 {243 {
@@ -247,11 +246,11 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFBroadcastOneElemOB
247 MaskReg mask = UpdateMask<RT>(iAxis34Size);246 MaskReg mask = UpdateMask<RT>(iAxis34Size);
248 for (uint16_t axis1Idx = 0; axis1Idx < static_cast<uint16_t>(innerAxis1); axis1Idx++) {247 for (uint16_t axis1Idx = 0; axis1Idx < static_cast<uint16_t>(innerAxis1); axis1Idx++) {
249 auto aregI = Reg::CreateAddrReg<RT>(axis34LpIdx, axis34Offset, axis1Idx, axis1OutOffset);248 auto aregI = Reg::CreateAddrReg<RT>(axis34LpIdx, axis34Offset, axis1Idx, axis1OutOffset);
250- DataCopy(tmpIn, reOutAddr, aregI);249+ Reg::LoadAlign(tmpIn, reOutAddr, aregI);
251 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2 - 1); axis2Idx++) {250 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2 - 1); axis2Idx++) {
252 auto aregO = Reg::CreateAddrReg<RT>(axis34LpIdx, axis34Offset, axis1Idx, axis1OutOffset, axis2Idx,251 auto aregO = Reg::CreateAddrReg<RT>(axis34LpIdx, axis34Offset, axis1Idx, axis1OutOffset, axis2Idx,
253 axis2Offset);252 axis2Offset);
254- DataCopy(reOutAddr + axis2Offset, tmpIn, aregO, mask);253+ Reg::StoreAlign(reOutAddr + axis2Offset, tmpIn, aregO, mask);
255 }254 }
256 }255 }
257 }256 }
@@ -262,8 +261,8 @@ template <typename T, typename U, bool isLastDimSmall>
262__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBroadcastToB(LocalTensor<T>& outputTensor,261__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBroadcastToB(LocalTensor<T>& outputTensor,
263 LocalTensor<T>& inputTensor)262 LocalTensor<T>& inputTensor)
264{263{
265- __local_mem__ T* inputAddr = (__local_mem__ T*)inputTensor.GetPhyAddr();264+ __ubuf__ T* inputAddr = (__ubuf__ T*)inputTensor.GetPhyAddr();
266- __local_mem__ T* outputAddr = (__local_mem__ T*)outputTensor.GetPhyAddr();265+ __ubuf__ T* outputAddr = (__ubuf__ T*)outputTensor.GetPhyAddr();
267 266 
268 if constexpr (sizeof(T) == sizeof(RT)) {267 if constexpr (sizeof(T) == sizeof(RT)) {
269 VFBroadcastOneElemLB(inputAddr, outputAddr);268 VFBroadcastOneElemLB(inputAddr, outputAddr);
@@ -281,10 +280,10 @@ template <typename T, typename U, bool isLastDimSmall>
281__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBroadcastToA(LocalTensor<T>& outputTensor,280__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBroadcastToA(LocalTensor<T>& outputTensor,
282 LocalTensor<T>& inputTensor)281 LocalTensor<T>& inputTensor)
283{282{
284- __local_mem__ T* inputAddr = (__local_mem__ T*)inputTensor.GetPhyAddr();283+ __ubuf__ T* inputAddr = (__ubuf__ T*)inputTensor.GetPhyAddr();
285- __local_mem__ T* outputAddr = (__local_mem__ T*)outputTensor.GetPhyAddr();284+ __ubuf__ T* outputAddr = (__ubuf__ T*)outputTensor.GetPhyAddr();
286- auto reInAddr = reinterpret_cast<__local_mem__ RT*>(inputAddr);285+ auto reInAddr = reinterpret_cast<__ubuf__ RT*>(inputAddr);
287- auto reOutAddr = reinterpret_cast<__local_mem__ RT*>(outputAddr);286+ auto reOutAddr = reinterpret_cast<__ubuf__ RT*>(outputAddr);
288 287 
289 uint32_t axis4BA = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt);288 uint32_t axis4BA = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt);
290 uint32_t axis4Offset = VL_CNT;289 uint32_t axis4Offset = VL_CNT;
@@ -307,12 +306,12 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBroadcastToA(
307 MaskReg mask = UpdateMask<RT>(lastASize);306 MaskReg mask = UpdateMask<RT>(lastASize);
308 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {307 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {
309 auto aregI = Reg::CreateAddrReg<RT>(axis4LpIdx, axis4Offset, axis2Idx, axis2InOffset);308 auto aregI = Reg::CreateAddrReg<RT>(axis4LpIdx, axis4Offset, axis2Idx, axis2InOffset);
310- DataCopy(tmpIn, reInAddr, aregI);309+ Reg::LoadAlign(tmpIn, reInAddr, aregI);
311 for (uint16_t axis1Idx = 0; axis1Idx < static_cast<uint16_t>(innerAxis1); axis1Idx++) {310 for (uint16_t axis1Idx = 0; axis1Idx < static_cast<uint16_t>(innerAxis1); axis1Idx++) {
312 for (uint16_t axis3Idx = 0; axis3Idx < static_cast<uint16_t>(innerAxis3); axis3Idx++) {311 for (uint16_t axis3Idx = 0; axis3Idx < static_cast<uint16_t>(innerAxis3); axis3Idx++) {
313 auto aregO = Reg::CreateAddrReg<RT>(axis4LpIdx, axis4Offset, axis2Idx, axis2Offset,312 auto aregO = Reg::CreateAddrReg<RT>(axis4LpIdx, axis4Offset, axis2Idx, axis2Offset,
314 axis1Idx, axis1Offset, axis3Idx, axis3Offset);313 axis1Idx, axis1Offset, axis3Idx, axis3Offset);
315- DataCopy(reOutAddr, tmpIn, aregO, mask);314+ Reg::StoreAlign(reOutAddr, tmpIn, aregO, mask);
316 }315 }
317 }316 }
318 }317 }
@@ -326,11 +325,11 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBroadcastToA(
326 MaskReg mask = UpdateMask<RT>(lastASize);325 MaskReg mask = UpdateMask<RT>(lastASize);
327 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {326 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {
328 auto aregI = Reg::CreateAddrReg<RT>(axis4LpIdx, axis4Offset, axis2Idx, axis2InOffset);327 auto aregI = Reg::CreateAddrReg<RT>(axis4LpIdx, axis4Offset, axis2Idx, axis2InOffset);
329- DataCopy(tmpIn, reInAddr, aregI);328+ Reg::LoadAlign(tmpIn, reInAddr, aregI);
330 for (uint16_t axis3Idx = 0; axis3Idx < static_cast<uint16_t>(innerAxis3); axis3Idx++) {329 for (uint16_t axis3Idx = 0; axis3Idx < static_cast<uint16_t>(innerAxis3); axis3Idx++) {
331 auto aregO = Reg::CreateAddrReg<RT>(axis4LpIdx, axis4Offset, axis2Idx, axis2Offset, axis3Idx,330 auto aregO = Reg::CreateAddrReg<RT>(axis4LpIdx, axis4Offset, axis2Idx, axis2Offset, axis3Idx,
332 axis3Offset);331 axis3Offset);
333- DataCopy(reOutAddr, tmpIn, aregO, mask);332+ Reg::StoreAlign(reOutAddr, tmpIn, aregO, mask);
334 }333 }
335 }334 }
336 }335 }
@@ -342,10 +341,10 @@ template <typename T, typename U, bool isLastDimSmall>
342__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBrcLastDimLEBlock(LocalTensor<T>& outputTensor,341__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBrcLastDimLEBlock(LocalTensor<T>& outputTensor,
343 LocalTensor<T>& inputTensor)342 LocalTensor<T>& inputTensor)
344{343{
345- __local_mem__ T* inputAddr = (__local_mem__ T*)inputTensor.GetPhyAddr();344+ __ubuf__ T* inputAddr = (__ubuf__ T*)inputTensor.GetPhyAddr();
346- __local_mem__ T* outputAddr = (__local_mem__ T*)outputTensor.GetPhyAddr();345+ __ubuf__ T* outputAddr = (__ubuf__ T*)outputTensor.GetPhyAddr();
347- auto reInAddr = reinterpret_cast<__local_mem__ RT*>(inputAddr);346+ auto reInAddr = reinterpret_cast<__ubuf__ RT*>(inputAddr);
348- auto reOutAddr = reinterpret_cast<__local_mem__ RT*>(outputAddr);347+ auto reOutAddr = reinterpret_cast<__ubuf__ RT*>(outputAddr);
349 348 
350 uint32_t axis4BA = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt);349 uint32_t axis4BA = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt);
351 if constexpr (sizeof(T) != sizeof(RT)) {350 if constexpr (sizeof(T) != sizeof(RT)) {
@@ -362,9 +361,9 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBrcLastDimLEB
362 AscendC::Reg::RegTensor<RT> tmpIn;361 AscendC::Reg::RegTensor<RT> tmpIn;
363 MaskReg mask = UpdateMask<RT>(lastASize);362 MaskReg mask = UpdateMask<RT>(lastASize);
364 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {363 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {
365- DataCopy<RT, Reg::LoadDist::DIST_BLK>(tmpIn, reInAddr + axis2Idx * axis2InOffset);364+ Reg::LoadAlign<RT, Reg::LoadDist::DIST_BLK>(tmpIn, reInAddr + axis2Idx * axis2InOffset);
366 for (uint16_t axis1Idx = 0; axis1Idx < static_cast<uint16_t>(innerAxis1); axis1Idx++) {365 for (uint16_t axis1Idx = 0; axis1Idx < static_cast<uint16_t>(innerAxis1); axis1Idx++) {
367- DataCopy(reOutAddr + axis2Idx * axis2Offset + axis1Idx * axis1Offset, tmpIn, mask);366+ Reg::StoreAlign(reOutAddr + axis2Idx * axis2Offset + axis1Idx * axis1Offset, tmpIn, mask);
368 }367 }
369 }368 }
370 }369 }
@@ -374,8 +373,8 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBrcLastDimLEB
374 AscendC::Reg::RegTensor<RT> tmpIn;373 AscendC::Reg::RegTensor<RT> tmpIn;
375 MaskReg mask = UpdateMask<RT>(lastASize);374 MaskReg mask = UpdateMask<RT>(lastASize);
376 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {375 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {
377- DataCopy<RT, Reg::LoadDist::DIST_BLK>(tmpIn, reInAddr + axis2Idx * axis2InOffset);376+ Reg::LoadAlign<RT, Reg::LoadDist::DIST_BLK>(tmpIn, reInAddr + axis2Idx * axis2InOffset);
378- DataCopy(reOutAddr + axis2Idx * axis2Offset, tmpIn, mask);377+ Reg::StoreAlign(reOutAddr + axis2Idx * axis2Offset, tmpIn, mask);
379 }378 }
380 }379 }
381 }380 }
@@ -399,10 +398,10 @@ template <typename T, typename U, bool isLastDimSmall>
399__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBrcLastDimGTBlock(LocalTensor<T>& outputTensor,398__aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBrcLastDimGTBlock(LocalTensor<T>& outputTensor,
400 LocalTensor<T>& inputTensor)399 LocalTensor<T>& inputTensor)
401{400{
402- __local_mem__ T* inputAddr = (__local_mem__ T*)inputTensor.GetPhyAddr();401+ __ubuf__ T* inputAddr = (__ubuf__ T*)inputTensor.GetPhyAddr();
403- __local_mem__ T* outputAddr = (__local_mem__ T*)outputTensor.GetPhyAddr();402+ __ubuf__ T* outputAddr = (__ubuf__ T*)outputTensor.GetPhyAddr();
404- auto reInAddr = reinterpret_cast<__local_mem__ int32_t*>(inputAddr);403+ auto reInAddr = reinterpret_cast<__ubuf__ int32_t*>(inputAddr);
405- auto reOutAddr = reinterpret_cast<__local_mem__ int32_t*>(outputAddr);404+ auto reOutAddr = reinterpret_cast<__ubuf__ int32_t*>(outputAddr);
406 405 
407 uint32_t axis4BA = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt);406 uint32_t axis4BA = Ops::Base::CeilAlign(innerAxis4, dataAlignCnt);
408 if constexpr (sizeof(T) == sizeof(int64_t)) {407 if constexpr (sizeof(T) == sizeof(int64_t)) {
@@ -426,10 +425,10 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBrcLastDimGTB
426 GenGatherIdx(gatherIdx, static_cast<int32_t>(axis4BA));425 GenGatherIdx(gatherIdx, static_cast<int32_t>(axis4BA));
427 MaskReg mask = UpdateMask<int32_t>(lastASize);426 MaskReg mask = UpdateMask<int32_t>(lastASize);
428 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {427 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {
429- DataCopy(tmpIn, reInAddr + axis2Idx * axis2InOffset);428+ Reg::LoadAlign(tmpIn, reInAddr + axis2Idx * axis2InOffset);
430 Reg::Gather(tmpOut, tmpIn, (Reg::RegTensor<uint32_t>&)gatherIdx);429 Reg::Gather(tmpOut, tmpIn, (Reg::RegTensor<uint32_t>&)gatherIdx);
431 for (uint16_t axis1Idx = 0; axis1Idx < static_cast<uint16_t>(innerAxis1); axis1Idx++) {430 for (uint16_t axis1Idx = 0; axis1Idx < static_cast<uint16_t>(innerAxis1); axis1Idx++) {
432- DataCopy(reOutAddr + axis2Idx * axis2Offset + axis1Idx * axis1Offset, tmpOut, mask);431+ Reg::StoreAlign(reOutAddr + axis2Idx * axis2Offset + axis1Idx * axis1Offset, tmpOut, mask);
433 }432 }
434 }433 }
435 }434 }
@@ -442,9 +441,9 @@ __aicore__ inline void BroadcastToUb<T, U, isLastDimSmall>::VFInnerBrcLastDimGTB
442 GenGatherIdx(gatherIdx, static_cast<int32_t>(axis4BA));441 GenGatherIdx(gatherIdx, static_cast<int32_t>(axis4BA));
443 MaskReg mask = UpdateMask<int32_t>(lastASize);442 MaskReg mask = UpdateMask<int32_t>(lastASize);
444 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {443 for (uint16_t axis2Idx = 0; axis2Idx < static_cast<uint16_t>(innerAxis2); axis2Idx++) {
445- DataCopy(tmpIn, reInAddr + axis2Idx * axis2InOffset);444+ Reg::LoadAlign(tmpIn, reInAddr + axis2Idx * axis2InOffset);
446 Reg::Gather(tmpOut, tmpIn, (Reg::RegTensor<uint32_t>&)gatherIdx);445 Reg::Gather(tmpOut, tmpIn, (Reg::RegTensor<uint32_t>&)gatherIdx);
447- DataCopy(reOutAddr + axis2Idx * axis2Offset, tmpOut, mask);446+ Reg::StoreAlign(reOutAddr + axis2Idx * axis2Offset, tmpOut, mask);
448 }447 }
449 }448 }
450 }449 }
Mconversion/confusion_transpose_d/op_host/arch35/confusion_transpose_d_tiling_arch35.cpp+3-3
@@ -303,9 +303,9 @@ ge::graphStatus ConfusionTransposeDTilingForAscendC(gert::TilingContext* context
303 compileInfo.transposeCompilerInfo.ubSize = ubSize;303 compileInfo.transposeCompilerInfo.ubSize = ubSize;
304 304 
305 TransposeNddmaTiling transposeTilingObject(context);305 TransposeNddmaTiling transposeTilingObject(context);
306- OP_CHECK_IF((transposeTilingObject.TilingForReleatedTranspose(context, &tilingData.transposeOpTiling,306+ OP_CHECK_IF((transposeTilingObject.TilingForRelatedTranspose(context, &tilingData.transposeOpTiling,
307- &compileInfo.transposeCompilerInfo,307+ &compileInfo.transposeCompilerInfo,
308- inputShapeInfo) == ge::GRAPH_FAILED),308+ inputShapeInfo) == ge::GRAPH_FAILED),
309 OP_LOGE(context->GetNodeName(), "Transpose Tiling failed"), return ge::GRAPH_FAILED);309 OP_LOGE(context->GetNodeName(), "Transpose Tiling failed"), return ge::GRAPH_FAILED);
310 310 
311 tilingData.SaveToBuffer(context->GetRawTilingData()->GetData(), context->GetRawTilingData()->GetCapacity());311 tilingData.SaveToBuffer(context->GetRawTilingData()->GetData(), context->GetRawTilingData()->GetCapacity());
Mconversion/depth_to_space/examples/test_geir_depth_to_space.cpp+3-3
@@ -185,7 +185,7 @@ int main(int argc, char* argv[])
185 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};185 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
186 Status ret = ge::GEInitialize(global_options);186 Status ret = ge::GEInitialize(global_options);
187 if (ret != SUCCESS) {187 if (ret != SUCCESS) {
188- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());188+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
189 return FAILED;189 return FAILED;
190 }190 }
191 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());191 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -235,7 +235,7 @@ int main(int argc, char* argv[])
235 std::vector<ge::Tensor> output;235 std::vector<ge::Tensor> output;
236 ret = session->RunGraph(graph_id, input, output);236 ret = session->RunGraph(graph_id, input, output);
237 if (ret != SUCCESS) {237 if (ret != SUCCESS) {
238- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());238+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
239 delete session;239 delete session;
240 GEFinalize();240 GEFinalize();
241 return FAILED;241 return FAILED;
@@ -277,7 +277,7 @@ int main(int argc, char* argv[])
277 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());277 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
278 ret = ge::GEFinalize();278 ret = ge::GEFinalize();
279 if (ret != SUCCESS) {279 if (ret != SUCCESS) {
280- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());280+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
281 return FAILED;281 return FAILED;
282 }282 }
283 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());283 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mconversion/depth_to_space/op_host/arch35/depth_to_space_tiling_arch35.cpp+3-3
@@ -209,9 +209,9 @@ ge::graphStatus DepthToSpaceTilingForAscendC(gert::TilingContext* context,
209 compileInfo.transposeCompilerInfo.ubSize = transposeCompileInfo->ubSize;209 compileInfo.transposeCompilerInfo.ubSize = transposeCompileInfo->ubSize;
210 210 
211 TransposeNddmaTiling transposeTilingObject(context);211 TransposeNddmaTiling transposeTilingObject(context);
212- OP_CHECK_IF((transposeTilingObject.TilingForReleatedTranspose(context, &tilingData.transposeOpTiling,212+ OP_CHECK_IF((transposeTilingObject.TilingForRelatedTranspose(context, &tilingData.transposeOpTiling,
213- &compileInfo.transposeCompilerInfo,213+ &compileInfo.transposeCompilerInfo,
214- inputShapeInfo) == ge::GRAPH_FAILED),214+ inputShapeInfo) == ge::GRAPH_FAILED),
215 OP_LOGE(context->GetNodeName(), "Transpose Tiling failed"), return ge::GRAPH_FAILED);215 OP_LOGE(context->GetNodeName(), "Transpose Tiling failed"), return ge::GRAPH_FAILED);
216 216 
217 tilingData.SaveToBuffer(context->GetRawTilingData()->GetData(), context->GetRawTilingData()->GetCapacity());217 tilingData.SaveToBuffer(context->GetRawTilingData()->GetData(), context->GetRawTilingData()->GetCapacity());
Mconversion/matrix_set_diag_v2/examples/test_geir_matrix_set_diag_v2.cpp+3-3
@@ -182,7 +182,7 @@ int ExecuteGraph(Graph& graph, std::vector<ge::Tensor>& input, std::vector<ge::T
182 printf("%s - INFO - [XIR]: Start to run ir compute graph\n", GetTime().c_str());182 printf("%s - INFO - [XIR]: Start to run ir compute graph\n", GetTime().c_str());
183 ret = session->RunGraph(graph_id, input, output);183 ret = session->RunGraph(graph_id, input, output);
184 if (ret != SUCCESS) {184 if (ret != SUCCESS) {
185- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());185+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
186 delete session;186 delete session;
187 GEFinalize();187 GEFinalize();
188 return FAILED;188 return FAILED;
@@ -232,7 +232,7 @@ int main(int argc, char* argv[])
232 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};232 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
233 Status ret = ge::GEInitialize(global_options);233 Status ret = ge::GEInitialize(global_options);
234 if (ret != SUCCESS) {234 if (ret != SUCCESS) {
235- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());235+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
236 return FAILED;236 return FAILED;
237 }237 }
238 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());238 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -272,7 +272,7 @@ int main(int argc, char* argv[])
272 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());272 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
273 ret = ge::GEFinalize();273 ret = ge::GEFinalize();
274 if (ret != SUCCESS) {274 if (ret != SUCCESS) {
275- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());275+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
276 return FAILED;276 return FAILED;
277 }277 }
278 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());278 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mconversion/pad_v3/op_host/arch35/pad_v3_tiling_arch35.cpp+8-8
@@ -320,7 +320,7 @@ void PadACTiling::GetOptimizeTiling(const PadV3UbTileInfo& oldTilingInfo, PadV3U
320 // ubPerCoreCnt 不发生变化为前提时，最多循环coreNum+dimNum_次就可以找到最优解, 这里仅做防死循环保护320 // ubPerCoreCnt 不发生变化为前提时，最多循环coreNum+dimNum_次就可以找到最优解, 这里仅做防死循环保护
321 uint32_t maxLoop = coreNum_ + dimNum_;321 uint32_t maxLoop = coreNum_ + dimNum_;
322 uint32_t loops = 0;322 uint32_t loops = 0;
323- bool finded = false;323+ bool found = false;
324 for (uint8_t iDim = oldTilingInfo.ubSplitAxis; iDim < dimNum_; iDim++) {324 for (uint8_t iDim = oldTilingInfo.ubSplitAxis; iDim < dimNum_; iDim++) {
325 if (iDim != oldTilingInfo.ubSplitAxis) {325 if (iDim != oldTilingInfo.ubSplitAxis) {
326 outCount *= cutOutput ? tilingData_->outShape[iDim - 1] : tilingData_->inShape[iDim - 1];326 outCount *= cutOutput ? tilingData_->outShape[iDim - 1] : tilingData_->inShape[iDim - 1];
@@ -332,7 +332,7 @@ void PadACTiling::GetOptimizeTiling(const PadV3UbTileInfo& oldTilingInfo, PadV3U
332 for (int64_t factor = iDimFactor; factor > 0;) {332 for (int64_t factor = iDimFactor; factor > 0;) {
333 loops++;333 loops++;
334 if (loops > maxLoop) {334 if (loops > maxLoop) {
335- finded = true;335+ found = true;
336 OP_LOGD(context_, "loops:%u is bigger than maxLoop:%u", loops, maxLoop);336 OP_LOGD(context_, "loops:%u is bigger than maxLoop:%u", loops, maxLoop);
337 break;337 break;
338 }338 }
@@ -352,14 +352,14 @@ void PadACTiling::GetOptimizeTiling(const PadV3UbTileInfo& oldTilingInfo, PadV3U
352 if (oldTilingInfo.ubPerCoreCnt != tmpPerCount) {352 if (oldTilingInfo.ubPerCoreCnt != tmpPerCount) {
353 OP_LOGD(context_, "iDim:%u factor:%ld tmpPerCount:%ld not equal ubPerCoreCnt:%ld", iDim, factor,353 OP_LOGD(context_, "iDim:%u factor:%ld tmpPerCount:%ld not equal ubPerCoreCnt:%ld", iDim, factor,
354 tmpPerCount, oldTilingInfo.ubPerCoreCnt);354 tmpPerCount, oldTilingInfo.ubPerCoreCnt);
355- finded = true;355+ found = true;
356 break;356 break;
357 }357 }
358 358 
359 if (factor * tilingData_->inStride[iDim] * dtypeBytes_ < MIN_PER_UB_SIZE ||359 if (factor * tilingData_->inStride[iDim] * dtypeBytes_ < MIN_PER_UB_SIZE ||
360 tmpFactor * tilingData_->inStride[iDim] * dtypeBytes_ < MIN_PER_UB_SIZE) {360 tmpFactor * tilingData_->inStride[iDim] * dtypeBytes_ < MIN_PER_UB_SIZE) {
361 OP_LOGD(context_, "iDim:%u factor:%ld tmpFactor:%ld in ubSize is too small", iDim, factor, tmpFactor);361 OP_LOGD(context_, "iDim:%u factor:%ld tmpFactor:%ld in ubSize is too small", iDim, factor, tmpFactor);
362- finded = true;362+ found = true;
363 break;363 break;
364 }364 }
365 365 
@@ -373,16 +373,16 @@ void PadACTiling::GetOptimizeTiling(const PadV3UbTileInfo& oldTilingInfo, PadV3U
373 OP_LOGD(context_, "current iDim:%u factor:%ld iDimOuter:%ld tmpFactor:%ld tmpCoreNum:%ld usedRate:%f", iDim,373 OP_LOGD(context_, "current iDim:%u factor:%ld iDimOuter:%ld tmpFactor:%ld tmpCoreNum:%ld usedRate:%f", iDim,
374 factor, iDimOuter, tmpFactor, tmpCoreNum, usedRate);374 factor, iDimOuter, tmpFactor, tmpCoreNum, usedRate);
375 if (usedRate >= MIN_USED_CORES_RATIO) {375 if (usedRate >= MIN_USED_CORES_RATIO) {
376- finded = true;376+ found = true;
377 break;377 break;
378 }378 }
379 factor = tmpFactor - 1;379 factor = tmpFactor - 1;
380 }380 }
381 381 
382- OP_LOGD(context_, "iDim:%u ubSplitAxis:%u ubSplitFactor:%u loops:%u finded:%d", iDim, newTilingInfo.ubSplitAxis,382+ OP_LOGD(context_, "iDim:%u ubSplitAxis:%u ubSplitFactor:%u loops:%u found:%d", iDim, newTilingInfo.ubSplitAxis,
383- newTilingInfo.ubSplitFactor, loops, finded);383+ newTilingInfo.ubSplitFactor, loops, found);
384 384 
385- if (finded) {385+ if (found) {
386 break;386 break;
387 }387 }
388 }388 }
Mconversion/pad_v3/op_kernel/arch35/pad_circular_gather.h+67-73
@@ -289,8 +289,8 @@ private:
289 uint32_t alignRed = copyStartOffset % BLOCK_NUM;289 uint32_t alignRed = copyStartOffset % BLOCK_NUM;
290 uint32_t alignOffset = 0;290 uint32_t alignOffset = 0;
291 if (alignRed != 0) {291 if (alignRed != 0) {
292- __local_mem__ T* inAddrTmp = (__local_mem__ T*)outLocalReal.GetPhyAddr() + copyStartOffset;292+ __ubuf__ T* inAddrTmp = (__ubuf__ T*)outLocalReal.GetPhyAddr() + copyStartOffset;
293- __local_mem__ T* outAddrTmp = (__local_mem__ T*)outLocalTmp.GetPhyAddr();293+ __ubuf__ T* outAddrTmp = (__ubuf__ T*)outLocalTmp.GetPhyAddr();
294 294 
295 alignOffset = BLOCK_NUM - alignRed;295 alignOffset = BLOCK_NUM - alignRed;
296 copyStartOffset = copyStartOffset + alignOffset;296 copyStartOffset = copyStartOffset + alignOffset;
@@ -356,21 +356,21 @@ private:
356 }356 }
357 }357 }
358 358 
359- __aicore__ inline void CopyTmpUnAlign(__local_mem__ T* inAddrTmp, __local_mem__ T* outAddrTmp, uint32_t alignOffset)359+ __aicore__ inline void CopyTmpUnAlign(__ubuf__ T* inAddrTmp, __ubuf__ T* outAddrTmp, uint32_t alignOffset)
360 {360 {
361 uint32_t newCnt = (sizeof(T) != sizeof(OutType)) ? CONST2 * alignOffset : alignOffset;361 uint32_t newCnt = (sizeof(T) != sizeof(OutType)) ? CONST2 * alignOffset : alignOffset;
362- auto newInAddr = reinterpret_cast<__local_mem__ OutType*>(inAddrTmp);362+ auto newInAddr = reinterpret_cast<__ubuf__ OutType*>(inAddrTmp);
363- auto newOutAddr = reinterpret_cast<__local_mem__ OutType*>(outAddrTmp);363+ auto newOutAddr = reinterpret_cast<__ubuf__ OutType*>(outAddrTmp);
364 364 
365 __VEC_SCOPE__365 __VEC_SCOPE__
366 {366 {
367 Reg::RegTensor<OutType> regData;367 Reg::RegTensor<OutType> regData;
368- Reg::UnalignReg uReg;368+ Reg::UnalignRegForLoad uReg;
369 Reg::MaskReg maskIdx = Reg::UpdateMask<OutType>(newCnt);369 Reg::MaskReg maskIdx = Reg::UpdateMask<OutType>(newCnt);
370 370 
371- Reg::DataCopyUnAlignPre(uReg, newInAddr);371+ Reg::LoadUnAlignPre(uReg, newInAddr);
372- Reg::DataCopyUnAlign(regData, uReg, newInAddr, newCnt);372+ Reg::LoadUnAlign(regData, uReg, newInAddr, newCnt);
373- Reg::DataCopy(newOutAddr, regData, maskIdx);373+ Reg::StoreAlign(newOutAddr, regData, maskIdx);
374 }374 }
375 }375 }
376 376 
@@ -401,7 +401,7 @@ private:
401 int32_t lastLeftPadNum = tdPtr_->leftPad[dimNum_ - 1];401 int32_t lastLeftPadNum = tdPtr_->leftPad[dimNum_ - 1];
402 uint32_t lastOutDimSize = tdPtr_->outShape[dimNum_ - 1];402 uint32_t lastOutDimSize = tdPtr_->outShape[dimNum_ - 1];
403 uint16_t lastDimsLeft = vlSplitIn_;403 uint16_t lastDimsLeft = vlSplitIn_;
404- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();404+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
405 405 
406 __VEC_SCOPE__406 __VEC_SCOPE__
407 {407 {
@@ -409,31 +409,31 @@ private:
409 Reg::RegTensor<RangeType> lineRange, lineRangeNew;409 Reg::RegTensor<RangeType> lineRange, lineRangeNew;
410 Reg::MaskReg leftMask, rightMask;410 Reg::MaskReg leftMask, rightMask;
411 Reg::RegTensor<RangeType> leftPadIdxReg, rightPadIdxReg;411 Reg::RegTensor<RangeType> leftPadIdxReg, rightPadIdxReg;
412- Reg::UnalignReg uRegIn;412+ Reg::UnalignRegForStore uRegIn;
413 413 
414 // 先拼好-1轴的索引414 // 先拼好-1轴的索引
415 Reg::Arange(lineRange, 0);415 Reg::Arange(lineRange, 0);
416 // 先拷出去，防止索引尾部脏数据416 // 先拷出去，防止索引尾部脏数据
417- Reg::DataCopy(idxAddr, lineRange, maskIdx);417+ Reg::StoreAlign(idxAddr, lineRange, maskIdx);
418 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();418 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();
419 419 
420 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);420 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);
421- Reg::CompareScalar<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);421+ Reg::Compares<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);
422 Reg::Arange(leftPadIdxReg, lastInDimSize - lastLeftPadNum);422 Reg::Arange(leftPadIdxReg, lastInDimSize - lastLeftPadNum);
423- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);423+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);
424 424 
425 Reg::Arange(rightPadIdxReg, ((RangeType)-1) * (lastLeftPadNum + lastInDimSize));425 Reg::Arange(rightPadIdxReg, ((RangeType)-1) * (lastLeftPadNum + lastInDimSize));
426- Reg::CompareScalar<RangeType, CMPMODE::GE>(rightMask, rightPadIdxReg, 0, maskIdx);426+ Reg::Compares<RangeType, CMPMODE::GE>(rightMask, rightPadIdxReg, 0, maskIdx);
427- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);427+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);
428 428 
429 // -2轴有效输入的索引429 // -2轴有效输入的索引
430- __local_mem__ RangeType* idxAddrTmp2 = idxAddr;430+ __ubuf__ RangeType* idxAddrTmp2 = idxAddr;
431 for (uint16_t i = 0; i < lastDimsLeft; i++) {431 for (uint16_t i = 0; i < lastDimsLeft; i++) {
432 RangeType loopStride = (RangeType)lastInDimSize * i;432 RangeType loopStride = (RangeType)lastInDimSize * i;
433 Reg::Adds(lineRangeNew, lineRange, loopStride, maskIdx);433 Reg::Adds(lineRangeNew, lineRange, loopStride, maskIdx);
434- Reg::DataCopyUnAlign(idxAddrTmp2, lineRangeNew, uRegIn, lastOutDimSize);434+ Reg::StoreUnAlign(idxAddrTmp2, lineRangeNew, uRegIn, lastOutDimSize);
435 }435 }
436- Reg::DataCopyUnAlignPost(idxAddrTmp2, uRegIn, 0);436+ Reg::StoreUnAlignPost(idxAddrTmp2, uRegIn, 0);
437 }437 }
438 }438 }
439 439 
@@ -450,7 +450,7 @@ private:
450 int32_t lastLeftPadNum = tdPtr_->leftPad[dimNum_ - 1];450 int32_t lastLeftPadNum = tdPtr_->leftPad[dimNum_ - 1];
451 uint16_t last2LeftPadNum = tdPtr_->leftPad[dimNum_ - CONST2];451 uint16_t last2LeftPadNum = tdPtr_->leftPad[dimNum_ - CONST2];
452 uint16_t last2RightPadNum = tdPtr_->outShape[dimNum_ - CONST2] - lastSecInDimSize - last2LeftPadNum;452 uint16_t last2RightPadNum = tdPtr_->outShape[dimNum_ - CONST2] - lastSecInDimSize - last2LeftPadNum;
453- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();453+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
454 454 
455 __VEC_SCOPE__455 __VEC_SCOPE__
456 {456 {
@@ -458,106 +458,103 @@ private:
458 Reg::RegTensor<RangeType> lineRange, lineRangeNew, lineRangeBk;458 Reg::RegTensor<RangeType> lineRange, lineRangeNew, lineRangeBk;
459 Reg::MaskReg leftMask, rightMask;459 Reg::MaskReg leftMask, rightMask;
460 Reg::RegTensor<RangeType> leftPadIdxReg, rightPadIdxReg;460 Reg::RegTensor<RangeType> leftPadIdxReg, rightPadIdxReg;
461- Reg::UnalignReg uReg;461+ Reg::UnalignRegForStore uReg;
462 462 
463 // 先拼好-1轴的索引463 // 先拼好-1轴的索引
464 Reg::Arange(lineRange, 0);464 Reg::Arange(lineRange, 0);
465 // 先拷出去，防止索引尾部脏数据465 // 先拷出去，防止索引尾部脏数据
466- Reg::DataCopy(idxAddr, lineRange, maskIdx);466+ Reg::StoreAlign(idxAddr, lineRange, maskIdx);
467 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();467 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();
468 468 
469 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);469 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);
470- Reg::CompareScalar<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);470+ Reg::Compares<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);
471 Reg::Arange(leftPadIdxReg, lastInDimSize - lastLeftPadNum);471 Reg::Arange(leftPadIdxReg, lastInDimSize - lastLeftPadNum);
472- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);472+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);
473 473 
474 Reg::Arange(rightPadIdxReg, ((RangeType)-1) * (lastLeftPadNum + lastInDimSize));474 Reg::Arange(rightPadIdxReg, ((RangeType)-1) * (lastLeftPadNum + lastInDimSize));
475- Reg::CompareScalar<RangeType, CMPMODE::GE>(rightMask, rightPadIdxReg, 0, maskIdx);475+ Reg::Compares<RangeType, CMPMODE::GE>(rightMask, rightPadIdxReg, 0, maskIdx);
476- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);476+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);
477 477 
478 // -3轴有效输入的索引478 // -3轴有效输入的索引
479 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {479 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {
480 Reg::Adds(lineRangeBk, lineRange, (RangeType)(i * inStride1), maskIdx);480 Reg::Adds(lineRangeBk, lineRange, (RangeType)(i * inStride1), maskIdx);
481 // -2轴leftpad行数, 索引取H轴下部481 // -2轴leftpad行数, 索引取H轴下部
482- __local_mem__ RangeType* idxAddrTmp = idxAddr + i * outStride1;482+ __ubuf__ RangeType* idxAddrTmp = idxAddr + i * outStride1;
483 for (uint16_t j = 0; j < last2LeftPadNum; j++) {483 for (uint16_t j = 0; j < last2LeftPadNum; j++) {
484 Reg::Adds(lineRangeNew, lineRangeBk,484 Reg::Adds(lineRangeNew, lineRangeBk,
485 (RangeType)((lastSecInDimSize - last2LeftPadNum + j) * lastInDimSize), maskIdx);485 (RangeType)((lastSecInDimSize - last2LeftPadNum + j) * lastInDimSize), maskIdx);
486- Reg::DataCopyUnAlign(idxAddrTmp, lineRangeNew, uReg, outStride2);486+ Reg::StoreUnAlign(idxAddrTmp, lineRangeNew, uReg, outStride2);
487 }487 }
488- Reg::DataCopyUnAlignPost(idxAddrTmp, uReg, 0);488+ Reg::StoreUnAlignPost(idxAddrTmp, uReg, 0);
489 489 
490 // -2 轴inputshape, 索引递增490 // -2 轴inputshape, 索引递增
491- __local_mem__ RangeType* idxAddrTmp1 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2;491+ __ubuf__ RangeType* idxAddrTmp1 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2;
492 for (uint16_t j = 0; j < lastSecInDimSize; j++) {492 for (uint16_t j = 0; j < lastSecInDimSize; j++) {
493 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(j * lastInDimSize), maskIdx);493 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(j * lastInDimSize), maskIdx);
494- Reg::DataCopyUnAlign(idxAddrTmp1, lineRangeNew, uReg, outStride2);494+ Reg::StoreUnAlign(idxAddrTmp1, lineRangeNew, uReg, outStride2);
495 }495 }
496- Reg::DataCopyUnAlignPost(idxAddrTmp1, uReg, 0);496+ Reg::StoreUnAlignPost(idxAddrTmp1, uReg, 0);
497 497 
498 // -2轴rightpad行数, 索引取H轴上部498 // -2轴rightpad行数, 索引取H轴上部
499- __local_mem__ RangeType* idxAddrTmp2 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2 +499+ __ubuf__ RangeType* idxAddrTmp2 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2 +
500- lastSecInDimSize * outStride2;500+ lastSecInDimSize * outStride2;
501 for (uint16_t j = 0; j < last2RightPadNum; j++) {501 for (uint16_t j = 0; j < last2RightPadNum; j++) {
502 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(j * lastInDimSize), maskIdx);502 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(j * lastInDimSize), maskIdx);
503- Reg::DataCopyUnAlign(idxAddrTmp2, lineRangeNew, uReg, outStride2);503+ Reg::StoreUnAlign(idxAddrTmp2, lineRangeNew, uReg, outStride2);
504 }504 }
505- Reg::DataCopyUnAlignPost(idxAddrTmp2, uReg, 0);505+ Reg::StoreUnAlignPost(idxAddrTmp2, uReg, 0);
506 }506 }
507 }507 }
508 }508 }
509 509 
510 __aicore__ inline void VlInCopyProc(uint16_t inLoops, uint16_t lastInLoops, RangeType idxOffset, uint32_t maskValue,510 __aicore__ inline void VlInCopyProc(uint16_t inLoops, uint16_t lastInLoops, RangeType idxOffset, uint32_t maskValue,
511- uint32_t lastInMaskValue, __local_mem__ T* curInAddr,511+ uint32_t lastInMaskValue, __ubuf__ T* curInAddr, __ubuf__ T* curOutAddr,
512- __local_mem__ T* curOutAddr, Reg::RegTensor<RangeType>& regIdx,512+ Reg::RegTensor<RangeType>& regIdx, uint32_t idxPadOffset)
513- uint32_t idxPadOffset)
514 {513 {
515 Reg::RegTensor<T> regData;514 Reg::RegTensor<T> regData;
516 Reg::RegTensor<T> regDataT;515 Reg::RegTensor<T> regDataT;
517 Reg::RegTensor<RangeType> regIdxBk;516 Reg::RegTensor<RangeType> regIdxBk;
518 Reg::RegTensor<RangeType> regNewIdx;517 Reg::RegTensor<RangeType> regNewIdx;
519- Reg::UnalignReg uReg;518+ Reg::UnalignRegForStore uReg;
520 uint32_t validMask = maskValue;519 uint32_t validMask = maskValue;
521 if constexpr (sizeof(T) == 8) {520 if constexpr (sizeof(T) == 8) {
522 validMask = maskValue * 2;521 validMask = maskValue * 2;
523 }522 }
524 Reg::MaskReg maskIdx = Reg::UpdateMask<RangeType>(validMask);523 Reg::MaskReg maskIdx = Reg::UpdateMask<RangeType>(validMask);
525 524 
526- __local_mem__ T* outAddrTmp = curOutAddr;525+ __ubuf__ T* outAddrTmp = curOutAddr;
527 Reg::Adds(regIdxBk, regIdx, idxPadOffset, maskIdx);526 Reg::Adds(regIdxBk, regIdx, idxPadOffset, maskIdx);
528 for (uint16_t cpIdx = 0; cpIdx < inLoops; cpIdx++) {527 for (uint16_t cpIdx = 0; cpIdx < inLoops; cpIdx++) {
529 Reg::Adds(regNewIdx, regIdxBk, cpIdx * idxOffset, maskIdx);528 Reg::Adds(regNewIdx, regIdxBk, cpIdx * idxOffset, maskIdx);
530- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx,529+ Reg::Gather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx, maskIdx);
531- maskIdx);
532 if constexpr (sizeof(T) != 1) {530 if constexpr (sizeof(T) != 1) {
533- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, maskValue);531+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, maskValue);
534 } else {532 } else {
535 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);533 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
536- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, maskValue);534+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, maskValue);
537 }535 }
538 }536 }
539- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);537+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
540 for (uint16_t cpTailIdx = 0; cpTailIdx < lastInLoops; cpTailIdx++) {538 for (uint16_t cpTailIdx = 0; cpTailIdx < lastInLoops; cpTailIdx++) {
541 outAddrTmp = curOutAddr + inLoops * maskValue;539 outAddrTmp = curOutAddr + inLoops * maskValue;
542 Reg::Adds(regNewIdx, regIdxBk, inLoops * idxOffset, maskIdx);540 Reg::Adds(regNewIdx, regIdxBk, inLoops * idxOffset, maskIdx);
543- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx,541+ Reg::Gather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx, maskIdx);
544- maskIdx);
545 if constexpr (sizeof(T) != 1) {542 if constexpr (sizeof(T) != 1) {
546- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, lastInMaskValue);543+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, lastInMaskValue);
547 } else {544 } else {
548 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);545 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
549- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, lastInMaskValue);546+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, lastInMaskValue);
550 }547 }
551- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);548+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
552 }549 }
553 }550 }
554 551 
555 __aicore__ inline void GatherProcessUb2DFw(const LocalTensor<RangeType>& idxTensor, LocalTensor<T>& inTensor,552 __aicore__ inline void GatherProcessUb2DFw(const LocalTensor<RangeType>& idxTensor, LocalTensor<T>& inTensor,
556 LocalTensor<T>& outTensor, uint16_t ubAxisInCopyNum)553 LocalTensor<T>& outTensor, uint16_t ubAxisInCopyNum)
557 {554 {
558- __local_mem__ RangeType* idxAddrFw = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();555+ __ubuf__ RangeType* idxAddrFw = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
559- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();556+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
560- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr() + BLOCK_NUM;557+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr() + BLOCK_NUM;
561 558 
562 uint16_t vlSplitLoopIn = vlSplitIn_;559 uint16_t vlSplitLoopIn = vlSplitIn_;
563 RangeType idxOffset = tdPtr_->inStride[dimNum_ - CONST2] * vlSplitLoopIn;560 RangeType idxOffset = tdPtr_->inStride[dimNum_ - CONST2] * vlSplitLoopIn;
@@ -571,7 +568,7 @@ private:
571 __VEC_SCOPE__568 __VEC_SCOPE__
572 {569 {
573 Reg::RegTensor<RangeType> regIdx;570 Reg::RegTensor<RangeType> regIdx;
574- Reg::DataCopy(regIdx, idxAddrFw);571+ Reg::LoadAlign(regIdx, idxAddrFw);
575 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr, outAddr,572 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr, outAddr,
576 regIdx, 0);573 regIdx, 0);
577 }574 }
@@ -580,9 +577,9 @@ private:
580 __aicore__ inline void GatherProcessUb3DFw(const LocalTensor<RangeType>& idxTensor, LocalTensor<T>& inTensor,577 __aicore__ inline void GatherProcessUb3DFw(const LocalTensor<RangeType>& idxTensor, LocalTensor<T>& inTensor,
581 LocalTensor<T>& outTensor, uint16_t ubAxisInCopyNum)578 LocalTensor<T>& outTensor, uint16_t ubAxisInCopyNum)
582 {579 {
583- __local_mem__ RangeType* idxAddrFw = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();580+ __ubuf__ RangeType* idxAddrFw = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
584- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();581+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
585- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr() + BLOCK_NUM;582+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr() + BLOCK_NUM;
586 583 
587 uint16_t vlSplitLoopIn = vlSplitIn_;584 uint16_t vlSplitLoopIn = vlSplitIn_;
588 uint32_t strideInVl = tdPtr_->inStride[dimNum_ - CONST2];585 uint32_t strideInVl = tdPtr_->inStride[dimNum_ - CONST2];
@@ -633,13 +630,13 @@ private:
633 __VEC_SCOPE__630 __VEC_SCOPE__
634 {631 {
635 Reg::RegTensor<RangeType> regIdx;632 Reg::RegTensor<RangeType> regIdx;
636- Reg::DataCopy(regIdx, idxAddrFw);633+ Reg::LoadAlign(regIdx, idxAddrFw);
637 634 
638 // 该次Ub内C轴上的copyIn, VL切3维时退化为0635 // 该次Ub内C轴上的copyIn, VL切3维时退化为0
639 for (uint16_t uiIdx = 0; uiIdx < ubAxisInCopyLoops; uiIdx++) {636 for (uint16_t uiIdx = 0; uiIdx < ubAxisInCopyLoops; uiIdx++) {
640 // H轴左pad637 // H轴左pad
641 uint32_t idxPadOffset = uiIdx * strideInVlO1 + leftPadInVlOffset;638 uint32_t idxPadOffset = uiIdx * strideInVlO1 + leftPadInVlOffset;
642- __local_mem__ T* curInOutAddr = outAddr + uiIdx * strideOutVlO1;639+ __ubuf__ T* curInOutAddr = outAddr + uiIdx * strideOutVlO1;
643 VlInCopyProc(leftPadLoops, lastLeftPadLoops, idxOffset, maskValue, lastLeftPadMaskValue, inAddr,640 VlInCopyProc(leftPadLoops, lastLeftPadLoops, idxOffset, maskValue, lastLeftPadMaskValue, inAddr,
644 curInOutAddr, regIdx, idxPadOffset);641 curInOutAddr, regIdx, idxPadOffset);
645 642 
@@ -658,9 +655,9 @@ private:
658 __aicore__ inline void GatherProcessUb4DFw(const LocalTensor<RangeType>& idxTensor, LocalTensor<T>& inTensor,655 __aicore__ inline void GatherProcessUb4DFw(const LocalTensor<RangeType>& idxTensor, LocalTensor<T>& inTensor,
659 LocalTensor<T>& outTensor, uint16_t ubAxisInCopyNum)656 LocalTensor<T>& outTensor, uint16_t ubAxisInCopyNum)
660 {657 {
661- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();658+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
662- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();659+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
663- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr() + BLOCK_NUM;660+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr() + BLOCK_NUM;
664 661 
665 uint16_t vlSplitLoopIn = vlSplitIn_;662 uint16_t vlSplitLoopIn = vlSplitIn_;
666 uint16_t ubAxisLeftPadLoops = 0; // ubAxisLeftPadNum; 当前不支持N轴的pad, 只会为0663 uint16_t ubAxisLeftPadLoops = 0; // ubAxisLeftPadNum; 当前不支持N轴的pad, 只会为0
@@ -728,7 +725,7 @@ private:
728 __VEC_SCOPE__725 __VEC_SCOPE__
729 {726 {
730 Reg::RegTensor<RangeType> regIdx;727 Reg::RegTensor<RangeType> regIdx;
731- Reg::DataCopy(regIdx, idxAddr);728+ Reg::LoadAlign(regIdx, idxAddr);
732 729 
733 for (uint16_t nIdx = 0; nIdx < ubAxisInCopyLoops; nIdx++) {730 for (uint16_t nIdx = 0; nIdx < ubAxisInCopyLoops; nIdx++) {
734 // C轴左pad, VL切3维时退化为1731 // C轴左pad, VL切3维时退化为1
@@ -737,13 +734,12 @@ private:
737 for (uint16_t i = 0; i < vlO1LeftPadNum; i++) {734 for (uint16_t i = 0; i < vlO1LeftPadNum; i++) {
738 // H轴左pad, VL切3维时退化为C轴左pad735 // H轴左pad, VL切3维时退化为C轴左pad
739 uint32_t idxPadOffset = curInOffset + i * strideInVlO1 + leftPadInVlOffset;736 uint32_t idxPadOffset = curInOffset + i * strideInVlO1 + leftPadInVlOffset;
740- __local_mem__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;737+ __ubuf__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;
741 VlInCopyProc(leftPadLoops, lastLeftPadLoops, idxOffset, maskValue, lastLeftPadMaskValue, inAddr,738 VlInCopyProc(leftPadLoops, lastLeftPadLoops, idxOffset, maskValue, lastLeftPadMaskValue, inAddr,
742 curPadOutAddr, regIdx, idxPadOffset);739 curPadOutAddr, regIdx, idxPadOffset);
743 740 
744 // H轴输入个数, VL切3维时退化为C轴输入个数741 // H轴输入个数, VL切3维时退化为C轴输入个数
745- __local_mem__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 +742+ __ubuf__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 + vlLeftPadNum * strideOutVl;
746- vlLeftPadNum * strideOutVl;
747 idxPadOffset = curInOffset + i * strideInVlO1;743 idxPadOffset = curInOffset + i * strideInVlO1;
748 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,744 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,
749 curOutAddr, regIdx, idxPadOffset);745 curOutAddr, regIdx, idxPadOffset);
@@ -760,13 +756,12 @@ private:
760 for (uint16_t i = 0; i < vlO1InNum; i++) {756 for (uint16_t i = 0; i < vlO1InNum; i++) {
761 // H轴左pad757 // H轴左pad
762 uint32_t idxPadOffset = curInOffset + i * strideInVlO1 + leftPadInVlOffset;758 uint32_t idxPadOffset = curInOffset + i * strideInVlO1 + leftPadInVlOffset;
763- __local_mem__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;759+ __ubuf__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;
764 VlInCopyProc(leftPadLoops, lastLeftPadLoops, idxOffset, maskValue, lastLeftPadMaskValue, inAddr,760 VlInCopyProc(leftPadLoops, lastLeftPadLoops, idxOffset, maskValue, lastLeftPadMaskValue, inAddr,
765 curPadOutAddr, regIdx, idxPadOffset);761 curPadOutAddr, regIdx, idxPadOffset);
766 762 
767 // H轴输入有效个数763 // H轴输入有效个数
768- __local_mem__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 +764+ __ubuf__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 + vlLeftPadNum * strideOutVl;
769- vlLeftPadNum * strideOutVl;
770 idxPadOffset = curInOffset + i * strideInVlO1;765 idxPadOffset = curInOffset + i * strideInVlO1;
771 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,766 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,
772 curOutAddr, regIdx, idxPadOffset);767 curOutAddr, regIdx, idxPadOffset);
@@ -782,12 +777,11 @@ private:
782 curOutOffset = nIdx * strideOutN + vlO1LeftPadNum * strideOutVlO1 + vlO1InNum * strideOutVlO1;777 curOutOffset = nIdx * strideOutN + vlO1LeftPadNum * strideOutVlO1 + vlO1InNum * strideOutVlO1;
783 for (uint16_t i = 0; i < vlO1RightPadNum; i++) {778 for (uint16_t i = 0; i < vlO1RightPadNum; i++) {
784 uint32_t idxPadOffset = curInOffset + i * strideInVlO1 + leftPadInVlOffset;779 uint32_t idxPadOffset = curInOffset + i * strideInVlO1 + leftPadInVlOffset;
785- __local_mem__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;780+ __ubuf__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;
786 VlInCopyProc(leftPadLoops, lastLeftPadLoops, idxOffset, maskValue, lastLeftPadMaskValue, inAddr,781 VlInCopyProc(leftPadLoops, lastLeftPadLoops, idxOffset, maskValue, lastLeftPadMaskValue, inAddr,
787 curPadOutAddr, regIdx, idxPadOffset);782 curPadOutAddr, regIdx, idxPadOffset);
788 783 
789- __local_mem__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 +784+ __ubuf__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 + vlLeftPadNum * strideOutVl;
790- vlLeftPadNum * strideOutVl;
791 idxPadOffset = curInOffset + i * strideInVlO1;785 idxPadOffset = curInOffset + i * strideInVlO1;
792 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,786 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,
793 curOutAddr, regIdx, idxPadOffset);787 curOutAddr, regIdx, idxPadOffset);
Mconversion/pad_v3/op_kernel/arch35/pad_circular_huge_width.h+6-6
@@ -267,13 +267,13 @@ private:
267 __VEC_SCOPE__267 __VEC_SCOPE__
268 {268 {
269 AscendC::Reg::RegTensor<T> vReg;269 AscendC::Reg::RegTensor<T> vReg;
270- AscendC::Reg::UnalignReg uReg;270+ AscendC::Reg::UnalignRegForLoad uReg;
271- AscendC::Reg::UnalignReg uReg1;271+ AscendC::Reg::UnalignRegForStore uReg1;
272 272 
273- AscendC::Reg::DataCopyUnAlignPre(uReg, srcLeftDataAddr);273+ AscendC::Reg::LoadUnAlignPre(uReg, srcLeftDataAddr);
274- AscendC::Reg::DataCopyUnAlign(vReg, uReg, srcLeftDataAddr);274+ AscendC::Reg::LoadUnAlign(vReg, uReg, srcLeftDataAddr);
275- AscendC::Reg::DataCopyUnAlign(srcAddr, vReg, uReg1, leftUnalignLen);275+ AscendC::Reg::StoreUnAlign(srcAddr, vReg, uReg1, leftUnalignLen);
276- AscendC::Reg::DataCopyUnAlignPost(srcAddr, uReg1, 0);276+ AscendC::Reg::StoreUnAlignPost(srcAddr, uReg1, 0);
277 }277 }
278 }278 }
279 279 
Mconversion/pad_v3/op_kernel/arch35/pad_circular_normal_w.h+34-34
@@ -292,8 +292,8 @@ public:
292 PadCircNormalParam& padParam)292 PadCircNormalParam& padParam)
293 {293 {
294 const int8_t dimNum = tilingData_->dimNum;294 const int8_t dimNum = tilingData_->dimNum;
295- auto dstAddr = reinterpret_cast<__local_mem__ T*>(dst.GetPhyAddr());295+ auto dstAddr = reinterpret_cast<__ubuf__ T*>(dst.GetPhyAddr());
296- auto srcAddr = reinterpret_cast<__local_mem__ T*>(src.GetPhyAddr());296+ auto srcAddr = reinterpret_cast<__ubuf__ T*>(src.GetPhyAddr());
297 const uint32_t moveLen = tilingData_->leftPad[dimNum - 1];297 const uint32_t moveLen = tilingData_->leftPad[dimNum - 1];
298 const uint32_t InOffset = tilingData_->inShape[dimNum - 1] - tilingData_->leftPad[dimNum - 1];298 const uint32_t InOffset = tilingData_->inShape[dimNum - 1] - tilingData_->leftPad[dimNum - 1];
299 const uint16_t padVLNum = moveLen / VL_ELEMS;299 const uint16_t padVLNum = moveLen / VL_ELEMS;
@@ -306,20 +306,20 @@ public:
306 uint32_t endLen = padBLNum;306 uint32_t endLen = padBLNum;
307 endMask = AscendC::Reg::UpdateMask<T>(endLen);307 endMask = AscendC::Reg::UpdateMask<T>(endLen);
308 AscendC::Reg::RegTensor<T> vRegTmp;308 AscendC::Reg::RegTensor<T> vRegTmp;
309- AscendC::Reg::UnalignReg uReg;309+ AscendC::Reg::UnalignRegForLoad uReg;
310 AscendC::Reg::MaskReg maskAll = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();310 AscendC::Reg::MaskReg maskAll = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();
311 311 
312 for (uint16_t i = 0; i < padVLNum; i++) {312 for (uint16_t i = 0; i < padVLNum; i++) {
313 __ubuf__ T* Addr6 = srcAddr + InOffset + i * VL_ELEMS;313 __ubuf__ T* Addr6 = srcAddr + InOffset + i * VL_ELEMS;
314- AscendC::Reg::DataCopyUnAlignPre(uReg, Addr6);314+ AscendC::Reg::LoadUnAlignPre(uReg, Addr6);
315- AscendC::Reg::DataCopyUnAlign(vRegTmp, uReg, Addr6);315+ AscendC::Reg::LoadUnAlign(vRegTmp, uReg, Addr6);
316- AscendC::Reg::DataCopy(dstAddr + i * VL_ELEMS, vRegTmp, maskAll);316+ AscendC::Reg::StoreAlign(dstAddr + i * VL_ELEMS, vRegTmp, maskAll);
317 }317 }
318 for (uint16_t i = 0; i < BLNum; i++) {318 for (uint16_t i = 0; i < BLNum; i++) {
319 __ubuf__ T* Addr7 = srcAddr + InOffset + padVLNum * VL_ELEMS;319 __ubuf__ T* Addr7 = srcAddr + InOffset + padVLNum * VL_ELEMS;
320- AscendC::Reg::DataCopyUnAlignPre(uReg, Addr7);320+ AscendC::Reg::LoadUnAlignPre(uReg, Addr7);
321- AscendC::Reg::DataCopyUnAlign(vRegTmp, uReg, Addr7);321+ AscendC::Reg::LoadUnAlign(vRegTmp, uReg, Addr7);
322- AscendC::Reg::DataCopy(dstAddr + padVLNum * VL_ELEMS, vRegTmp, endMask);322+ AscendC::Reg::StoreAlign(dstAddr + padVLNum * VL_ELEMS, vRegTmp, endMask);
323 }323 }
324 }324 }
325 }325 }
@@ -331,7 +331,7 @@ public:
331 return;331 return;
332 }332 }
333 const int8_t dimNum = tilingData_->dimNum;333 const int8_t dimNum = tilingData_->dimNum;
334- auto dstAddr = reinterpret_cast<__local_mem__ T*>(dst.GetPhyAddr());334+ auto dstAddr = reinterpret_cast<__ubuf__ T*>(dst.GetPhyAddr());
335 const uint32_t InOffset = tilingData_->inShape[dimNum - 1] - tilingData_->leftPad[dimNum - 1];335 const uint32_t InOffset = tilingData_->inShape[dimNum - 1] - tilingData_->leftPad[dimNum - 1];
336 const uint16_t padVLNum = padParam.padLeft / VL_ELEMS;336 const uint16_t padVLNum = padParam.padLeft / VL_ELEMS;
337 const uint16_t padBLNum = padParam.padLeft % VL_ELEMS;337 const uint16_t padBLNum = padParam.padLeft % VL_ELEMS;
@@ -356,7 +356,7 @@ public:
356 uint32_t nolPadLen = VL_ELEMS - padBLNum;356 uint32_t nolPadLen = VL_ELEMS - padBLNum;
357 AscendC::Reg::MaskReg maskAll = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();357 AscendC::Reg::MaskReg maskAll = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();
358 lMask = AscendC::Reg::UpdateMask<T>(nolPadLen);358 lMask = AscendC::Reg::UpdateMask<T>(nolPadLen);
359- AscendC::Reg::MaskNot(lMask, lMask, maskAll);359+ AscendC::Reg::Not(lMask, lMask, maskAll);
360 360 
361 if constexpr (UB_AXES == CONST2) {361 if constexpr (UB_AXES == CONST2) {
362 for (uint16_t h = 0; h < dimHNum; h++) {362 for (uint16_t h = 0; h < dimHNum; h++) {
@@ -382,26 +382,26 @@ public:
382 }382 }
383 }383 }
384 384 
385- __aicore__ inline void PadLeftSideOne(__local_mem__ T* srcAddr, uint32_t firstOffset, uint32_t InOffset,385+ __aicore__ inline void PadLeftSideOne(__ubuf__ T* srcAddr, uint32_t firstOffset, uint32_t InOffset,
386 uint16_t padVLNum, uint16_t padBLNum, uint16_t BLNum, Reg::MaskReg endMask)386 uint16_t padVLNum, uint16_t padBLNum, uint16_t BLNum, Reg::MaskReg endMask)
387 {387 {
388 __VEC_SCOPE__388 __VEC_SCOPE__
389 {389 {
390 AscendC::Reg::RegTensor<T> vRegTmp;390 AscendC::Reg::RegTensor<T> vRegTmp;
391- AscendC::Reg::UnalignReg uReg;391+ AscendC::Reg::UnalignRegForLoad uReg;
392 AscendC::Reg::MaskReg maskAll = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();392 AscendC::Reg::MaskReg maskAll = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();
393 393 
394 for (uint16_t i = 0; i < padVLNum; i++) {394 for (uint16_t i = 0; i < padVLNum; i++) {
395 __ubuf__ T* Addr0 = srcAddr + firstOffset + InOffset + padBLNum + i * VL_ELEMS;395 __ubuf__ T* Addr0 = srcAddr + firstOffset + InOffset + padBLNum + i * VL_ELEMS;
396- AscendC::Reg::DataCopyUnAlignPre(uReg, Addr0);396+ AscendC::Reg::LoadUnAlignPre(uReg, Addr0);
397- AscendC::Reg::DataCopyUnAlign(vRegTmp, uReg, Addr0);397+ AscendC::Reg::LoadUnAlign(vRegTmp, uReg, Addr0);
398- AscendC::Reg::DataCopy(srcAddr + firstOffset - (padVLNum - i) * VL_ELEMS, vRegTmp, maskAll);398+ AscendC::Reg::StoreAlign(srcAddr + firstOffset - (padVLNum - i) * VL_ELEMS, vRegTmp, maskAll);
399 }399 }
400 for (uint16_t i = 0; i < BLNum; i++) {400 for (uint16_t i = 0; i < BLNum; i++) {
401 __ubuf__ T* Addr2 = srcAddr + firstOffset + InOffset + padBLNum - VL_ELEMS;401 __ubuf__ T* Addr2 = srcAddr + firstOffset + InOffset + padBLNum - VL_ELEMS;
402- AscendC::Reg::DataCopyUnAlignPre(uReg, Addr2);402+ AscendC::Reg::LoadUnAlignPre(uReg, Addr2);
403- AscendC::Reg::DataCopyUnAlign(vRegTmp, uReg, Addr2);403+ AscendC::Reg::LoadUnAlign(vRegTmp, uReg, Addr2);
404- AscendC::Reg::DataCopy(srcAddr + firstOffset - (padVLNum + 1) * VL_ELEMS, vRegTmp, endMask);404+ AscendC::Reg::StoreAlign(srcAddr + firstOffset - (padVLNum + 1) * VL_ELEMS, vRegTmp, endMask);
405 }405 }
406 }406 }
407 }407 }
@@ -412,7 +412,7 @@ public:
412 return;412 return;
413 }413 }
414 const int8_t dimNum = tilingData_->dimNum;414 const int8_t dimNum = tilingData_->dimNum;
415- auto dstAddr = reinterpret_cast<__local_mem__ T*>(dst.GetPhyAddr());415+ auto dstAddr = reinterpret_cast<__ubuf__ T*>(dst.GetPhyAddr());
416 const uint32_t OutOffset = tilingData_->inShape[dimNum - 1];416 const uint32_t OutOffset = tilingData_->inShape[dimNum - 1];
417 const uint16_t padVLNum = padParam.padRight / VL_ELEMS;417 const uint16_t padVLNum = padParam.padRight / VL_ELEMS;
418 const uint16_t padBLNum = padParam.padRight % VL_ELEMS;418 const uint16_t padBLNum = padParam.padRight % VL_ELEMS;
@@ -451,27 +451,27 @@ public:
451 }451 }
452 }452 }
453 453 
454- __aicore__ inline void PadRightSideOne(__local_mem__ T* srcAddr, uint32_t firstOffset, uint32_t OutOffset,454+ __aicore__ inline void PadRightSideOne(__ubuf__ T* srcAddr, uint32_t firstOffset, uint32_t OutOffset,
455 uint16_t padVLNum, uint16_t padBLNum, uint16_t BLNum)455 uint16_t padVLNum, uint16_t padBLNum, uint16_t BLNum)
456 {456 {
457 __VEC_SCOPE__457 __VEC_SCOPE__
458 {458 {
459 AscendC::Reg::RegTensor<T> vRegTmp;459 AscendC::Reg::RegTensor<T> vRegTmp;
460- AscendC::Reg::UnalignReg uReg;460+ AscendC::Reg::UnalignRegForStore uReg;
461 uint32_t padLen = padBLNum;461 uint32_t padLen = padBLNum;
462 uint32_t allLen = VL_ELEMS;462 uint32_t allLen = VL_ELEMS;
463 463 
464 for (uint16_t i = 0; i < padVLNum; i++) {464 for (uint16_t i = 0; i < padVLNum; i++) {
465 __ubuf__ T* Addr3 = srcAddr + firstOffset + OutOffset + i * VL_ELEMS;465 __ubuf__ T* Addr3 = srcAddr + firstOffset + OutOffset + i * VL_ELEMS;
466- AscendC::Reg::DataCopy(vRegTmp, srcAddr + firstOffset + i * VL_ELEMS);466+ AscendC::Reg::LoadAlign(vRegTmp, srcAddr + firstOffset + i * VL_ELEMS);
467- AscendC::Reg::DataCopyUnAlign(Addr3, vRegTmp, uReg, allLen);467+ AscendC::Reg::StoreUnAlign(Addr3, vRegTmp, uReg, allLen);
468- AscendC::Reg::DataCopyUnAlignPost(Addr3, uReg, 0);468+ AscendC::Reg::StoreUnAlignPost(Addr3, uReg, 0);
469 }469 }
470 for (uint16_t i = 0; i < BLNum; i++) {470 for (uint16_t i = 0; i < BLNum; i++) {
471 __ubuf__ T* Addr4 = srcAddr + firstOffset + OutOffset + padVLNum * VL_ELEMS;471 __ubuf__ T* Addr4 = srcAddr + firstOffset + OutOffset + padVLNum * VL_ELEMS;
472- AscendC::Reg::DataCopy(vRegTmp, srcAddr + firstOffset + padVLNum * VL_ELEMS);472+ AscendC::Reg::LoadAlign(vRegTmp, srcAddr + firstOffset + padVLNum * VL_ELEMS);
473- AscendC::Reg::DataCopyUnAlign(Addr4, vRegTmp, uReg, padLen);473+ AscendC::Reg::StoreUnAlign(Addr4, vRegTmp, uReg, padLen);
474- AscendC::Reg::DataCopyUnAlignPost(Addr4, uReg, 0);474+ AscendC::Reg::StoreUnAlignPost(Addr4, uReg, 0);
475 }475 }
476 }476 }
477 }477 }
@@ -481,7 +481,7 @@ public:
481 {481 {
482 const int8_t ubAxis = tilingData_->ubAxis;482 const int8_t ubAxis = tilingData_->ubAxis;
483 const int8_t dimNum = tilingData_->dimNum;483 const int8_t dimNum = tilingData_->dimNum;
484- auto dstAddr = reinterpret_cast<__local_mem__ T*>(dst.GetPhyAddr());484+ auto dstAddr = reinterpret_cast<__ubuf__ T*>(dst.GetPhyAddr());
485 const uint32_t padHW = padParam.padStride[curAxis - ubAxis - 1];485 const uint32_t padHW = padParam.padStride[curAxis - ubAxis - 1];
486 const uint32_t padCHW = (curAxis - ubAxis <= 1) ? 0 : padParam.padStride[curAxis - ubAxis - 2];486 const uint32_t padCHW = (curAxis - ubAxis <= 1) ? 0 : padParam.padStride[curAxis - ubAxis - 2];
487 const uint32_t padW = padParam.padStride[curAxis - ubAxis];487 const uint32_t padW = padParam.padStride[curAxis - ubAxis];
@@ -514,13 +514,13 @@ public:
514 for (uint16_t c = 0; c < dimCNum; c++) {514 for (uint16_t c = 0; c < dimCNum; c++) {
515 uint32_t tempOffset = startOffset + c * padHW + n * padCHW;515 uint32_t tempOffset = startOffset + c * padHW + n * padCHW;
516 for (uint16_t i = 0; i < padVLNum; i++) {516 for (uint16_t i = 0; i < padVLNum; i++) {
517- AscendC::Reg::DataCopy(vRegTmp, dstAddr + tempOffset + InOffset + i * VL_ELEMS);517+ AscendC::Reg::LoadAlign(vRegTmp, dstAddr + tempOffset + InOffset + i * VL_ELEMS);
518- AscendC::Reg::DataCopy(dstAddr + tempOffset + OutOffset + i * VL_ELEMS, vRegTmp, maskAll);518+ AscendC::Reg::StoreAlign(dstAddr + tempOffset + OutOffset + i * VL_ELEMS, vRegTmp, maskAll);
519 }519 }
520 for (uint16_t i = 0; i < BLNum; i++) {520 for (uint16_t i = 0; i < BLNum; i++) {
521- AscendC::Reg::DataCopy(vRegTmp, dstAddr + tempOffset + InOffset + padVLNum * VL_ELEMS);521+ AscendC::Reg::LoadAlign(vRegTmp, dstAddr + tempOffset + InOffset + padVLNum * VL_ELEMS);
522- AscendC::Reg::DataCopy(dstAddr + tempOffset + OutOffset + padVLNum * VL_ELEMS, vRegTmp,522+ AscendC::Reg::StoreAlign(dstAddr + tempOffset + OutOffset + padVLNum * VL_ELEMS, vRegTmp,
523- endMask);523+ endMask);
524 }524 }
525 }525 }
526 }526 }
Mconversion/pad_v3/op_kernel/arch35/pad_edge_gather.h+99-106
@@ -253,8 +253,8 @@ private:
253 RangeType lastDimIdx = lastInDimSize - 1;253 RangeType lastDimIdx = lastInDimSize - 1;
254 RangeType last2DimIdx = lastSecInDimSize - 1;254 RangeType last2DimIdx = lastSecInDimSize - 1;
255 255 
256- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();256+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
257- __local_mem__ RangeType* idxAddr2 = (__local_mem__ RangeType*)idxTensor.GetPhyAddr() + VL_RANGE_CNT;257+ __ubuf__ RangeType* idxAddr2 = (__ubuf__ RangeType*)idxTensor.GetPhyAddr() + VL_RANGE_CNT;
258 258 
259 __VEC_SCOPE__259 __VEC_SCOPE__
260 {260 {
@@ -266,72 +266,72 @@ private:
266 Reg::RegTensor<RangeType> leftPadIdxReg;266 Reg::RegTensor<RangeType> leftPadIdxReg;
267 Reg::MaskReg rightMask;267 Reg::MaskReg rightMask;
268 Reg::RegTensor<RangeType> rightPadIdxReg;268 Reg::RegTensor<RangeType> rightPadIdxReg;
269- Reg::UnalignReg uReg;269+ Reg::UnalignRegForStore uReg;
270- Reg::UnalignReg uRegIn;270+ Reg::UnalignRegForLoad uRegIn;
271 271 
272 // 先拼好-1轴的索引272 // 先拼好-1轴的索引
273 Reg::Arange(lineRange, 0);273 Reg::Arange(lineRange, 0);
274 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);274 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);
275- Reg::CompareScalar<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);275+ Reg::Compares<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);
276 Reg::Duplicate(leftPadIdxReg, 0);276 Reg::Duplicate(leftPadIdxReg, 0);
277- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);277+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);
278- Reg::CompareScalar<RangeType, CMPMODE::GT>(rightMask, lineRange, lastDimIdx, maskIdx);278+ Reg::Compares<RangeType, CMPMODE::GT>(rightMask, lineRange, lastDimIdx, maskIdx);
279 Reg::Duplicate(rightPadIdxReg, lastDimIdx);279 Reg::Duplicate(rightPadIdxReg, lastDimIdx);
280- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);280+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);
281 281 
282 // -3轴纯pad的索引, 包含末尾两根轴282 // -3轴纯pad的索引, 包含末尾两根轴
283 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {283 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {
284 // -2轴leftpad行数, 索引都一样284 // -2轴leftpad行数, 索引都一样
285- __local_mem__ RangeType* idxAddrTmp = idxAddr + i * outStride1;285+ __ubuf__ RangeType* idxAddrTmp = idxAddr + i * outStride1;
286 for (uint16_t j = 0; j < last2LeftPadNum; j++) {286 for (uint16_t j = 0; j < last2LeftPadNum; j++) {
287- Reg::DataCopyUnAlign(idxAddrTmp, lineRange, uReg, outStride2);287+ Reg::StoreUnAlign(idxAddrTmp, lineRange, uReg, outStride2);
288 }288 }
289- Reg::DataCopyUnAlignPost(idxAddrTmp, uReg, 0);289+ Reg::StoreUnAlignPost(idxAddrTmp, uReg, 0);
290 290 
291 // -2 轴inputshape, 索引递增291 // -2 轴inputshape, 索引递增
292- __local_mem__ RangeType* idxAddrTmp1 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2;292+ __ubuf__ RangeType* idxAddrTmp1 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2;
293 for (uint16_t j = 0; j < lastSecInDimSize; j++) {293 for (uint16_t j = 0; j < lastSecInDimSize; j++) {
294 Reg::Adds(lineRangeNew, lineRange, (RangeType)(j * lastInDimSize), maskIdx);294 Reg::Adds(lineRangeNew, lineRange, (RangeType)(j * lastInDimSize), maskIdx);
295- Reg::DataCopyUnAlign(idxAddrTmp1, lineRangeNew, uReg, outStride2);295+ Reg::StoreUnAlign(idxAddrTmp1, lineRangeNew, uReg, outStride2);
296 }296 }
297- Reg::DataCopyUnAlignPost(idxAddrTmp1, uReg, 0);297+ Reg::StoreUnAlignPost(idxAddrTmp1, uReg, 0);
298 298 
299 // -2轴rightpad行数, 索引都一样299 // -2轴rightpad行数, 索引都一样
300 Reg::Adds(lineRangeNew, lineRange, (RangeType)(last2DimIdx * lastInDimSize), maskIdx);300 Reg::Adds(lineRangeNew, lineRange, (RangeType)(last2DimIdx * lastInDimSize), maskIdx);
301- __local_mem__ RangeType* idxAddrTmp2 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2 +301+ __ubuf__ RangeType* idxAddrTmp2 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2 +
302- lastSecInDimSize * outStride2;302+ lastSecInDimSize * outStride2;
303 for (uint16_t j = 0; j < last2RightPadNum; j++) {303 for (uint16_t j = 0; j < last2RightPadNum; j++) {
304- Reg::DataCopyUnAlign(idxAddrTmp2, lineRangeNew, uReg, outStride2);304+ Reg::StoreUnAlign(idxAddrTmp2, lineRangeNew, uReg, outStride2);
305 }305 }
306- Reg::DataCopyUnAlignPost(idxAddrTmp2, uReg, 0);306+ Reg::StoreUnAlignPost(idxAddrTmp2, uReg, 0);
307 }307 }
308 308 
309 // -3轴有效输入的索引309 // -3轴有效输入的索引
310 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {310 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {
311 Reg::Adds(lineRangeBk, lineRange, (RangeType)(i * inStride1), maskIdx);311 Reg::Adds(lineRangeBk, lineRange, (RangeType)(i * inStride1), maskIdx);
312 // -2轴leftpad行数, 索引都一样312 // -2轴leftpad行数, 索引都一样
313- __local_mem__ RangeType* idxAddrTmp = idxAddr2 + i * outStride1;313+ __ubuf__ RangeType* idxAddrTmp = idxAddr2 + i * outStride1;
314 for (uint16_t j = 0; j < last2LeftPadNum; j++) {314 for (uint16_t j = 0; j < last2LeftPadNum; j++) {
315- Reg::DataCopyUnAlign(idxAddrTmp, lineRangeBk, uReg, outStride2);315+ Reg::StoreUnAlign(idxAddrTmp, lineRangeBk, uReg, outStride2);
316 }316 }
317- Reg::DataCopyUnAlignPost(idxAddrTmp, uReg, 0);317+ Reg::StoreUnAlignPost(idxAddrTmp, uReg, 0);
318 318 
319 // -2 轴inputshape, 索引递增319 // -2 轴inputshape, 索引递增
320- __local_mem__ RangeType* idxAddrTmp1 = idxAddr2 + i * outStride1 + last2LeftPadNum * outStride2;320+ __ubuf__ RangeType* idxAddrTmp1 = idxAddr2 + i * outStride1 + last2LeftPadNum * outStride2;
321 for (uint16_t j = 0; j < lastSecInDimSize; j++) {321 for (uint16_t j = 0; j < lastSecInDimSize; j++) {
322 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(j * lastInDimSize), maskIdx);322 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(j * lastInDimSize), maskIdx);
323- Reg::DataCopyUnAlign(idxAddrTmp1, lineRangeNew, uReg, outStride2);323+ Reg::StoreUnAlign(idxAddrTmp1, lineRangeNew, uReg, outStride2);
324 }324 }
325- Reg::DataCopyUnAlignPost(idxAddrTmp1, uReg, 0);325+ Reg::StoreUnAlignPost(idxAddrTmp1, uReg, 0);
326 326 
327 // -2轴rightpad行数, 索引都一样327 // -2轴rightpad行数, 索引都一样
328 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(last2DimIdx * lastInDimSize), maskIdx);328 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(last2DimIdx * lastInDimSize), maskIdx);
329- __local_mem__ RangeType* idxAddrTmp2 = idxAddr2 + i * outStride1 + last2LeftPadNum * outStride2 +329+ __ubuf__ RangeType* idxAddrTmp2 = idxAddr2 + i * outStride1 + last2LeftPadNum * outStride2 +
330- lastSecInDimSize * outStride2;330+ lastSecInDimSize * outStride2;
331 for (uint16_t j = 0; j < last2RightPadNum; j++) {331 for (uint16_t j = 0; j < last2RightPadNum; j++) {
332- Reg::DataCopyUnAlign(idxAddrTmp2, lineRangeNew, uReg, outStride2);332+ Reg::StoreUnAlign(idxAddrTmp2, lineRangeNew, uReg, outStride2);
333 }333 }
334- Reg::DataCopyUnAlignPost(idxAddrTmp2, uReg, 0);334+ Reg::StoreUnAlignPost(idxAddrTmp2, uReg, 0);
335 }335 }
336 }336 }
337 }337 }
@@ -344,8 +344,8 @@ private:
344 uint32_t lastOutDimSize = tdPtrGather_->outShape[dimNum_ - 1];344 uint32_t lastOutDimSize = tdPtrGather_->outShape[dimNum_ - 1];
345 uint16_t lastDimsLeft = vlSplitInEdgeGather_;345 uint16_t lastDimsLeft = vlSplitInEdgeGather_;
346 RangeType lastDimIdx = lastInDimSize - 1;346 RangeType lastDimIdx = lastInDimSize - 1;
347- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();347+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
348- __local_mem__ RangeType* idxAddr2 = (__local_mem__ RangeType*)idxTensor.GetPhyAddr() + VL_RANGE_CNT;348+ __ubuf__ RangeType* idxAddr2 = (__ubuf__ RangeType*)idxTensor.GetPhyAddr() + VL_RANGE_CNT;
349 349 
350 __VEC_SCOPE__350 __VEC_SCOPE__
351 {351 {
@@ -356,53 +356,52 @@ private:
356 Reg::RegTensor<RangeType> leftPadIdxReg;356 Reg::RegTensor<RangeType> leftPadIdxReg;
357 Reg::MaskReg rightMask;357 Reg::MaskReg rightMask;
358 Reg::RegTensor<RangeType> rightPadIdxReg;358 Reg::RegTensor<RangeType> rightPadIdxReg;
359- Reg::UnalignReg uReg;359+ Reg::UnalignRegForStore uReg;
360- Reg::UnalignReg uRegIn;360+ Reg::UnalignRegForStore uRegIn;
361 361 
362 // 先拼好-1轴的索引362 // 先拼好-1轴的索引
363 Reg::Arange(lineRange, 0);363 Reg::Arange(lineRange, 0);
364 // 先拷出去，防止索引尾部脏数据364 // 先拷出去，防止索引尾部脏数据
365- Reg::DataCopy(idxAddr, lineRange, maskIdx);365+ Reg::StoreAlign(idxAddr, lineRange, maskIdx);
366- Reg::DataCopy(idxAddr2, lineRange, maskIdx);366+ Reg::StoreAlign(idxAddr2, lineRange, maskIdx);
367 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();367 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();
368 368 
369 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);369 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);
370- Reg::CompareScalar<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);370+ Reg::Compares<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);
371 Reg::Duplicate(leftPadIdxReg, (RangeType)0);371 Reg::Duplicate(leftPadIdxReg, (RangeType)0);
372- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);372+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);
373 373 
374- Reg::CompareScalar<RangeType, CMPMODE::GT>(rightMask, lineRange, lastDimIdx, maskIdx);374+ Reg::Compares<RangeType, CMPMODE::GT>(rightMask, lineRange, lastDimIdx, maskIdx);
375 Reg::Duplicate(rightPadIdxReg, lastDimIdx);375 Reg::Duplicate(rightPadIdxReg, lastDimIdx);
376- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);376+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);
377 377 
378 // -2轴leftpad行数, 索引都一样378 // -2轴leftpad行数, 索引都一样
379- __local_mem__ RangeType* idxAddrTmp = idxAddr;379+ __ubuf__ RangeType* idxAddrTmp = idxAddr;
380 for (uint16_t i = 0; i < lastDimsLeft; i++) {380 for (uint16_t i = 0; i < lastDimsLeft; i++) {
381- Reg::DataCopyUnAlign(idxAddrTmp, lineRange, uReg, lastOutDimSize);381+ Reg::StoreUnAlign(idxAddrTmp, lineRange, uReg, lastOutDimSize);
382 }382 }
383- Reg::DataCopyUnAlignPost(idxAddrTmp, uReg, 0);383+ Reg::StoreUnAlignPost(idxAddrTmp, uReg, 0);
384 384 
385 // -2轴有效输入的索引385 // -2轴有效输入的索引
386- __local_mem__ RangeType* idxAddrTmp2 = idxAddr2;386+ __ubuf__ RangeType* idxAddrTmp2 = idxAddr2;
387 for (uint16_t i = 0; i < lastDimsLeft; i++) {387 for (uint16_t i = 0; i < lastDimsLeft; i++) {
388 RangeType loopStride = (RangeType)lastInDimSize * i;388 RangeType loopStride = (RangeType)lastInDimSize * i;
389 Reg::Adds(lineRangeNew, lineRange, loopStride, maskIdx);389 Reg::Adds(lineRangeNew, lineRange, loopStride, maskIdx);
390- Reg::DataCopyUnAlign(idxAddrTmp2, lineRangeNew, uRegIn, lastOutDimSize);390+ Reg::StoreUnAlign(idxAddrTmp2, lineRangeNew, uRegIn, lastOutDimSize);
391 }391 }
392- Reg::DataCopyUnAlignPost(idxAddrTmp2, uRegIn, 0);392+ Reg::StoreUnAlignPost(idxAddrTmp2, uRegIn, 0);
393 }393 }
394 }394 }
395 395 
396 __aicore__ inline void VlInCopyProc(uint16_t inLoops, uint16_t lastInLoops, RangeType idxOffset, uint32_t maskValue,396 __aicore__ inline void VlInCopyProc(uint16_t inLoops, uint16_t lastInLoops, RangeType idxOffset, uint32_t maskValue,
397- uint32_t lastInMaskValue, __local_mem__ T* curInAddr,397+ uint32_t lastInMaskValue, __ubuf__ T* curInAddr, __ubuf__ T* curOutAddr,
398- __local_mem__ T* curOutAddr, Reg::RegTensor<RangeType>& regIdx,398+ Reg::RegTensor<RangeType>& regIdx, uint32_t idxPadOffset)
399- uint32_t idxPadOffset)
400 {399 {
401 Reg::RegTensor<T> regData;400 Reg::RegTensor<T> regData;
402 Reg::RegTensor<T> regDataT;401 Reg::RegTensor<T> regDataT;
403 Reg::RegTensor<RangeType> regIdxBk;402 Reg::RegTensor<RangeType> regIdxBk;
404 Reg::RegTensor<RangeType> regNewIdx;403 Reg::RegTensor<RangeType> regNewIdx;
405- Reg::UnalignReg uReg;404+ Reg::UnalignRegForStore uReg;
406 Reg::MaskReg maskAll = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();405 Reg::MaskReg maskAll = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();
407 uint32_t validMask = maskValue;406 uint32_t validMask = maskValue;
408 if constexpr (sizeof(T) == 8) {407 if constexpr (sizeof(T) == 8) {
@@ -410,45 +409,43 @@ private:
410 }409 }
411 Reg::MaskReg maskIdx = Reg::UpdateMask<RangeType>(validMask);410 Reg::MaskReg maskIdx = Reg::UpdateMask<RangeType>(validMask);
412 411 
413- __local_mem__ T* outAddrTmp = curOutAddr;412+ __ubuf__ T* outAddrTmp = curOutAddr;
414 Reg::Adds(regIdxBk, regIdx, idxPadOffset, maskIdx);413 Reg::Adds(regIdxBk, regIdx, idxPadOffset, maskIdx);
415 for (uint16_t cpIdx = 0; cpIdx < inLoops; cpIdx++) {414 for (uint16_t cpIdx = 0; cpIdx < inLoops; cpIdx++) {
416 Reg::Adds(regNewIdx, regIdxBk, cpIdx * idxOffset, maskIdx);415 Reg::Adds(regNewIdx, regIdxBk, cpIdx * idxOffset, maskIdx);
417- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx,416+ Reg::Gather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx, maskIdx);
418- maskIdx);
419 if constexpr (sizeof(T) != 1) {417 if constexpr (sizeof(T) != 1) {
420- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, maskValue);418+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, maskValue);
421 } else {419 } else {
422 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);420 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
423- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, maskValue);421+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, maskValue);
424 }422 }
425 }423 }
426- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);424+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
427 for (uint16_t cpTailIdx = 0; cpTailIdx < lastInLoops; cpTailIdx++) {425 for (uint16_t cpTailIdx = 0; cpTailIdx < lastInLoops; cpTailIdx++) {
428 outAddrTmp = curOutAddr + inLoops * maskValue;426 outAddrTmp = curOutAddr + inLoops * maskValue;
429 Reg::Adds(regNewIdx, regIdxBk, inLoops * idxOffset, maskIdx);427 Reg::Adds(regNewIdx, regIdxBk, inLoops * idxOffset, maskIdx);
430- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx,428+ Reg::Gather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx, maskIdx);
431- maskIdx);
432 if constexpr (sizeof(T) != 1) {429 if constexpr (sizeof(T) != 1) {
433- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, lastInMaskValue);430+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, lastInMaskValue);
434 } else {431 } else {
435 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);432 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
436- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, lastInMaskValue);433+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, lastInMaskValue);
437 }434 }
438- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);435+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
439 }436 }
440 }437 }
441 438 
442 // gather一次，copy多次439 // gather一次，copy多次
443 __aicore__ inline void VlPaddingCopyProc(uint16_t gatherLoops, uint16_t padLoops, uint16_t lastPadLoops,440 __aicore__ inline void VlPaddingCopyProc(uint16_t gatherLoops, uint16_t padLoops, uint16_t lastPadLoops,
444- uint32_t maskValue, uint32_t lastPadMaskValue,441+ uint32_t maskValue, uint32_t lastPadMaskValue, __ubuf__ T* curPadInAddr,
445- __local_mem__ T* curPadInAddr, __local_mem__ T* curPadOutAddr,442+ __ubuf__ T* curPadOutAddr, Reg::RegTensor<RangeType>& regIdxPad,
446- Reg::RegTensor<RangeType>& regIdxPad, uint32_t idxPadOffset)443+ uint32_t idxPadOffset)
447 {444 {
448 Reg::RegTensor<T> regData;445 Reg::RegTensor<T> regData;
449 Reg::RegTensor<T> regDataT;446 Reg::RegTensor<T> regDataT;
450 Reg::RegTensor<RangeType> regNewIdx;447 Reg::RegTensor<RangeType> regNewIdx;
451- Reg::UnalignReg uReg;448+ Reg::UnalignRegForStore uReg;
452 Reg::MaskReg maskAll = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();449 Reg::MaskReg maskAll = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();
453 uint32_t validMask = maskValue;450 uint32_t validMask = maskValue;
454 if constexpr (sizeof(T) == 8) {451 if constexpr (sizeof(T) == 8) {
@@ -459,27 +456,26 @@ private:
459 for (uint16_t gIdx = 0; gIdx < gatherLoops; gIdx++) {456 for (uint16_t gIdx = 0; gIdx < gatherLoops; gIdx++) {
460 Reg::Adds(regNewIdx, regIdxPad, idxPadOffset, maskIdx);457 Reg::Adds(regNewIdx, regIdxPad, idxPadOffset, maskIdx);
461 // gather一次，copy多次458 // gather一次，copy多次
462- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, curPadInAddr, (Reg::RegTensor<IdxType>&)regNewIdx,459+ Reg::Gather((Reg::RegTensor<CastType>&)regData, curPadInAddr, (Reg::RegTensor<IdxType>&)regNewIdx, maskIdx);
463- maskIdx);460+ __ubuf__ T* outAddrTmp = curPadOutAddr;
464- __local_mem__ T* outAddrTmp = curPadOutAddr;
465 for (uint16_t pIdx = 0; pIdx < padLoops; pIdx++) {461 for (uint16_t pIdx = 0; pIdx < padLoops; pIdx++) {
466 if constexpr (sizeof(T) != 1) {462 if constexpr (sizeof(T) != 1) {
467- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, maskValue);463+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, maskValue);
468 } else {464 } else {
469 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);465 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
470- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, maskValue);466+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, maskValue);
471 }467 }
472 }468 }
473- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);469+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
474 for (uint16_t pTaiIdx = 0; pTaiIdx < lastPadLoops; pTaiIdx++) {470 for (uint16_t pTaiIdx = 0; pTaiIdx < lastPadLoops; pTaiIdx++) {
475 outAddrTmp = curPadOutAddr + padLoops * maskValue;471 outAddrTmp = curPadOutAddr + padLoops * maskValue;
476 if constexpr (sizeof(T) != 1) {472 if constexpr (sizeof(T) != 1) {
477- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, lastPadMaskValue);473+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, lastPadMaskValue);
478 } else {474 } else {
479 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);475 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
480- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, lastPadMaskValue);476+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, lastPadMaskValue);
481 }477 }
482- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);478+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
483 }479 }
484 }480 }
485 }481 }
@@ -488,14 +484,14 @@ private:
488 LocalTensor<T>& outTensor, uint32_t ubAxisInCopyNum,484 LocalTensor<T>& outTensor, uint32_t ubAxisInCopyNum,
489 uint32_t ubAxisLeftPadNum, uint32_t ubAxisRightPadNum)485 uint32_t ubAxisLeftPadNum, uint32_t ubAxisRightPadNum)
490 {486 {
491- __local_mem__ RangeType* idxPadAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();487+ __ubuf__ RangeType* idxPadAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
492- __local_mem__ RangeType* idxAddr = idxPadAddr + VL_RANGE_CNT;488+ __ubuf__ RangeType* idxAddr = idxPadAddr + VL_RANGE_CNT;
493- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();489+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
494- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr();490+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr();
495 491 
496 // ubAxisInCopyNum 可能是0492 // ubAxisInCopyNum 可能是0
497- __local_mem__ T* outAddrValidIn = outAddr + tdPtrGather_->outStride[dimNum_ - CONST2] * ubAxisLeftPadNum;493+ __ubuf__ T* outAddrValidIn = outAddr + tdPtrGather_->outStride[dimNum_ - CONST2] * ubAxisLeftPadNum;
498- __local_mem__ T* outAddrDupRight = outAddrValidIn + tdPtrGather_->outStride[dimNum_ - CONST2] * ubAxisInCopyNum;494+ __ubuf__ T* outAddrDupRight = outAddrValidIn + tdPtrGather_->outStride[dimNum_ - CONST2] * ubAxisInCopyNum;
499 495 
500 uint32_t vlSplitLoopIn = vlSplitInEdgeGather_;496 uint32_t vlSplitLoopIn = vlSplitInEdgeGather_;
501 if constexpr (sizeof(T) == 1) {497 if constexpr (sizeof(T) == 1) {
@@ -532,8 +528,8 @@ private:
532 {528 {
533 Reg::RegTensor<RangeType> regIdxPad;529 Reg::RegTensor<RangeType> regIdxPad;
534 Reg::RegTensor<RangeType> regIdx;530 Reg::RegTensor<RangeType> regIdx;
535- Reg::DataCopy(regIdxPad, idxPadAddr);531+ Reg::LoadAlign(regIdxPad, idxPadAddr);
536- Reg::DataCopy(regIdx, idxAddr);532+ Reg::LoadAlign(regIdx, idxAddr);
537 533 
538 // 该次Ub内H轴左pad534 // 该次Ub内H轴左pad
539 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue, inAddr,535 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue, inAddr,
@@ -554,10 +550,10 @@ private:
554 LocalTensor<T>& outTensor, uint32_t ubAxisInCopyNum,550 LocalTensor<T>& outTensor, uint32_t ubAxisInCopyNum,
555 uint32_t ubAxisLeftPadNum, uint32_t ubAxisRightPadNum)551 uint32_t ubAxisLeftPadNum, uint32_t ubAxisRightPadNum)
556 {552 {
557- __local_mem__ RangeType* idxPadAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();553+ __ubuf__ RangeType* idxPadAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
558- __local_mem__ RangeType* idxAddr = idxPadAddr + VL_RANGE_CNT;554+ __ubuf__ RangeType* idxAddr = idxPadAddr + VL_RANGE_CNT;
559- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();555+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
560- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr();556+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr();
561 557 
562 uint32_t vlSplitLoopIn = vlSplitInEdgeGather_;558 uint32_t vlSplitLoopIn = vlSplitInEdgeGather_;
563 if constexpr (sizeof(T) == 1) {559 if constexpr (sizeof(T) == 1) {
@@ -623,18 +619,18 @@ private:
623 {619 {
624 Reg::RegTensor<RangeType> regIdxPad;620 Reg::RegTensor<RangeType> regIdxPad;
625 Reg::RegTensor<RangeType> regIdx;621 Reg::RegTensor<RangeType> regIdx;
626- Reg::DataCopy(regIdxPad, idxPadAddr);622+ Reg::LoadAlign(regIdxPad, idxPadAddr);
627- Reg::DataCopy(regIdx, idxAddr);623+ Reg::LoadAlign(regIdx, idxAddr);
628 624 
629 // 该次Ub内C轴左pad, VL切3维时退化为1625 // 该次Ub内C轴左pad, VL切3维时退化为1
630 for (uint16_t ulIdx = 0; ulIdx < ubAxisLeftPadLoops; ulIdx++) {626 for (uint16_t ulIdx = 0; ulIdx < ubAxisLeftPadLoops; ulIdx++) {
631 // H轴左pad，VL切3维时退化为该次Ub内C轴左pad627 // H轴左pad，VL切3维时退化为该次Ub内C轴左pad
632- __local_mem__ T* curPadOutAddr = outAddr + ulIdx * strideOutVlO1;628+ __ubuf__ T* curPadOutAddr = outAddr + ulIdx * strideOutVlO1;
633 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,629 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,
634 inAddr, curPadOutAddr, regIdxPad, 0);630 inAddr, curPadOutAddr, regIdxPad, 0);
635 631 
636 // H轴上的输入，VL切3维时退化为该次Ub内C轴有效输入632 // H轴上的输入，VL切3维时退化为该次Ub内C轴有效输入
637- __local_mem__ T* curOutAddr = outAddr + ulIdx * strideOutVlO1 + vlLeftPadNum * strideOutVl;633+ __ubuf__ T* curOutAddr = outAddr + ulIdx * strideOutVlO1 + vlLeftPadNum * strideOutVl;
638 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,634 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,
639 curOutAddr, regIdx, 0);635 curOutAddr, regIdx, 0);
640 636 
@@ -648,7 +644,7 @@ private:
648 for (uint16_t uiIdx = 0; uiIdx < ubAxisInCopyLoops; uiIdx++) {644 for (uint16_t uiIdx = 0; uiIdx < ubAxisInCopyLoops; uiIdx++) {
649 // H轴左pad645 // H轴左pad
650 uint32_t idxPadOffset = uiIdx * strideInVlO1;646 uint32_t idxPadOffset = uiIdx * strideInVlO1;
651- __local_mem__ T* curInOutAddr = outAddr + ubAxisLeftPadLoops * strideOutVlO1 + uiIdx * strideOutVlO1;647+ __ubuf__ T* curInOutAddr = outAddr + ubAxisLeftPadLoops * strideOutVlO1 + uiIdx * strideOutVlO1;
652 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,648 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,
653 inAddr, curInOutAddr, regIdxPad, idxPadOffset);649 inAddr, curInOutAddr, regIdxPad, idxPadOffset);
654 650 
@@ -670,8 +666,8 @@ private:
670 for (uint16_t urIdx = 0; urIdx < ubAxisRightPadLoops; urIdx++) {666 for (uint16_t urIdx = 0; urIdx < ubAxisRightPadLoops; urIdx++) {
671 // H轴左pad667 // H轴左pad
672 uint32_t idxPadOffset = rightPadInVlO1Offset;668 uint32_t idxPadOffset = rightPadInVlO1Offset;
673- __local_mem__ T* curPadOutAddr = outAddr + ubAxisLeftPadLoops * strideOutVlO1 +669+ __ubuf__ T* curPadOutAddr = outAddr + ubAxisLeftPadLoops * strideOutVlO1 +
674- ubAxisInCopyLoops * strideOutVlO1 + urIdx * strideOutVlO1;670+ ubAxisInCopyLoops * strideOutVlO1 + urIdx * strideOutVlO1;
675 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,671 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,
676 inAddr, curPadOutAddr, regIdxPad, idxPadOffset);672 inAddr, curPadOutAddr, regIdxPad, idxPadOffset);
677 673 
@@ -696,10 +692,10 @@ private:
696 LocalTensor<T>& outTensor, uint32_t ubAxisInCopyNum,692 LocalTensor<T>& outTensor, uint32_t ubAxisInCopyNum,
697 uint32_t ubAxisLeftPadNum, uint32_t ubAxisRightPadNum)693 uint32_t ubAxisLeftPadNum, uint32_t ubAxisRightPadNum)
698 {694 {
699- __local_mem__ RangeType* idxPadAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();695+ __ubuf__ RangeType* idxPadAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
700- __local_mem__ RangeType* idxAddr = idxPadAddr + VL_RANGE_CNT;696+ __ubuf__ RangeType* idxAddr = idxPadAddr + VL_RANGE_CNT;
701- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();697+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
702- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr();698+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr();
703 699 
704 uint32_t vlSplitLoopIn = vlSplitInEdgeGather_;700 uint32_t vlSplitLoopIn = vlSplitInEdgeGather_;
705 if constexpr (sizeof(T) == 1) {701 if constexpr (sizeof(T) == 1) {
@@ -775,8 +771,8 @@ private:
775 {771 {
776 Reg::RegTensor<RangeType> regIdxPad;772 Reg::RegTensor<RangeType> regIdxPad;
777 Reg::RegTensor<RangeType> regIdx;773 Reg::RegTensor<RangeType> regIdx;
778- Reg::DataCopy(regIdxPad, idxPadAddr);774+ Reg::LoadAlign(regIdxPad, idxPadAddr);
779- Reg::DataCopy(regIdx, idxAddr);775+ Reg::LoadAlign(regIdx, idxAddr);
780 776 
781 // 处理N轴上的输入, N轴没有pad777 // 处理N轴上的输入, N轴没有pad
782 for (uint16_t nIdx = 0; nIdx < ubAxisInCopyLoops; nIdx++) {778 for (uint16_t nIdx = 0; nIdx < ubAxisInCopyLoops; nIdx++) {
@@ -786,13 +782,12 @@ private:
786 for (uint16_t i = 0; i < vlO1LeftPadNum; i++) {782 for (uint16_t i = 0; i < vlO1LeftPadNum; i++) {
787 // H轴左pad, VL切3维时退化为C轴左pad783 // H轴左pad, VL切3维时退化为C轴左pad
788 uint32_t idxPadOffset = curInOffset;784 uint32_t idxPadOffset = curInOffset;
789- __local_mem__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;785+ __ubuf__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;
790 VlPaddingCopyProc(leftGatherLoops4D, leftPadLoops, lastLeftPadLoops4D, maskValue,786 VlPaddingCopyProc(leftGatherLoops4D, leftPadLoops, lastLeftPadLoops4D, maskValue,
791 lastLeftPadMaskValue, inAddr, curPadOutAddr, regIdxPad, idxPadOffset);787 lastLeftPadMaskValue, inAddr, curPadOutAddr, regIdxPad, idxPadOffset);
792 788 
793 // H轴输入个数, VL切3维时退化为C轴输入个数789 // H轴输入个数, VL切3维时退化为C轴输入个数
794- __local_mem__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 +790+ __ubuf__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 + vlLeftPadNum * strideOutVl;
795- vlLeftPadNum * strideOutVl;
796 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,791 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,
797 curOutAddr, regIdx, idxPadOffset);792 curOutAddr, regIdx, idxPadOffset);
798 793 
@@ -809,13 +804,12 @@ private:
809 for (uint16_t i = 0; i < vlO1InNum; i++) {804 for (uint16_t i = 0; i < vlO1InNum; i++) {
810 // H轴左pad805 // H轴左pad
811 uint32_t idxPadOffset = curInOffset + i * strideInVlO1;806 uint32_t idxPadOffset = curInOffset + i * strideInVlO1;
812- __local_mem__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;807+ __ubuf__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;
813 VlPaddingCopyProc(leftGatherLoops4D, leftPadLoops, lastLeftPadLoops4D, maskValue,808 VlPaddingCopyProc(leftGatherLoops4D, leftPadLoops, lastLeftPadLoops4D, maskValue,
814 lastLeftPadMaskValue, inAddr, curPadOutAddr, regIdxPad, idxPadOffset);809 lastLeftPadMaskValue, inAddr, curPadOutAddr, regIdxPad, idxPadOffset);
815 810 
816 // H轴输入有效个数811 // H轴输入有效个数
817- __local_mem__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 +812+ __ubuf__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 + vlLeftPadNum * strideOutVl;
818- vlLeftPadNum * strideOutVl;
819 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,813 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,
820 curOutAddr, regIdx, idxPadOffset);814 curOutAddr, regIdx, idxPadOffset);
821 815 
@@ -831,12 +825,11 @@ private:
831 curOutOffset = nIdx * strideOutN + vlO1LeftPadNum * strideOutVlO1 + vlO1InNum * strideOutVlO1;825 curOutOffset = nIdx * strideOutN + vlO1LeftPadNum * strideOutVlO1 + vlO1InNum * strideOutVlO1;
832 for (uint16_t i = 0; i < vlO1RightPadNum; i++) {826 for (uint16_t i = 0; i < vlO1RightPadNum; i++) {
833 uint32_t idxPadOffset = curInOffset;827 uint32_t idxPadOffset = curInOffset;
834- __local_mem__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;828+ __ubuf__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;
835 VlPaddingCopyProc(leftGatherLoops4D, leftPadLoops, lastLeftPadLoops4D, maskValue,829 VlPaddingCopyProc(leftGatherLoops4D, leftPadLoops, lastLeftPadLoops4D, maskValue,
836 lastLeftPadMaskValue, inAddr, curPadOutAddr, regIdxPad, idxPadOffset);830 lastLeftPadMaskValue, inAddr, curPadOutAddr, regIdxPad, idxPadOffset);
837 831 
838- __local_mem__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 +832+ __ubuf__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 + vlLeftPadNum * strideOutVl;
839- vlLeftPadNum * strideOutVl;
840 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,833 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,
841 curOutAddr, regIdx, idxPadOffset);834 curOutAddr, regIdx, idxPadOffset);
842 835 
Mconversion/pad_v3/op_kernel/arch35/pad_edge_huge_width.h+7-7
@@ -285,13 +285,13 @@ private:
285 __VEC_SCOPE__285 __VEC_SCOPE__
286 {286 {
287 AscendC::Reg::RegTensor<T, Trait> vReg;287 AscendC::Reg::RegTensor<T, Trait> vReg;
288- AscendC::Reg::UnalignReg uReg;288+ AscendC::Reg::UnalignRegForStore uReg;
289 289 
290 for (uint16_t k = 0; k < needPadLeft; k++) {290 for (uint16_t k = 0; k < needPadLeft; k++) {
291 __ubuf__ T* outAddr = dstAddr + padWLOffset;291 __ubuf__ T* outAddr = dstAddr + padWLOffset;
292- AscendC::Reg::DataCopy(vReg, additionAddr);292+ AscendC::Reg::LoadAlign(vReg, additionAddr);
293- AscendC::Reg::DataCopyUnAlign(outAddr, vReg, uReg, padLeftSize);293+ AscendC::Reg::StoreUnAlign(outAddr, vReg, uReg, padLeftSize);
294- AscendC::Reg::DataCopyUnAlignPost(outAddr, uReg, 0);294+ AscendC::Reg::StoreUnAlignPost(outAddr, uReg, 0);
295 }295 }
296 296 
297 for (uint16_t j = 0; j < needPadRight; j++) {297 for (uint16_t j = 0; j < needPadRight; j++) {
@@ -299,14 +299,14 @@ private:
299 AscendC::Reg::Duplicate(vReg, padRightValue);299 AscendC::Reg::Duplicate(vReg, padRightValue);
300 300 
301 for (uint16_t k = 0; k < repeatTimes; k++) {301 for (uint16_t k = 0; k < repeatTimes; k++) {
302- AscendC::Reg::DataCopyUnAlign(outAddr, vReg, uReg, additionLen);302+ AscendC::Reg::StoreUnAlign(outAddr, vReg, uReg, additionLen);
303 }303 }
304 304 
305 for (uint16_t k = 0; k < needPadRightSurplus; k++) {305 for (uint16_t k = 0; k < needPadRightSurplus; k++) {
306 outAddr = dstAddr + padWROffset + repeatTimes * additionLen;306 outAddr = dstAddr + padWROffset + repeatTimes * additionLen;
307- AscendC::Reg::DataCopyUnAlign(outAddr, vReg, uReg, padRightLen);307+ AscendC::Reg::StoreUnAlign(outAddr, vReg, uReg, padRightLen);
308 }308 }
309- AscendC::Reg::DataCopyUnAlignPost(outAddr, uReg, 0);309+ AscendC::Reg::StoreUnAlignPost(outAddr, uReg, 0);
310 }310 }
311 }311 }
312 }312 }
Mconversion/pad_v3/op_kernel/arch35/pad_edge_normal_w.h+113-107
@@ -495,7 +495,7 @@ private:
495 __aicore__ inline void PadRightSide(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t ubOffset,495 __aicore__ inline void PadRightSide(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t ubOffset,
496 uint32_t copylen)496 uint32_t copylen)
497 {497 {
498- auto dstAddr = reinterpret_cast<__local_mem__ RT*>(dst.GetPhyAddr());498+ auto dstAddr = reinterpret_cast<__ubuf__ RT*>(dst.GetPhyAddr());
499 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;499 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;
500 const int8_t dimNum = tilingData_->dimNum;500 const int8_t dimNum = tilingData_->dimNum;
501 const uint16_t dimNNum = (UB_AXES < CONST4) ? 1 : inCopyLen_[dimNum - CONST4];501 const uint16_t dimNNum = (UB_AXES < CONST4) ? 1 : inCopyLen_[dimNum - CONST4];
@@ -533,9 +533,9 @@ private:
533 uint32_t outLen2 = padRightBLNum * BLK_ELEMS * sizeNum;533 uint32_t outLen2 = padRightBLNum * BLK_ELEMS * sizeNum;
534 534 
535 rMask = AscendC::Reg::UpdateMask<RT>(norPadLen);535 rMask = AscendC::Reg::UpdateMask<RT>(norPadLen);
536- AscendC::Reg::MaskNot(rMask, rMask, maskAll);536+ AscendC::Reg::Not(rMask, rMask, maskAll);
537 outMask = AscendC::Reg::UpdateMask<RT>(outLen);537 outMask = AscendC::Reg::UpdateMask<RT>(outLen);
538- AscendC::Reg::MaskAnd(outNMask, outMask, rMask, maskAll);538+ AscendC::Reg::And(outNMask, outMask, rMask, maskAll);
539 outMask = AscendC::Reg::UpdateMask<RT>(outLen2);539 outMask = AscendC::Reg::UpdateMask<RT>(outLen2);
540 540 
541 if constexpr (UB_AXES == CONST2) {541 if constexpr (UB_AXES == CONST2) {
@@ -558,9 +558,9 @@ private:
558 }558 }
559 }559 }
560 560 
561- __aicore__ inline void PadRightSideOne(__local_mem__ RT* dstAddr, uint32_t copylen, uint32_t step,561+ __aicore__ inline void PadRightSideOne(__ubuf__ RT* dstAddr, uint32_t copylen, uint32_t step, uint32_t lastOffset,
562- uint32_t lastOffset, uint32_t padRightFloorAlign, uint16_t padRightVLNum,562+ uint32_t padRightFloorAlign, uint16_t padRightVLNum, uint16_t padRightBLNum,
563- uint16_t padRightBLNum, Reg::MaskReg outMask, Reg::MaskReg outNMask)563+ Reg::MaskReg outMask, Reg::MaskReg outNMask)
564 {564 {
565 __VEC_SCOPE__565 __VEC_SCOPE__
566 {566 {
@@ -572,57 +572,58 @@ private:
572 AscendC::Reg::RegTensor<RT> tmpIn1;572 AscendC::Reg::RegTensor<RT> tmpIn1;
573 AscendC::Reg::RegTensor<RT> tmpOut;573 AscendC::Reg::RegTensor<RT> tmpOut;
574 for (uint16_t h = 0; h < copylen; h++) {574 for (uint16_t h = 0; h < copylen; h++) {
575- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn, dstAddr + h * step + lastOffset);575+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn, dstAddr + h * step + lastOffset);
576- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn1,576+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn1,
577- dstAddr + h * step + lastOffset + 1);577+ dstAddr + h * step + lastOffset + 1);
578 Reg::Interleave(vRegTmp, tmpOut, tmpIn, tmpIn1);578 Reg::Interleave(vRegTmp, tmpOut, tmpIn, tmpIn1);
579- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign - BLK_ELEMS * 2, vRegTmp, outNMask);579+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign - BLK_ELEMS * 2, vRegTmp,
580+ outNMask);
580 for (uint16_t i = 0; i < padRightVLNum; i++) {581 for (uint16_t i = 0; i < padRightVLNum; i++) {
581- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign + i * VL_ELEMS * 2, vRegTmp,582+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign + i * VL_ELEMS * 2, vRegTmp,
582- maskAll);583+ maskAll);
583 }584 }
584 for (uint16_t i = 0; i < padRightBLNum; i++) {585 for (uint16_t i = 0; i < padRightBLNum; i++) {
585- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign + padRightVLNum * VL_ELEMS * 2,586+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign + padRightVLNum * VL_ELEMS * 2,
586- vRegTmp, outMask);587+ vRegTmp, outMask);
587 }588 }
588 }589 }
589 } else if constexpr (sizeof(T) == CONST4) {590 } else if constexpr (sizeof(T) == CONST4) {
590 for (uint16_t h = 0; h < copylen; h++) {591 for (uint16_t h = 0; h < copylen; h++) {
591- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(vRegTmp, dstAddr + h * step + lastOffset);592+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(vRegTmp, dstAddr + h * step + lastOffset);
592- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign - BLK_ELEMS, vRegTmp, outNMask);593+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign - BLK_ELEMS, vRegTmp, outNMask);
593 for (uint16_t i = 0; i < padRightVLNum; i++) {594 for (uint16_t i = 0; i < padRightVLNum; i++) {
594- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign + i * VL_ELEMS, vRegTmp,595+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign + i * VL_ELEMS, vRegTmp,
595- maskAll);596+ maskAll);
596 }597 }
597 for (uint16_t i = 0; i < padRightBLNum; i++) {598 for (uint16_t i = 0; i < padRightBLNum; i++) {
598- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign + padRightVLNum * VL_ELEMS,599+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign + padRightVLNum * VL_ELEMS,
599- vRegTmp, outMask);600+ vRegTmp, outMask);
600 }601 }
601 }602 }
602 } else if constexpr (sizeof(T) == CONST2) {603 } else if constexpr (sizeof(T) == CONST2) {
603 for (uint16_t h = 0; h < copylen; h++) {604 for (uint16_t h = 0; h < copylen; h++) {
604- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B16>(vRegTmp, dstAddr + h * step + lastOffset);605+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B16>(vRegTmp, dstAddr + h * step + lastOffset);
605- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign - BLK_ELEMS, vRegTmp, outNMask);606+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign - BLK_ELEMS, vRegTmp, outNMask);
606 for (uint16_t i = 0; i < padRightVLNum; i++) {607 for (uint16_t i = 0; i < padRightVLNum; i++) {
607- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign + i * VL_ELEMS, vRegTmp,608+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign + i * VL_ELEMS, vRegTmp,
608- maskAll);609+ maskAll);
609 }610 }
610 for (uint16_t i = 0; i < padRightBLNum; i++) {611 for (uint16_t i = 0; i < padRightBLNum; i++) {
611- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign + padRightVLNum * VL_ELEMS,612+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign + padRightVLNum * VL_ELEMS,
612- vRegTmp, outMask);613+ vRegTmp, outMask);
613 }614 }
614 }615 }
615 } else if constexpr (sizeof(T) == 1) {616 } else if constexpr (sizeof(T) == 1) {
616 for (uint16_t h = 0; h < copylen; h++) {617 for (uint16_t h = 0; h < copylen; h++) {
617- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B8>(vRegTmp, dstAddr + h * step + lastOffset);618+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B8>(vRegTmp, dstAddr + h * step + lastOffset);
618- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign - BLK_ELEMS, vRegTmp, outNMask);619+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign - BLK_ELEMS, vRegTmp, outNMask);
619 for (uint16_t i = 0; i < padRightVLNum; i++) {620 for (uint16_t i = 0; i < padRightVLNum; i++) {
620- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign + i * VL_ELEMS, vRegTmp,621+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign + i * VL_ELEMS, vRegTmp,
621- maskAll);622+ maskAll);
622 }623 }
623 for (uint16_t i = 0; i < padRightBLNum; i++) {624 for (uint16_t i = 0; i < padRightBLNum; i++) {
624- AscendC::Reg::DataCopy(dstAddr + h * step + padRightFloorAlign + padRightVLNum * VL_ELEMS,625+ AscendC::Reg::StoreAlign(dstAddr + h * step + padRightFloorAlign + padRightVLNum * VL_ELEMS,
625- vRegTmp, outMask);626+ vRegTmp, outMask);
626 }627 }
627 }628 }
628 }629 }
@@ -631,7 +632,7 @@ private:
631 632 
632 __aicore__ inline void PadLeftSideLast(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t ubOffset)633 __aicore__ inline void PadLeftSideLast(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t ubOffset)
633 {634 {
634- auto dstAddr = reinterpret_cast<__local_mem__ RT*>(dst.GetPhyAddr());635+ auto dstAddr = reinterpret_cast<__ubuf__ RT*>(dst.GetPhyAddr());
635 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;636 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;
636 const int8_t dimNum = tilingData_->dimNum;637 const int8_t dimNum = tilingData_->dimNum;
637 const uint16_t dimNNum = (UB_AXES < CONST4) ? 1 : inCopyLen_[dimNum - CONST4];638 const uint16_t dimNNum = (UB_AXES < CONST4) ? 1 : inCopyLen_[dimNum - CONST4];
@@ -665,23 +666,23 @@ private:
665 uint32_t outnLen = padLeftBLNum * BLK_ELEMS * sizeNum;666 uint32_t outnLen = padLeftBLNum * BLK_ELEMS * sizeNum;
666 uint32_t ubInOffset = 0;667 uint32_t ubInOffset = 0;
667 rMask = AscendC::Reg::UpdateMask<RT>(norPadLen);668 rMask = AscendC::Reg::UpdateMask<RT>(norPadLen);
668- AscendC::Reg::MaskNot(rMask, rMask, maskAll);669+ AscendC::Reg::Not(rMask, rMask, maskAll);
669 outNMask = AscendC::Reg::UpdateMask<RT>(outLen);670 outNMask = AscendC::Reg::UpdateMask<RT>(outLen);
670- AscendC::Reg::MaskAnd(outMask, outNMask, rMask, maskAll);671+ AscendC::Reg::And(outMask, outNMask, rMask, maskAll);
671 outNMask = AscendC::Reg::UpdateMask<RT>(outnLen);672 outNMask = AscendC::Reg::UpdateMask<RT>(outnLen);
672 673 
673 if constexpr (sizeof(T) == 1) {674 if constexpr (sizeof(T) == 1) {
674 for (uint16_t n = 0; n < dimNNum; n++) {675 for (uint16_t n = 0; n < dimNNum; n++) {
675 for (uint16_t c = 0; c < dimCNum; c++) {676 for (uint16_t c = 0; c < dimCNum; c++) {
676 ubInOffset = firstOffset + n * padCHW + c * padHW + additionOffset_;677 ubInOffset = firstOffset + n * padCHW + c * padHW + additionOffset_;
677- AscendC::Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B8>(vRegTmp, dstAddr + ubInOffset);678+ AscendC::Reg::LoadAlign<T, Reg::LoadDist::DIST_BRC_B8>(vRegTmp, dstAddr + ubInOffset);
678 ubInOffset = ubInOffset + padRightFloorAlign;679 ubInOffset = ubInOffset + padRightFloorAlign;
679- AscendC::Reg::DataCopy(dstAddr + ubInOffset - BLK_ELEMS, vRegTmp, outMask);680+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset - BLK_ELEMS, vRegTmp, outMask);
680 for (uint16_t i = 0; i < padLeftVLNum; i++) {681 for (uint16_t i = 0; i < padLeftVLNum; i++) {
681- AscendC::Reg::DataCopy(dstAddr + ubInOffset + i * VL_ELEMS, vRegTmp, maskAll);682+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + i * VL_ELEMS, vRegTmp, maskAll);
682 }683 }
683 for (uint16_t i = 0; i < BLNum; i++) {684 for (uint16_t i = 0; i < BLNum; i++) {
684- AscendC::Reg::DataCopy(dstAddr + ubInOffset + padLeftVLNum * VL_ELEMS, vRegTmp, outNMask);685+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + padLeftVLNum * VL_ELEMS, vRegTmp, outNMask);
685 }686 }
686 }687 }
687 }688 }
@@ -689,14 +690,14 @@ private:
689 for (uint16_t n = 0; n < dimNNum; n++) {690 for (uint16_t n = 0; n < dimNNum; n++) {
690 for (uint16_t c = 0; c < dimCNum; c++) {691 for (uint16_t c = 0; c < dimCNum; c++) {
691 ubInOffset = firstOffset + n * padCHW + c * padHW + additionOffset_;692 ubInOffset = firstOffset + n * padCHW + c * padHW + additionOffset_;
692- AscendC::Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B16>(vRegTmp, dstAddr + ubInOffset);693+ AscendC::Reg::LoadAlign<T, Reg::LoadDist::DIST_BRC_B16>(vRegTmp, dstAddr + ubInOffset);
693 ubInOffset = ubInOffset + padRightFloorAlign;694 ubInOffset = ubInOffset + padRightFloorAlign;
694- AscendC::Reg::DataCopy(dstAddr + ubInOffset - BLK_ELEMS, vRegTmp, outMask);695+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset - BLK_ELEMS, vRegTmp, outMask);
695 for (uint16_t i = 0; i < padLeftVLNum; i++) {696 for (uint16_t i = 0; i < padLeftVLNum; i++) {
696- AscendC::Reg::DataCopy(dstAddr + ubInOffset + i * VL_ELEMS, vRegTmp, maskAll);697+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + i * VL_ELEMS, vRegTmp, maskAll);
697 }698 }
698 for (uint16_t i = 0; i < BLNum; i++) {699 for (uint16_t i = 0; i < BLNum; i++) {
699- AscendC::Reg::DataCopy(dstAddr + ubInOffset + padLeftVLNum * VL_ELEMS, vRegTmp, outNMask);700+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + padLeftVLNum * VL_ELEMS, vRegTmp, outNMask);
700 }701 }
701 }702 }
702 }703 }
@@ -704,14 +705,14 @@ private:
704 for (uint16_t n = 0; n < dimNNum; n++) {705 for (uint16_t n = 0; n < dimNNum; n++) {
705 for (uint16_t c = 0; c < dimCNum; c++) {706 for (uint16_t c = 0; c < dimCNum; c++) {
706 ubInOffset = firstOffset + n * padCHW + c * padHW + additionOffset_;707 ubInOffset = firstOffset + n * padCHW + c * padHW + additionOffset_;
707- AscendC::Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B32>(vRegTmp, dstAddr + ubInOffset);708+ AscendC::Reg::LoadAlign<T, Reg::LoadDist::DIST_BRC_B32>(vRegTmp, dstAddr + ubInOffset);
708 ubInOffset = ubInOffset + padRightFloorAlign;709 ubInOffset = ubInOffset + padRightFloorAlign;
709- AscendC::Reg::DataCopy(dstAddr + ubInOffset - BLK_ELEMS, vRegTmp, outMask);710+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset - BLK_ELEMS, vRegTmp, outMask);
710 for (uint16_t i = 0; i < padLeftVLNum; i++) {711 for (uint16_t i = 0; i < padLeftVLNum; i++) {
711- AscendC::Reg::DataCopy(dstAddr + ubInOffset + i * VL_ELEMS, vRegTmp, maskAll);712+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + i * VL_ELEMS, vRegTmp, maskAll);
712 }713 }
713 for (uint16_t i = 0; i < BLNum; i++) {714 for (uint16_t i = 0; i < BLNum; i++) {
714- AscendC::Reg::DataCopy(dstAddr + ubInOffset + padLeftVLNum * VL_ELEMS, vRegTmp, outNMask);715+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + padLeftVLNum * VL_ELEMS, vRegTmp, outNMask);
715 }716 }
716 }717 }
717 }718 }
@@ -719,17 +720,17 @@ private:
719 for (uint16_t n = 0; n < dimNNum; n++) {720 for (uint16_t n = 0; n < dimNNum; n++) {
720 for (uint16_t c = 0; c < dimCNum; c++) {721 for (uint16_t c = 0; c < dimCNum; c++) {
721 ubInOffset = firstOffset + n * padCHW + c * padHW + additionOffset_ * 2;722 ubInOffset = firstOffset + n * padCHW + c * padHW + additionOffset_ * 2;
722- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn, dstAddr + ubInOffset);723+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn, dstAddr + ubInOffset);
723- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn1, dstAddr + ubInOffset + 1);724+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn1, dstAddr + ubInOffset + 1);
724 Reg::Interleave(vRegTmp, tmpOut, tmpIn, tmpIn1);725 Reg::Interleave(vRegTmp, tmpOut, tmpIn, tmpIn1);
725 ubInOffset = ubInOffset + padRightFloorAlign;726 ubInOffset = ubInOffset + padRightFloorAlign;
726- AscendC::Reg::DataCopy(dstAddr + ubInOffset - BLK_ELEMS * 2, vRegTmp, outMask);727+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset - BLK_ELEMS * 2, vRegTmp, outMask);
727 for (uint16_t i = 0; i < padLeftVLNum; i++) {728 for (uint16_t i = 0; i < padLeftVLNum; i++) {
728- AscendC::Reg::DataCopy(dstAddr + ubInOffset + i * VL_ELEMS * 2, vRegTmp, maskAll);729+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + i * VL_ELEMS * 2, vRegTmp, maskAll);
729 }730 }
730 for (uint16_t i = 0; i < BLNum; i++) {731 for (uint16_t i = 0; i < BLNum; i++) {
731- AscendC::Reg::DataCopy(dstAddr + ubInOffset + padLeftVLNum * VL_ELEMS * 2, vRegTmp,732+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + padLeftVLNum * VL_ELEMS * 2, vRegTmp,
732- outNMask);733+ outNMask);
733 }734 }
734 }735 }
735 }736 }
@@ -740,7 +741,7 @@ private:
740 __aicore__ inline void PadLeftSide(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t ubOffset,741 __aicore__ inline void PadLeftSide(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t ubOffset,
741 bool isFirst, uint32_t copylen)742 bool isFirst, uint32_t copylen)
742 {743 {
743- auto dstAddr = reinterpret_cast<__local_mem__ RT*>(dst.GetPhyAddr());744+ auto dstAddr = reinterpret_cast<__ubuf__ RT*>(dst.GetPhyAddr());
744 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;745 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;
745 const int8_t ubAxis = tilingData_->ubAxis;746 const int8_t ubAxis = tilingData_->ubAxis;
746 const uint64_t ubFactor = tilingData_->ubFactor;747 const uint64_t ubFactor = tilingData_->ubFactor;
@@ -777,7 +778,7 @@ private:
777 778 
778 uint32_t nolPadLen = VL_ELEMS * sizeNum - PadLeftSize;779 uint32_t nolPadLen = VL_ELEMS * sizeNum - PadLeftSize;
779 lMask = AscendC::Reg::UpdateMask<RT>(nolPadLen);780 lMask = AscendC::Reg::UpdateMask<RT>(nolPadLen);
780- AscendC::Reg::MaskNot(lMask, lMask, maskAll);781+ AscendC::Reg::Not(lMask, lMask, maskAll);
781 if constexpr (UB_AXES == CONST2) {782 if constexpr (UB_AXES == CONST2) {
782 PadLeftSideOne(dstAddr, firstOffset + additionOffset_ * sizeNum, copylen, padW, padLeftVLNum, BLNum,783 PadLeftSideOne(dstAddr, firstOffset + additionOffset_ * sizeNum, copylen, padW, padLeftVLNum, BLNum,
783 lMask);784 lMask);
@@ -797,8 +798,8 @@ private:
797 }798 }
798 }799 }
799 800 
800- __aicore__ inline void PadLeftSideOne(__local_mem__ RT* dstAddr, uint32_t firstOffset, uint32_t copylen,801+ __aicore__ inline void PadLeftSideOne(__ubuf__ RT* dstAddr, uint32_t firstOffset, uint32_t copylen, uint32_t step,
801- uint32_t step, uint16_t padLeftVLNum, uint16_t BLNum, Reg::MaskReg lMask)802+ uint16_t padLeftVLNum, uint16_t BLNum, Reg::MaskReg lMask)
802 {803 {
803 __VEC_SCOPE__804 __VEC_SCOPE__
804 {805 {
@@ -810,54 +811,57 @@ private:
810 AscendC::Reg::RegTensor<RT> tmpIn1;811 AscendC::Reg::RegTensor<RT> tmpIn1;
811 AscendC::Reg::RegTensor<RT> tmpOut;812 AscendC::Reg::RegTensor<RT> tmpOut;
812 for (uint16_t h = 0; h < copylen; h++) {813 for (uint16_t h = 0; h < copylen; h++) {
813- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn, dstAddr + firstOffset + h * step);814+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn, dstAddr + firstOffset + h * step);
814- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn1,815+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn1,
815- dstAddr + firstOffset + h * step + 1);816+ dstAddr + firstOffset + h * step + 1);
816 Reg::Interleave(vRegTmp, tmpOut, tmpIn, tmpIn1);817 Reg::Interleave(vRegTmp, tmpOut, tmpIn, tmpIn1);
817 // 先逐个vreg，再逐个32B818 // 先逐个vreg，再逐个32B
818 for (uint16_t i = 0; i < padLeftVLNum; i++) {819 for (uint16_t i = 0; i < padLeftVLNum; i++) {
819- AscendC::Reg::DataCopy(dstAddr + firstOffset + h * step - (i + 1) * VL_ELEMS * 2, vRegTmp,820+ AscendC::Reg::StoreAlign(dstAddr + firstOffset + h * step - (i + 1) * VL_ELEMS * 2, vRegTmp,
820- maskAll);821+ maskAll);
821 }822 }
822 for (uint16_t i = 0; i < BLNum; i++) {823 for (uint16_t i = 0; i < BLNum; i++) {
823- AscendC::Reg::DataCopy(dstAddr + firstOffset + h * step - (padLeftVLNum + 1) * VL_ELEMS * 2,824+ AscendC::Reg::StoreAlign(dstAddr + firstOffset + h * step - (padLeftVLNum + 1) * VL_ELEMS * 2,
824- vRegTmp, lMask);825+ vRegTmp, lMask);
825 }826 }
826 }827 }
827 } else if constexpr (sizeof(T) == CONST4) {828 } else if constexpr (sizeof(T) == CONST4) {
828 for (uint16_t h = 0; h < copylen; h++) {829 for (uint16_t h = 0; h < copylen; h++) {
829- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(vRegTmp, dstAddr + firstOffset + h * step);830+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(vRegTmp, dstAddr + firstOffset + h * step);
830 // 先逐个vreg，再逐个32B831 // 先逐个vreg，再逐个32B
831 for (uint16_t i = 0; i < padLeftVLNum; i++) {832 for (uint16_t i = 0; i < padLeftVLNum; i++) {
832- AscendC::Reg::DataCopy(dstAddr + firstOffset + h * step - (i + 1) * VL_ELEMS, vRegTmp, maskAll);833+ AscendC::Reg::StoreAlign(dstAddr + firstOffset + h * step - (i + 1) * VL_ELEMS, vRegTmp,
834+ maskAll);
833 }835 }
834 for (uint16_t i = 0; i < BLNum; i++) {836 for (uint16_t i = 0; i < BLNum; i++) {
835- AscendC::Reg::DataCopy(dstAddr + firstOffset + h * step - (padLeftVLNum + 1) * VL_ELEMS,837+ AscendC::Reg::StoreAlign(dstAddr + firstOffset + h * step - (padLeftVLNum + 1) * VL_ELEMS,
836- vRegTmp, lMask);838+ vRegTmp, lMask);
837 }839 }
838 }840 }
839 } else if constexpr (sizeof(T) == CONST2) {841 } else if constexpr (sizeof(T) == CONST2) {
840 for (uint16_t h = 0; h < copylen; h++) {842 for (uint16_t h = 0; h < copylen; h++) {
841- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B16>(vRegTmp, dstAddr + firstOffset + h * step);843+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B16>(vRegTmp, dstAddr + firstOffset + h * step);
842 // 先逐个vreg，再逐个32B844 // 先逐个vreg，再逐个32B
843 for (uint16_t i = 0; i < padLeftVLNum; i++) {845 for (uint16_t i = 0; i < padLeftVLNum; i++) {
844- AscendC::Reg::DataCopy(dstAddr + firstOffset + h * step - (i + 1) * VL_ELEMS, vRegTmp, maskAll);846+ AscendC::Reg::StoreAlign(dstAddr + firstOffset + h * step - (i + 1) * VL_ELEMS, vRegTmp,
847+ maskAll);
845 }848 }
846 for (uint16_t i = 0; i < BLNum; i++) {849 for (uint16_t i = 0; i < BLNum; i++) {
847- AscendC::Reg::DataCopy(dstAddr + firstOffset + h * step - (padLeftVLNum + 1) * VL_ELEMS,850+ AscendC::Reg::StoreAlign(dstAddr + firstOffset + h * step - (padLeftVLNum + 1) * VL_ELEMS,
848- vRegTmp, lMask);851+ vRegTmp, lMask);
849 }852 }
850 }853 }
851 } else if constexpr (sizeof(T) == 1) {854 } else if constexpr (sizeof(T) == 1) {
852 for (uint16_t h = 0; h < copylen; h++) {855 for (uint16_t h = 0; h < copylen; h++) {
853- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B8>(vRegTmp, dstAddr + firstOffset + h * step);856+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B8>(vRegTmp, dstAddr + firstOffset + h * step);
854 // 先逐个vreg，再逐个32B857 // 先逐个vreg，再逐个32B
855 for (uint16_t i = 0; i < padLeftVLNum; i++) {858 for (uint16_t i = 0; i < padLeftVLNum; i++) {
856- AscendC::Reg::DataCopy(dstAddr + firstOffset + h * step - (i + 1) * VL_ELEMS, vRegTmp, maskAll);859+ AscendC::Reg::StoreAlign(dstAddr + firstOffset + h * step - (i + 1) * VL_ELEMS, vRegTmp,
860+ maskAll);
857 }861 }
858 for (uint16_t i = 0; i < BLNum; i++) {862 for (uint16_t i = 0; i < BLNum; i++) {
859- AscendC::Reg::DataCopy(dstAddr + firstOffset + h * step - (padLeftVLNum + 1) * VL_ELEMS,863+ AscendC::Reg::StoreAlign(dstAddr + firstOffset + h * step - (padLeftVLNum + 1) * VL_ELEMS,
860- vRegTmp, lMask);864+ vRegTmp, lMask);
861 }865 }
862 }866 }
863 }867 }
@@ -866,7 +870,7 @@ private:
866 870 
867 __aicore__ inline void PadLeftSideFirst(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t ubOffset)871 __aicore__ inline void PadLeftSideFirst(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t ubOffset)
868 {872 {
869- auto dstAddr = reinterpret_cast<__local_mem__ RT*>(dst.GetPhyAddr());873+ auto dstAddr = reinterpret_cast<__ubuf__ RT*>(dst.GetPhyAddr());
870 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;874 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;
871 const int8_t dimNum = tilingData_->dimNum;875 const int8_t dimNum = tilingData_->dimNum;
872 const uint32_t padRightFloorAlign = CeilAlign(padParam.padWROffset * sizeNum, BLK_ELEMS * sizeNum);876 const uint32_t padRightFloorAlign = CeilAlign(padParam.padWROffset * sizeNum, BLK_ELEMS * sizeNum);
@@ -892,26 +896,27 @@ private:
892 AscendC::Reg::RegTensor<RT> tmpOut;896 AscendC::Reg::RegTensor<RT> tmpOut;
893 897 
894 if constexpr (sizeof(T) == 1) {898 if constexpr (sizeof(T) == 1) {
895- AscendC::Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B8>(vRegTmp, dstAddr + firstOffset + additionOffset_);899+ AscendC::Reg::LoadAlign<T, Reg::LoadDist::DIST_BRC_B8>(vRegTmp,
900+ dstAddr + firstOffset + additionOffset_);
896 // 第一行左pad，写到临时空间901 // 第一行左pad，写到临时空间
897- AscendC::Reg::DataCopy(dstAddr, vRegTmp, outMask);902+ AscendC::Reg::StoreAlign(dstAddr, vRegTmp, outMask);
898 } else if constexpr (sizeof(T) == CONST2) {903 } else if constexpr (sizeof(T) == CONST2) {
899- AscendC::Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B16>(vRegTmp,904+ AscendC::Reg::LoadAlign<T, Reg::LoadDist::DIST_BRC_B16>(vRegTmp,
900- dstAddr + firstOffset + additionOffset_);905+ dstAddr + firstOffset + additionOffset_);
901 // 第一行左pad，写到临时空间906 // 第一行左pad，写到临时空间
902- AscendC::Reg::DataCopy(dstAddr, vRegTmp, outMask);907+ AscendC::Reg::StoreAlign(dstAddr, vRegTmp, outMask);
903 } else if constexpr (sizeof(T) == CONST4) {908 } else if constexpr (sizeof(T) == CONST4) {
904- AscendC::Reg::DataCopy<T, Reg::LoadDist::DIST_BRC_B32>(vRegTmp,909+ AscendC::Reg::LoadAlign<T, Reg::LoadDist::DIST_BRC_B32>(vRegTmp,
905- dstAddr + firstOffset + additionOffset_);910+ dstAddr + firstOffset + additionOffset_);
906 // 第一行左pad，写到临时空间911 // 第一行左pad，写到临时空间
907- AscendC::Reg::DataCopy(dstAddr, vRegTmp, outMask);912+ AscendC::Reg::StoreAlign(dstAddr, vRegTmp, outMask);
908 } else if constexpr (sizeof(T) > CONST4) {913 } else if constexpr (sizeof(T) > CONST4) {
909- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn,914+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(tmpIn,
910- dstAddr + firstOffset + 2 * additionOffset_);915+ dstAddr + firstOffset + 2 * additionOffset_);
911- AscendC::Reg::DataCopy<RT, Reg::LoadDist::DIST_BRC_B32>(916+ AscendC::Reg::LoadAlign<RT, Reg::LoadDist::DIST_BRC_B32>(
912 tmpIn1, dstAddr + firstOffset + 2 * additionOffset_ + 1);917 tmpIn1, dstAddr + firstOffset + 2 * additionOffset_ + 1);
913 Reg::Interleave(vRegTmp, tmpOut, tmpIn, tmpIn1);918 Reg::Interleave(vRegTmp, tmpOut, tmpIn, tmpIn1);
914- AscendC::Reg::DataCopy(dstAddr, vRegTmp, outMask);919+ AscendC::Reg::StoreAlign(dstAddr, vRegTmp, outMask);
915 }920 }
916 }921 }
917 }922 }
@@ -920,7 +925,7 @@ private:
920 __aicore__ inline void PadCopySame(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t inOffset,925 __aicore__ inline void PadCopySame(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t inOffset,
921 uint32_t outOffset, uint32_t copyLen, int8_t curAxis)926 uint32_t outOffset, uint32_t copyLen, int8_t curAxis)
922 {927 {
923- auto dstAddr = reinterpret_cast<__local_mem__ RT*>(dst.GetPhyAddr());928+ auto dstAddr = reinterpret_cast<__ubuf__ RT*>(dst.GetPhyAddr());
924 const int8_t ubAxis = tilingData_->ubAxis;929 const int8_t ubAxis = tilingData_->ubAxis;
925 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;930 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;
926 const uint16_t dimHNum = copyLen;931 const uint16_t dimHNum = copyLen;
@@ -939,17 +944,18 @@ private:
939 outMask = AscendC::Reg::UpdateMask<T, Trait>(outLen);944 outMask = AscendC::Reg::UpdateMask<T, Trait>(outLen);
940 945 
941 for (uint16_t i = 0; i < padVLNum; i++) {946 for (uint16_t i = 0; i < padVLNum; i++) {
942- AscendC::Reg::DataCopy(vRegTmp, dstAddr + (inOffset + i * VL_ELEMS + additionOffset_) * sizeNum);947+ AscendC::Reg::LoadAlign(vRegTmp, dstAddr + (inOffset + i * VL_ELEMS + additionOffset_) * sizeNum);
943 for (uint16_t n = 0; n < dimHNum; n++) {948 for (uint16_t n = 0; n < dimHNum; n++) {
944- AscendC::Reg::DataCopy(949+ AscendC::Reg::StoreAlign(
945 dstAddr + (outOffset + i * VL_ELEMS + additionOffset_) * sizeNum + n * totalNum, vRegTmp,950 dstAddr + (outOffset + i * VL_ELEMS + additionOffset_) * sizeNum + n * totalNum, vRegTmp,
946 maskAll);951 maskAll);
947 }952 }
948 }953 }
949 for (uint16_t i = 0; i < BLNum; i++) {954 for (uint16_t i = 0; i < BLNum; i++) {
950- AscendC::Reg::DataCopy(vRegTmp, dstAddr + (inOffset + additionOffset_ + padVLNum * VL_ELEMS) * sizeNum);955+ AscendC::Reg::LoadAlign(vRegTmp,
956+ dstAddr + (inOffset + additionOffset_ + padVLNum * VL_ELEMS) * sizeNum);
951 for (uint16_t n = 0; n < dimHNum; n++) {957 for (uint16_t n = 0; n < dimHNum; n++) {
952- AscendC::Reg::DataCopy(958+ AscendC::Reg::StoreAlign(
953 dstAddr + (outOffset + additionOffset_ + padVLNum * VL_ELEMS) * sizeNum + n * totalNum, vRegTmp,959 dstAddr + (outOffset + additionOffset_ + padVLNum * VL_ELEMS) * sizeNum + n * totalNum, vRegTmp,
954 outMask);960 outMask);
955 }961 }
@@ -961,7 +967,7 @@ private:
961 __aicore__ inline void PadCopyDiff(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t ubOffset,967 __aicore__ inline void PadCopyDiff(const LocalTensor<T>& dst, PadReplNormalParam& padParam, uint32_t ubOffset,
962 int8_t curAxis)968 int8_t curAxis)
963 {969 {
964- auto dstAddr = reinterpret_cast<__local_mem__ RT*>(dst.GetPhyAddr());970+ auto dstAddr = reinterpret_cast<__ubuf__ RT*>(dst.GetPhyAddr());
965 const int8_t dimNum = tilingData_->dimNum;971 const int8_t dimNum = tilingData_->dimNum;
966 const int8_t ubAxis = tilingData_->ubAxis;972 const int8_t ubAxis = tilingData_->ubAxis;
967 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;973 const uint16_t sizeNum = (sizeof(T) > CONST4) ? 2 : 1;
@@ -995,29 +1001,29 @@ private:
995 for (uint16_t c = 0; c < dimCNum; c++) {1001 for (uint16_t c = 0; c < dimCNum; c++) {
996 inOffset = (ubOffset + additionOffset_) * sizeNum + c * padHW + n * padCHW;1002 inOffset = (ubOffset + additionOffset_) * sizeNum + c * padHW + n * padCHW;
997 for (uint16_t i = 0; i < padVLNum; i++) {1003 for (uint16_t i = 0; i < padVLNum; i++) {
998- AscendC::Reg::DataCopy(vRegTmp, dstAddr + inOffset + i * VL_ELEMS * sizeNum + firstOffset);1004+ AscendC::Reg::LoadAlign(vRegTmp, dstAddr + inOffset + i * VL_ELEMS * sizeNum + firstOffset);
999 for (uint16_t h = 0; h < dimUp; h++) {1005 for (uint16_t h = 0; h < dimUp; h++) {
1000- AscendC::Reg::DataCopy(dstAddr + inOffset + i * VL_ELEMS * sizeNum + h * oneLen, vRegTmp,1006+ AscendC::Reg::StoreAlign(dstAddr + inOffset + i * VL_ELEMS * sizeNum + h * oneLen, vRegTmp,
1001- maskAll);1007+ maskAll);
1002 }1008 }
1003- AscendC::Reg::DataCopy(vRegTmp, dstAddr + inOffset + i * VL_ELEMS * sizeNum + lastOffset);1009+ AscendC::Reg::LoadAlign(vRegTmp, dstAddr + inOffset + i * VL_ELEMS * sizeNum + lastOffset);
1004 for (uint16_t h = 0; h < dimDown; h++) {1010 for (uint16_t h = 0; h < dimDown; h++) {
1005- AscendC::Reg::DataCopy(1011+ AscendC::Reg::StoreAlign(
1006 dstAddr + inOffset + i * VL_ELEMS * sizeNum + lastOffset + (h + 1) * oneLen, vRegTmp,1012 dstAddr + inOffset + i * VL_ELEMS * sizeNum + lastOffset + (h + 1) * oneLen, vRegTmp,
1007 maskAll);1013 maskAll);
1008 }1014 }
1009 }1015 }
1010 for (uint16_t i = 0; i < BLNum; i++) {1016 for (uint16_t i = 0; i < BLNum; i++) {
1011- AscendC::Reg::DataCopy(vRegTmp,1017+ AscendC::Reg::LoadAlign(vRegTmp,
1012- dstAddr + inOffset + padVLNum * sizeNum * VL_ELEMS + firstOffset);1018+ dstAddr + inOffset + padVLNum * sizeNum * VL_ELEMS + firstOffset);
1013 for (uint16_t h = 0; h < dimUp; h++) {1019 for (uint16_t h = 0; h < dimUp; h++) {
1014- AscendC::Reg::DataCopy(dstAddr + inOffset + padVLNum * VL_ELEMS * sizeNum + h * oneLen,1020+ AscendC::Reg::StoreAlign(dstAddr + inOffset + padVLNum * VL_ELEMS * sizeNum + h * oneLen,
1015- vRegTmp, outMask);1021+ vRegTmp, outMask);
1016 }1022 }
1017- AscendC::Reg::DataCopy(vRegTmp,1023+ AscendC::Reg::LoadAlign(vRegTmp,
1018- dstAddr + inOffset + padVLNum * sizeNum * VL_ELEMS + lastOffset);1024+ dstAddr + inOffset + padVLNum * sizeNum * VL_ELEMS + lastOffset);
1019 for (uint16_t h = 0; h < dimDown; h++) {1025 for (uint16_t h = 0; h < dimDown; h++) {
1020- AscendC::Reg::DataCopy(1026+ AscendC::Reg::StoreAlign(
1021 dstAddr + inOffset + padVLNum * VL_ELEMS * sizeNum + lastOffset + (h + 1) * oneLen,1027 dstAddr + inOffset + padVLNum * VL_ELEMS * sizeNum + lastOffset + (h + 1) * oneLen,
1022 vRegTmp, outMask);1028 vRegTmp, outMask);
1023 }1029 }
Mconversion/pad_v3/op_kernel/arch35/pad_gather.h+29-29
@@ -343,25 +343,25 @@ private:
343 int32_t leftPadNum = tdPtr_->leftPad[dimNum_ - CONST2] * tdPtr_->outStride[dimNum_ - CONST2] +343 int32_t leftPadNum = tdPtr_->leftPad[dimNum_ - CONST2] * tdPtr_->outStride[dimNum_ - CONST2] +
344 tdPtr_->leftPad[dimNum_ - 1];344 tdPtr_->leftPad[dimNum_ - 1];
345 345 
346- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();346+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
347 347 
348 __VEC_SCOPE__348 __VEC_SCOPE__
349 {349 {
350 Reg::MaskReg maskMain = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();350 Reg::MaskReg maskMain = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();
351 Reg::RegTensor<RangeType> indexReg;351 Reg::RegTensor<RangeType> indexReg;
352 Reg::RegTensor<RangeType> validReg;352 Reg::RegTensor<RangeType> validReg;
353- Reg::UnalignReg uReg;353+ Reg::UnalignRegForStore uReg;
354 354 
355 Reg::Arange(indexReg, 0); // 0-128355 Reg::Arange(indexReg, 0); // 0-128
356- Reg::DataCopy(idxAddr, indexReg, maskMain);356+ Reg::StoreAlign(idxAddr, indexReg, maskMain);
357 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();357 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();
358 358 
359 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {359 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {
360 for (uint16_t j = 0; j < lastSecInDimSize; j++) {360 for (uint16_t j = 0; j < lastSecInDimSize; j++) {
361- __local_mem__ RangeType* idxAddrTmp = idxAddr + leftPadNum + i * outStride1 + j * outStride2;361+ __ubuf__ RangeType* idxAddrTmp = idxAddr + leftPadNum + i * outStride1 + j * outStride2;
362 Reg::Arange(validReg, validBeginIdx + i * inStride1 + j * inStride2);362 Reg::Arange(validReg, validBeginIdx + i * inStride1 + j * inStride2);
363- Reg::DataCopyUnAlign(idxAddrTmp, validReg, uReg, lastInDimSize);363+ Reg::StoreUnAlign(idxAddrTmp, validReg, uReg, lastInDimSize);
364- Reg::DataCopyUnAlignPost(idxAddrTmp, uReg, 0);364+ Reg::StoreUnAlignPost(idxAddrTmp, uReg, 0);
365 }365 }
366 }366 }
367 }367 }
@@ -376,7 +376,7 @@ private:
376 int32_t scatBeginIdx = lastLeftPadNum + (vlSplitInGather_ - 1) * allPadNum;376 int32_t scatBeginIdx = lastLeftPadNum + (vlSplitInGather_ - 1) * allPadNum;
377 uint32_t scatterNum = vlSplitInGather_ * lastInDimSize;377 uint32_t scatterNum = vlSplitInGather_ * lastInDimSize;
378 uint16_t lastDimsLeft = vlSplitInGather_ - 1;378 uint16_t lastDimsLeft = vlSplitInGather_ - 1;
379- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();379+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
380 380 
381 /*381 /*
382 1. 生成 (0,1,2,,,,127) -> ub 假设 vlSplitInGather_=3382 1. 生成 (0,1,2,,,,127) -> ub 假设 vlSplitInGather_=3
@@ -397,7 +397,7 @@ private:
397 Reg::RegTensor<RangeType> scatIdxReg;397 Reg::RegTensor<RangeType> scatIdxReg;
398 Reg::RegTensor<RangeType> tmpScatIdxReg;398 Reg::RegTensor<RangeType> tmpScatIdxReg;
399 Reg::Arange(indexReg, 0); // b16:0-128; b64:0-32399 Reg::Arange(indexReg, 0); // b16:0-128; b64:0-32
400- Reg::DataCopy(idxAddr, indexReg, maskMain);400+ Reg::StoreAlign(idxAddr, indexReg, maskMain);
401 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();401 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();
402 402 
403 Reg::Arange(validReg, beginIdx); // 128 129 ..403 Reg::Arange(validReg, beginIdx); // 128 129 ..
@@ -406,20 +406,20 @@ private:
406 uint32_t sreg0 = lastInDimSize * (lastDimsLeft - i);406 uint32_t sreg0 = lastInDimSize * (lastDimsLeft - i);
407 mask = Reg::UpdateMask<RangeType>(sreg0);407 mask = Reg::UpdateMask<RangeType>(sreg0);
408 Reg::Arange(tmpScatIdxReg, lastLeftPadNum + (lastDimsLeft - 1 - i) * allPadNum);408 Reg::Arange(tmpScatIdxReg, lastLeftPadNum + (lastDimsLeft - 1 - i) * allPadNum);
409- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(scatIdxReg, tmpScatIdxReg, mask);409+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(scatIdxReg, tmpScatIdxReg, mask);
410 }410 }
411 411 
412 mask = Reg::UpdateMask<RangeType>(scatterNum);412 mask = Reg::UpdateMask<RangeType>(scatterNum);
413- Reg::DataCopyScatter(idxAddr, validReg, (Reg::RegTensor<IdxType>&)scatIdxReg, mask);413+ Reg::Scatter(idxAddr, validReg, (Reg::RegTensor<IdxType>&)scatIdxReg, mask);
414 }414 }
415 }415 }
416 416 
417 __aicore__ inline void GatherProcess(const PadGatherParam& gatherParam, const LocalTensor<RangeType>& idxTensor,417 __aicore__ inline void GatherProcess(const PadGatherParam& gatherParam, const LocalTensor<RangeType>& idxTensor,
418 LocalTensor<T>& inTensor, LocalTensor<T>& outTensor, uint32_t outUbStart)418 LocalTensor<T>& inTensor, LocalTensor<T>& outTensor, uint32_t outUbStart)
419 {419 {
420- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();420+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
421- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();421+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
422- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr() + outUbStart;422+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr() + outUbStart;
423 423 
424 RangeType validBegin = VL_CNT;424 RangeType validBegin = VL_CNT;
425 uint32_t vlSplitLoopIn = vlSplitInGather_;425 uint32_t vlSplitLoopIn = vlSplitInGather_;
@@ -455,46 +455,46 @@ private:
455 Reg::MaskReg maskIdx = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();455 Reg::MaskReg maskIdx = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();
456 Reg::MaskReg maskData;456 Reg::MaskReg maskData;
457 Reg::MaskReg pregT;457 Reg::MaskReg pregT;
458- Reg::UnalignReg uReg;458+ Reg::UnalignRegForStore uReg;
459 459 
460- Reg::DataCopy(regIdx, idxAddr);460+ Reg::LoadAlign(regIdx, idxAddr);
461 461 
462 Reg::Arange(regNewIdx, 0);462 Reg::Arange(regNewIdx, 0);
463- Reg::CompareScalar<RangeType, CMPMODE::GE>(pregT, regIdx, validBegin, maskIdx);463+ Reg::Compares<RangeType, CMPMODE::GE>(pregT, regIdx, validBegin, maskIdx);
464 464 
465 for (uint16_t nIdx = 0; nIdx < axisVlO2; nIdx++) {465 for (uint16_t nIdx = 0; nIdx < axisVlO2; nIdx++) {
466 for (uint16_t cIdx = 0; cIdx < axisVlO1; cIdx++) {466 for (uint16_t cIdx = 0; cIdx < axisVlO1; cIdx++) {
467- __local_mem__ T* outAddrTmp = outAddr + nIdx * strideOutVlO2 + cIdx * strideOutVlO1;467+ __ubuf__ T* outAddrTmp = outAddr + nIdx * strideOutVlO2 + cIdx * strideOutVlO1;
468 RangeType addsScale = nIdx * strideInVlO2 + cIdx * strideInVlO1;468 RangeType addsScale = nIdx * strideInVlO2 + cIdx * strideInVlO1;
469 for (uint16_t hIdx = 0; hIdx < vlSplitLoopCnt; hIdx++) {469 for (uint16_t hIdx = 0; hIdx < vlSplitLoopCnt; hIdx++) {
470 Reg::Adds(regIdxBK, regIdx, hIdx * idxOffset + addsScale, pregT);470 Reg::Adds(regIdxBK, regIdx, hIdx * idxOffset + addsScale, pregT);
471- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(regNewIdx, regIdxBK, pregT);471+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(regNewIdx, regIdxBK, pregT);
472 472 
473- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, inAddr,473+ Reg::Gather((Reg::RegTensor<CastType>&)regData, inAddr, (Reg::RegTensor<IdxType>&)regNewIdx,
474- (Reg::RegTensor<IdxType>&)regNewIdx, maskIdx);474+ maskIdx);
475 if constexpr (sizeof(T) != 1) {475 if constexpr (sizeof(T) != 1) {
476 // Reg::DataCopy(outAddr + hIdx * maskValue, regData, maskData);476 // Reg::DataCopy(outAddr + hIdx * maskValue, regData, maskData);
477- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, maskValue);477+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, maskValue);
478 } else {478 } else {
479 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);479 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
480- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, maskValue);480+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, maskValue);
481 }481 }
482 }482 }
483- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);483+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
484 for (uint16_t hTail = 0; hTail < vlSplitTailLoopCnt; hTail++) {484 for (uint16_t hTail = 0; hTail < vlSplitTailLoopCnt; hTail++) {
485 outAddrTmp = outAddr + nIdx * strideOutVlO2 + cIdx * strideOutVlO1 + vlSplitLoopCnt * maskValue;485 outAddrTmp = outAddr + nIdx * strideOutVlO2 + cIdx * strideOutVlO1 + vlSplitLoopCnt * maskValue;
486 Reg::Adds(regIdxBK, regIdx, vlSplitLoopCnt * idxOffset + addsScale, pregT);486 Reg::Adds(regIdxBK, regIdx, vlSplitLoopCnt * idxOffset + addsScale, pregT);
487- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(regNewIdx, regIdxBK, pregT);487+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(regNewIdx, regIdxBK, pregT);
488 488 
489- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, inAddr,489+ Reg::Gather((Reg::RegTensor<CastType>&)regData, inAddr, (Reg::RegTensor<IdxType>&)regNewIdx,
490- (Reg::RegTensor<IdxType>&)regNewIdx, maskIdx);490+ maskIdx);
491 if constexpr (sizeof(T) != 1) {491 if constexpr (sizeof(T) != 1) {
492- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, maskValueTail);492+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, maskValueTail);
493 } else {493 } else {
494 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);494 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
495- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, maskValueTail);495+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, maskValueTail);
496 }496 }
497- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);497+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
498 }498 }
499 }499 }
500 }500 }
Mconversion/pad_v3/op_kernel/arch35/pad_huge_width.h+8-8
@@ -320,7 +320,7 @@ private:
320 {320 {
321 AscendC::Reg::RegTensor<T, Trait> vReg;321 AscendC::Reg::RegTensor<T, Trait> vReg;
322 AscendC::Reg::RegTensor<T, Trait> vRegTmp;322 AscendC::Reg::RegTensor<T, Trait> vRegTmp;
323- AscendC::Reg::UnalignReg uReg;323+ AscendC::Reg::UnalignRegForStore uReg;
324 AscendC::Reg::MaskReg pMask;324 AscendC::Reg::MaskReg pMask;
325 AscendC::Reg::MaskReg outMask;325 AscendC::Reg::MaskReg outMask;
326 AscendC::Reg::MaskReg maskAll = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL, Trait>();326 AscendC::Reg::MaskReg maskAll = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL, Trait>();
@@ -329,9 +329,9 @@ private:
329 for (uint16_t k = 0; k < needPadLeft; k++) {329 for (uint16_t k = 0; k < needPadLeft; k++) {
330 for (uint16_t n = 0; n < totalHNum; n++) {330 for (uint16_t n = 0; n < totalHNum; n++) {
331 __ubuf__ T* outAddr = dstAddr + dstOffset + padWLOffset + n * padW;331 __ubuf__ T* outAddr = dstAddr + dstOffset + padWLOffset + n * padW;
332- AscendC::Reg::DataCopy(vReg, additionAddr + n * additionLen);332+ AscendC::Reg::LoadAlign(vReg, additionAddr + n * additionLen);
333- AscendC::Reg::DataCopyUnAlign(outAddr, vReg, uReg, padLen);333+ AscendC::Reg::StoreUnAlign(outAddr, vReg, uReg, padLen);
334- AscendC::Reg::DataCopyUnAlignPost(outAddr, uReg, 0);334+ AscendC::Reg::StoreUnAlignPost(outAddr, uReg, 0);
335 }335 }
336 }336 }
337 337 
@@ -339,14 +339,14 @@ private:
339 uint32_t noPadLen = noPadRightSize;339 uint32_t noPadLen = noPadRightSize;
340 uint32_t outLen = BLK_ELEMS;340 uint32_t outLen = BLK_ELEMS;
341 pMask = AscendC::Reg::UpdateMask<T, Trait>(noPadLen);341 pMask = AscendC::Reg::UpdateMask<T, Trait>(noPadLen);
342- AscendC::Reg::MaskNot(pMask, pMask, maskAll);342+ AscendC::Reg::Not(pMask, pMask, maskAll);
343 outMask = AscendC::Reg::UpdateMask<T, Trait>(outLen);343 outMask = AscendC::Reg::UpdateMask<T, Trait>(outLen);
344 for (uint16_t n = 0; n < totalHNum; n++) {344 for (uint16_t n = 0; n < totalHNum; n++) {
345- AscendC::Reg::DataCopy(vReg, dstAddr + dstOffset + padRigthFloorAlign + n * padW);345+ AscendC::Reg::LoadAlign(vReg, dstAddr + dstOffset + padRigthFloorAlign + n * padW);
346 vRegTmp = vReg;346 vRegTmp = vReg;
347 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);347 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);
348- Copy(vReg, vRegTmp, pMask);348+ AscendC::Reg::Move(vReg, vRegTmp, pMask);
349- AscendC::Reg::DataCopy(dstAddr + dstOffset + padRigthFloorAlign + n * padW, vReg, outMask);349+ AscendC::Reg::StoreAlign(dstAddr + dstOffset + padRigthFloorAlign + n * padW, vReg, outMask);
350 }350 }
351 }351 }
352 }352 }
Mconversion/pad_v3/op_kernel/arch35/pad_mirror_gather.h+111-116
@@ -407,8 +407,8 @@ private:
407 uint32_t alignRed = copyStartOffset % BLOCK_NUM;407 uint32_t alignRed = copyStartOffset % BLOCK_NUM;
408 uint32_t alignOffset = 0;408 uint32_t alignOffset = 0;
409 if (alignRed != 0) {409 if (alignRed != 0) {
410- __local_mem__ T* inAddrTmp = (__local_mem__ T*)outLocalBwReal.GetPhyAddr() + copyStartOffset;410+ __ubuf__ T* inAddrTmp = (__ubuf__ T*)outLocalBwReal.GetPhyAddr() + copyStartOffset;
411- __local_mem__ T* outAddrTmp = (__local_mem__ T*)outLocalBwTmp.GetPhyAddr();411+ __ubuf__ T* outAddrTmp = (__ubuf__ T*)outLocalBwTmp.GetPhyAddr();
412 412 
413 alignOffset = BLOCK_NUM - alignRed;413 alignOffset = BLOCK_NUM - alignRed;
414 copyStartOffset = copyStartOffset + alignOffset;414 copyStartOffset = copyStartOffset + alignOffset;
@@ -483,21 +483,21 @@ private:
483 CopyOutPadBwImpl(outLocalBwReal, outLocalBwTmp, copyStartOffset, copyOutNum, totalOutIdx);483 CopyOutPadBwImpl(outLocalBwReal, outLocalBwTmp, copyStartOffset, copyOutNum, totalOutIdx);
484 }484 }
485 485 
486- __aicore__ inline void CopyTmpUnAlign(__local_mem__ T* inAddrTmp, __local_mem__ T* outAddrTmp, uint32_t alignOffset)486+ __aicore__ inline void CopyTmpUnAlign(__ubuf__ T* inAddrTmp, __ubuf__ T* outAddrTmp, uint32_t alignOffset)
487 {487 {
488 uint32_t newCnt = (sizeof(T) != sizeof(OutType)) ? CONST2 * alignOffset : alignOffset;488 uint32_t newCnt = (sizeof(T) != sizeof(OutType)) ? CONST2 * alignOffset : alignOffset;
489- auto newInAddr = reinterpret_cast<__local_mem__ OutType*>(inAddrTmp);489+ auto newInAddr = reinterpret_cast<__ubuf__ OutType*>(inAddrTmp);
490- auto newOutAddr = reinterpret_cast<__local_mem__ OutType*>(outAddrTmp);490+ auto newOutAddr = reinterpret_cast<__ubuf__ OutType*>(outAddrTmp);
491 491 
492 __VEC_SCOPE__492 __VEC_SCOPE__
493 {493 {
494 Reg::RegTensor<OutType> regData;494 Reg::RegTensor<OutType> regData;
495- Reg::UnalignReg uReg;495+ Reg::UnalignRegForLoad uReg;
496 Reg::MaskReg maskIdx = Reg::UpdateMask<OutType>(newCnt);496 Reg::MaskReg maskIdx = Reg::UpdateMask<OutType>(newCnt);
497 497 
498- Reg::DataCopyUnAlignPre(uReg, newInAddr);498+ Reg::LoadUnAlignPre(uReg, newInAddr);
499- Reg::DataCopyUnAlign(regData, uReg, newInAddr, newCnt);499+ Reg::LoadUnAlign(regData, uReg, newInAddr, newCnt);
500- Reg::DataCopy(newOutAddr, regData, maskIdx);500+ Reg::StoreAlign(newOutAddr, regData, maskIdx);
501 }501 }
502 }502 }
503 503 
@@ -546,8 +546,8 @@ private:
546 modeOffset = 0;546 modeOffset = 0;
547 }547 }
548 548 
549- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();549+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
550- __local_mem__ RangeType* idxAddr2 = (__local_mem__ RangeType*)idxTensor.GetPhyAddr() + VL_RANGE_CNT;550+ __ubuf__ RangeType* idxAddr2 = (__ubuf__ RangeType*)idxTensor.GetPhyAddr() + VL_RANGE_CNT;
551 551 
552 __VEC_SCOPE__552 __VEC_SCOPE__
553 {553 {
@@ -559,84 +559,84 @@ private:
559 Reg::RegTensor<RangeType> leftPadIdxReg;559 Reg::RegTensor<RangeType> leftPadIdxReg;
560 Reg::MaskReg rightMask;560 Reg::MaskReg rightMask;
561 Reg::RegTensor<RangeType> rightPadIdxReg;561 Reg::RegTensor<RangeType> rightPadIdxReg;
562- Reg::UnalignReg uReg;562+ Reg::UnalignRegForStore uReg;
563- Reg::UnalignReg uRegIn;563+ Reg::UnalignRegForLoad uRegIn;
564 564 
565 // 先拼好-1轴的索引565 // 先拼好-1轴的索引
566 Reg::Arange(lineRange, 0);566 Reg::Arange(lineRange, 0);
567 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);567 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);
568- Reg::CompareScalar<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);568+ Reg::Compares<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);
569 Reg::Arange<RangeType, Reg::IndexOrder::DECREASE_ORDER>(leftPadIdxReg,569 Reg::Arange<RangeType, Reg::IndexOrder::DECREASE_ORDER>(leftPadIdxReg,
570 lastLeftPadNum - decreaseOffset - modeOffset);570 lastLeftPadNum - decreaseOffset - modeOffset);
571- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);571+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);
572 572 
573 Reg::Arange<RangeType, Reg::IndexOrder::DECREASE_ORDER>(573 Reg::Arange<RangeType, Reg::IndexOrder::DECREASE_ORDER>(
574 rightPadIdxReg, lastRightPadArangeStart - decreaseOffset + modeOffset);574 rightPadIdxReg, lastRightPadArangeStart - decreaseOffset + modeOffset);
575- Reg::CompareScalar<RangeType, CMPMODE::LT>(rightMask, rightPadIdxReg, lastDimIdx + modeOffset, maskIdx);575+ Reg::Compares<RangeType, CMPMODE::LT>(rightMask, rightPadIdxReg, lastDimIdx + modeOffset, maskIdx);
576- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);576+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);
577 577 
578 // -3轴纯pad的索引, 包含末尾两根轴578 // -3轴纯pad的索引, 包含末尾两根轴
579 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {579 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {
580 Reg::Adds(lineRangeBk, lineRange, (RangeType)((lastTwoDimLoops - i - 1) * inStride1), maskIdx);580 Reg::Adds(lineRangeBk, lineRange, (RangeType)((lastTwoDimLoops - i - 1) * inStride1), maskIdx);
581 // -2轴leftpad行数, 索引都一样581 // -2轴leftpad行数, 索引都一样
582- __local_mem__ RangeType* idxAddrTmp = idxAddr + i * outStride1;582+ __ubuf__ RangeType* idxAddrTmp = idxAddr + i * outStride1;
583 for (uint16_t j = 0; j < last2LeftPadNum; j++) {583 for (uint16_t j = 0; j < last2LeftPadNum; j++) {
584 Reg::Adds(lineRangeNew, lineRangeBk,584 Reg::Adds(lineRangeNew, lineRangeBk,
585 (RangeType)((last2LeftPadNum - j - modeOffset) * lastInDimSize), maskIdx);585 (RangeType)((last2LeftPadNum - j - modeOffset) * lastInDimSize), maskIdx);
586- Reg::DataCopyUnAlign(idxAddrTmp, lineRangeNew, uReg, outStride2);586+ Reg::StoreUnAlign(idxAddrTmp, lineRangeNew, uReg, outStride2);
587 }587 }
588- Reg::DataCopyUnAlignPost(idxAddrTmp, uReg, 0);588+ Reg::StoreUnAlignPost(idxAddrTmp, uReg, 0);
589 589 
590 // -2 轴inputshape, 索引递增590 // -2 轴inputshape, 索引递增
591- __local_mem__ RangeType* idxAddrTmp1 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2;591+ __ubuf__ RangeType* idxAddrTmp1 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2;
592 for (uint16_t j = 0; j < lastSecInDimSize; j++) {592 for (uint16_t j = 0; j < lastSecInDimSize; j++) {
593 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(j * lastInDimSize), maskIdx);593 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(j * lastInDimSize), maskIdx);
594- Reg::DataCopyUnAlign(idxAddrTmp1, lineRangeNew, uReg, outStride2);594+ Reg::StoreUnAlign(idxAddrTmp1, lineRangeNew, uReg, outStride2);
595 }595 }
596- Reg::DataCopyUnAlignPost(idxAddrTmp1, uReg, 0);596+ Reg::StoreUnAlignPost(idxAddrTmp1, uReg, 0);
597 597 
598 // -2轴rightpad行数, 索引都一样598 // -2轴rightpad行数, 索引都一样
599 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(last2DimIdx * lastInDimSize), maskIdx);599 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(last2DimIdx * lastInDimSize), maskIdx);
600- __local_mem__ RangeType* idxAddrTmp2 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2 +600+ __ubuf__ RangeType* idxAddrTmp2 = idxAddr + i * outStride1 + last2LeftPadNum * outStride2 +
601- lastSecInDimSize * outStride2;601+ lastSecInDimSize * outStride2;
602 for (uint16_t j = 0; j < last2RightPadNum; j++) {602 for (uint16_t j = 0; j < last2RightPadNum; j++) {
603 Reg::Adds(lineRangeBk, lineRangeNew, (RangeType)((-1) * (j + 1 - modeOffset) * lastInDimSize),603 Reg::Adds(lineRangeBk, lineRangeNew, (RangeType)((-1) * (j + 1 - modeOffset) * lastInDimSize),
604 maskIdx);604 maskIdx);
605- Reg::DataCopyUnAlign(idxAddrTmp2, lineRangeBk, uReg, outStride2);605+ Reg::StoreUnAlign(idxAddrTmp2, lineRangeBk, uReg, outStride2);
606 }606 }
607- Reg::DataCopyUnAlignPost(idxAddrTmp2, uReg, 0);607+ Reg::StoreUnAlignPost(idxAddrTmp2, uReg, 0);
608 }608 }
609 609 
610 // -3轴有效输入的索引610 // -3轴有效输入的索引
611 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {611 for (uint16_t i = 0; i < lastTwoDimLoops; i++) {
612 Reg::Adds(lineRangeBk, lineRange, (RangeType)(i * inStride1), maskIdx);612 Reg::Adds(lineRangeBk, lineRange, (RangeType)(i * inStride1), maskIdx);
613 // -2轴leftpad行数, 索引都一样613 // -2轴leftpad行数, 索引都一样
614- __local_mem__ RangeType* idxAddrTmp = idxAddr2 + i * outStride1;614+ __ubuf__ RangeType* idxAddrTmp = idxAddr2 + i * outStride1;
615 for (uint16_t j = 0; j < last2LeftPadNum; j++) {615 for (uint16_t j = 0; j < last2LeftPadNum; j++) {
616 Reg::Adds(lineRangeNew, lineRangeBk,616 Reg::Adds(lineRangeNew, lineRangeBk,
617 (RangeType)((last2LeftPadNum - j - modeOffset) * lastInDimSize), maskIdx);617 (RangeType)((last2LeftPadNum - j - modeOffset) * lastInDimSize), maskIdx);
618- Reg::DataCopyUnAlign(idxAddrTmp, lineRangeNew, uReg, outStride2);618+ Reg::StoreUnAlign(idxAddrTmp, lineRangeNew, uReg, outStride2);
619 }619 }
620- Reg::DataCopyUnAlignPost(idxAddrTmp, uReg, 0);620+ Reg::StoreUnAlignPost(idxAddrTmp, uReg, 0);
621 621 
622 // -2 轴inputshape, 索引递增622 // -2 轴inputshape, 索引递增
623- __local_mem__ RangeType* idxAddrTmp1 = idxAddr2 + i * outStride1 + last2LeftPadNum * outStride2;623+ __ubuf__ RangeType* idxAddrTmp1 = idxAddr2 + i * outStride1 + last2LeftPadNum * outStride2;
624 for (uint16_t j = 0; j < lastSecInDimSize; j++) {624 for (uint16_t j = 0; j < lastSecInDimSize; j++) {
625 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(j * lastInDimSize), maskIdx);625 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(j * lastInDimSize), maskIdx);
626- Reg::DataCopyUnAlign(idxAddrTmp1, lineRangeNew, uReg, outStride2);626+ Reg::StoreUnAlign(idxAddrTmp1, lineRangeNew, uReg, outStride2);
627 }627 }
628- Reg::DataCopyUnAlignPost(idxAddrTmp1, uReg, 0);628+ Reg::StoreUnAlignPost(idxAddrTmp1, uReg, 0);
629 629 
630 // -2轴rightpad行数, 索引都一样630 // -2轴rightpad行数, 索引都一样
631 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(last2DimIdx * lastInDimSize), maskIdx);631 Reg::Adds(lineRangeNew, lineRangeBk, (RangeType)(last2DimIdx * lastInDimSize), maskIdx);
632- __local_mem__ RangeType* idxAddrTmp2 = idxAddr2 + i * outStride1 + last2LeftPadNum * outStride2 +632+ __ubuf__ RangeType* idxAddrTmp2 = idxAddr2 + i * outStride1 + last2LeftPadNum * outStride2 +
633- lastSecInDimSize * outStride2;633+ lastSecInDimSize * outStride2;
634 for (uint16_t j = 0; j < last2RightPadNum; j++) {634 for (uint16_t j = 0; j < last2RightPadNum; j++) {
635 Reg::Adds(lineRangeBk, lineRangeNew, (RangeType)((-1) * (j + 1 - modeOffset) * lastInDimSize),635 Reg::Adds(lineRangeBk, lineRangeNew, (RangeType)((-1) * (j + 1 - modeOffset) * lastInDimSize),
636 maskIdx);636 maskIdx);
637- Reg::DataCopyUnAlign(idxAddrTmp2, lineRangeBk, uReg, outStride2);637+ Reg::StoreUnAlign(idxAddrTmp2, lineRangeBk, uReg, outStride2);
638 }638 }
639- Reg::DataCopyUnAlignPost(idxAddrTmp2, uReg, 0);639+ Reg::StoreUnAlignPost(idxAddrTmp2, uReg, 0);
640 }640 }
641 }641 }
642 }642 }
@@ -649,8 +649,8 @@ private:
649 uint32_t lastOutDimSize = tdPtr_->outShape[dimNum_ - 1];649 uint32_t lastOutDimSize = tdPtr_->outShape[dimNum_ - 1];
650 uint16_t lastDimsLeft = vlSplitIn_;650 uint16_t lastDimsLeft = vlSplitIn_;
651 RangeType lastDimIdx = lastInDimSize - 1;651 RangeType lastDimIdx = lastInDimSize - 1;
652- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();652+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
653- __local_mem__ RangeType* idxAddr2 = (__local_mem__ RangeType*)idxTensor.GetPhyAddr() + VL_RANGE_CNT;653+ __ubuf__ RangeType* idxAddr2 = (__ubuf__ RangeType*)idxTensor.GetPhyAddr() + VL_RANGE_CNT;
654 uint32_t decreaseOffset = VL_RANGE_CNT - 1;654 uint32_t decreaseOffset = VL_RANGE_CNT - 1;
655 uint32_t lastRightPadArangeStart = lastLeftPadNum + 2 * lastDimIdx;655 uint32_t lastRightPadArangeStart = lastLeftPadNum + 2 * lastDimIdx;
656 uint32_t modeOffset = 1;656 uint32_t modeOffset = 1;
@@ -667,99 +667,95 @@ private:
667 Reg::RegTensor<RangeType> leftPadIdxReg;667 Reg::RegTensor<RangeType> leftPadIdxReg;
668 Reg::MaskReg rightMask;668 Reg::MaskReg rightMask;
669 Reg::RegTensor<RangeType> rightPadIdxReg;669 Reg::RegTensor<RangeType> rightPadIdxReg;
670- Reg::UnalignReg uReg;670+ Reg::UnalignRegForStore uReg;
671- Reg::UnalignReg uRegIn;671+ Reg::UnalignRegForStore uRegIn;
672 672 
673 // 先拼好-1轴的索引673 // 先拼好-1轴的索引
674 Reg::Arange(lineRange, 0);674 Reg::Arange(lineRange, 0);
675 // 先拷出去，防止索引尾部脏数据675 // 先拷出去，防止索引尾部脏数据
676- Reg::DataCopy(idxAddr, lineRange, maskIdx);676+ Reg::StoreAlign(idxAddr, lineRange, maskIdx);
677- Reg::DataCopy(idxAddr2, lineRange, maskIdx);677+ Reg::StoreAlign(idxAddr2, lineRange, maskIdx);
678 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();678 Reg::LocalMemBar<Reg::MemType::VEC_STORE, Reg::MemType::VEC_STORE>();
679 679 
680 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);680 Reg::Adds(lineRange, lineRange, ((RangeType)-1) * lastLeftPadNum, maskIdx);
681- Reg::CompareScalar<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);681+ Reg::Compares<RangeType, CMPMODE::LT>(leftMask, lineRange, 0, maskIdx);
682 Reg::Arange<RangeType, Reg::IndexOrder::DECREASE_ORDER>(leftPadIdxReg,682 Reg::Arange<RangeType, Reg::IndexOrder::DECREASE_ORDER>(leftPadIdxReg,
683 lastLeftPadNum - decreaseOffset - modeOffset);683 lastLeftPadNum - decreaseOffset - modeOffset);
684- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);684+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, leftPadIdxReg, leftMask);
685 685 
686 Reg::Arange<RangeType, Reg::IndexOrder::DECREASE_ORDER>(686 Reg::Arange<RangeType, Reg::IndexOrder::DECREASE_ORDER>(
687 rightPadIdxReg, lastRightPadArangeStart - decreaseOffset + modeOffset);687 rightPadIdxReg, lastRightPadArangeStart - decreaseOffset + modeOffset);
688- Reg::CompareScalar<RangeType, CMPMODE::LT>(rightMask, rightPadIdxReg, lastDimIdx + modeOffset, maskIdx);688+ Reg::Compares<RangeType, CMPMODE::LT>(rightMask, rightPadIdxReg, lastDimIdx + modeOffset, maskIdx);
689- Reg::Copy<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);689+ Reg::Move<RangeType, Reg::MaskMergeMode::MERGING>(lineRange, rightPadIdxReg, rightMask);
690 690 
691 // -2轴leftpad行数, 索引都一样691 // -2轴leftpad行数, 索引都一样
692- __local_mem__ RangeType* idxAddrTmp = idxAddr;692+ __ubuf__ RangeType* idxAddrTmp = idxAddr;
693 for (uint16_t i = 0; i < lastDimsLeft; i++) {693 for (uint16_t i = 0; i < lastDimsLeft; i++) {
694 RangeType loopStride = (RangeType)lastInDimSize *694 RangeType loopStride = (RangeType)lastInDimSize *
695 (lastDimsLeft - i - 1); // copyout需要带边界，故这里不区分mode695 (lastDimsLeft - i - 1); // copyout需要带边界，故这里不区分mode
696 Reg::Adds(lineRangeNew, lineRange, loopStride, maskIdx);696 Reg::Adds(lineRangeNew, lineRange, loopStride, maskIdx);
697- Reg::DataCopyUnAlign(idxAddrTmp, lineRangeNew, uReg, lastOutDimSize);697+ Reg::StoreUnAlign(idxAddrTmp, lineRangeNew, uReg, lastOutDimSize);
698 }698 }
699- Reg::DataCopyUnAlignPost(idxAddrTmp, uReg, 0);699+ Reg::StoreUnAlignPost(idxAddrTmp, uReg, 0);
700 700 
701 // -2轴有效输入的索引701 // -2轴有效输入的索引
702- __local_mem__ RangeType* idxAddrTmp2 = idxAddr2;702+ __ubuf__ RangeType* idxAddrTmp2 = idxAddr2;
703 for (uint16_t i = 0; i < lastDimsLeft; i++) {703 for (uint16_t i = 0; i < lastDimsLeft; i++) {
704 RangeType loopStride = (RangeType)lastInDimSize * i;704 RangeType loopStride = (RangeType)lastInDimSize * i;
705 Reg::Adds(lineRangeNew, lineRange, loopStride, maskIdx);705 Reg::Adds(lineRangeNew, lineRange, loopStride, maskIdx);
706- Reg::DataCopyUnAlign(idxAddrTmp2, lineRangeNew, uRegIn, lastOutDimSize);706+ Reg::StoreUnAlign(idxAddrTmp2, lineRangeNew, uRegIn, lastOutDimSize);
707 }707 }
708- Reg::DataCopyUnAlignPost(idxAddrTmp2, uRegIn, 0);708+ Reg::StoreUnAlignPost(idxAddrTmp2, uRegIn, 0);
709 }709 }
710 }710 }
711 711 
712 __aicore__ inline void VlInCopyProc(uint16_t inLoops, uint16_t lastInLoops, RangeType idxOffset, uint32_t maskValue,712 __aicore__ inline void VlInCopyProc(uint16_t inLoops, uint16_t lastInLoops, RangeType idxOffset, uint32_t maskValue,
713- uint32_t lastInMaskValue, __local_mem__ T* curInAddr,713+ uint32_t lastInMaskValue, __ubuf__ T* curInAddr, __ubuf__ T* curOutAddr,
714- __local_mem__ T* curOutAddr, Reg::RegTensor<RangeType>& regIdx,714+ Reg::RegTensor<RangeType>& regIdx, uint32_t idxPadOffset)
715- uint32_t idxPadOffset)
716 {715 {
717 Reg::RegTensor<T> regData;716 Reg::RegTensor<T> regData;
718 Reg::RegTensor<T> regDataT;717 Reg::RegTensor<T> regDataT;
719 Reg::RegTensor<RangeType> regIdxBk;718 Reg::RegTensor<RangeType> regIdxBk;
720 Reg::RegTensor<RangeType> regNewIdx;719 Reg::RegTensor<RangeType> regNewIdx;
721- Reg::UnalignReg uReg;720+ Reg::UnalignRegForStore uReg;
722 uint32_t validMask = maskValue;721 uint32_t validMask = maskValue;
723 if constexpr (sizeof(T) == 8) {722 if constexpr (sizeof(T) == 8) {
724 validMask = maskValue * 2;723 validMask = maskValue * 2;
725 }724 }
726 Reg::MaskReg maskIdx = Reg::UpdateMask<RangeType>(validMask);725 Reg::MaskReg maskIdx = Reg::UpdateMask<RangeType>(validMask);
727 726 
728- __local_mem__ T* outAddrTmp = curOutAddr;727+ __ubuf__ T* outAddrTmp = curOutAddr;
729 Reg::Adds(regIdxBk, regIdx, idxPadOffset, maskIdx);728 Reg::Adds(regIdxBk, regIdx, idxPadOffset, maskIdx);
730 for (uint16_t cpIdx = 0; cpIdx < inLoops; cpIdx++) {729 for (uint16_t cpIdx = 0; cpIdx < inLoops; cpIdx++) {
731 Reg::Adds(regNewIdx, regIdxBk, cpIdx * idxOffset, maskIdx);730 Reg::Adds(regNewIdx, regIdxBk, cpIdx * idxOffset, maskIdx);
732- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx,731+ Reg::Gather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx, maskIdx);
733- maskIdx);
734 if constexpr (sizeof(T) != 1) {732 if constexpr (sizeof(T) != 1) {
735- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, maskValue);733+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, maskValue);
736 } else {734 } else {
737 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);735 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
738- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, maskValue);736+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, maskValue);
739 }737 }
740 }738 }
741- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);739+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
742 for (uint16_t cpTailIdx = 0; cpTailIdx < lastInLoops; cpTailIdx++) {740 for (uint16_t cpTailIdx = 0; cpTailIdx < lastInLoops; cpTailIdx++) {
743 outAddrTmp = curOutAddr + inLoops * maskValue;741 outAddrTmp = curOutAddr + inLoops * maskValue;
744 Reg::Adds(regNewIdx, regIdxBk, inLoops * idxOffset, maskIdx);742 Reg::Adds(regNewIdx, regIdxBk, inLoops * idxOffset, maskIdx);
745- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx,743+ Reg::Gather((Reg::RegTensor<CastType>&)regData, curInAddr, (Reg::RegTensor<IdxType>&)regNewIdx, maskIdx);
746- maskIdx);
747 if constexpr (sizeof(T) != 1) {744 if constexpr (sizeof(T) != 1) {
748- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, lastInMaskValue);745+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, lastInMaskValue);
749 } else {746 } else {
750 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);747 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
751- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, lastInMaskValue);748+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, lastInMaskValue);
752 }749 }
753- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);750+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
754 }751 }
755 }752 }
756 753 
757 // gather一次，copy多次754 // gather一次，copy多次
758 __aicore__ inline void VlPaddingCopyProc(uint16_t gatherLoops, uint16_t padLoops, uint16_t lastPadLoops,755 __aicore__ inline void VlPaddingCopyProc(uint16_t gatherLoops, uint16_t padLoops, uint16_t lastPadLoops,
759- uint32_t maskValue, uint32_t lastPadMaskValue,756+ uint32_t maskValue, uint32_t lastPadMaskValue, __ubuf__ T* curPadInAddr,
760- __local_mem__ T* curPadInAddr, __local_mem__ T* curPadOutAddr,757+ __ubuf__ T* curPadOutAddr, Reg::RegTensor<RangeType>& regIdxPad,
761- Reg::RegTensor<RangeType>& regIdxPad, uint32_t idxPadOffset,758+ uint32_t idxPadOffset, RangeType idxOffset, uint16_t lastPadExcessIdx = 0)
762- RangeType idxOffset, uint16_t lastPadExcessIdx = 0)
763 {759 {
764 Reg::RegTensor<T> regData;760 Reg::RegTensor<T> regData;
765 Reg::RegTensor<T> regDataT;761 Reg::RegTensor<T> regDataT;
@@ -768,7 +764,7 @@ private:
768 Reg::RegTensor<RangeType> zeroIdxReg;764 Reg::RegTensor<RangeType> zeroIdxReg;
769 Reg::Duplicate(zeroIdxReg, (RangeType)0);765 Reg::Duplicate(zeroIdxReg, (RangeType)0);
770 Reg::MaskReg zeroMask;766 Reg::MaskReg zeroMask;
771- Reg::UnalignReg uReg;767+ Reg::UnalignRegForStore uReg;
772 uint32_t validMask = maskValue;768 uint32_t validMask = maskValue;
773 uint32_t validLastMask = lastPadMaskValue;769 uint32_t validLastMask = lastPadMaskValue;
774 if constexpr (sizeof(T) == 8) {770 if constexpr (sizeof(T) == 8) {
@@ -781,33 +777,33 @@ private:
781 for (uint16_t gIdx = 0; gIdx < gatherLoops; gIdx++) {777 for (uint16_t gIdx = 0; gIdx < gatherLoops; gIdx++) {
782 Reg::Adds(regIdxBk, regIdxPad, idxPadOffset, maskIdx);778 Reg::Adds(regIdxBk, regIdxPad, idxPadOffset, maskIdx);
783 // 完整vl循环779 // 完整vl循环
784- __local_mem__ T* outAddrTmp = curPadOutAddr + lastPadLoops * lastPadMaskValue;780+ __ubuf__ T* outAddrTmp = curPadOutAddr + lastPadLoops * lastPadMaskValue;
785 for (uint16_t pIdx = 0; pIdx < padLoops; pIdx++) {781 for (uint16_t pIdx = 0; pIdx < padLoops; pIdx++) {
786 Reg::Adds(regNewIdx, regIdxBk, (padLoops - pIdx - 1) * idxOffset, maskIdx);782 Reg::Adds(regNewIdx, regIdxBk, (padLoops - pIdx - 1) * idxOffset, maskIdx);
787 // gather一次，copy多次783 // gather一次，copy多次
788- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, curPadInAddr,784+ Reg::Gather((Reg::RegTensor<CastType>&)regData, curPadInAddr, (Reg::RegTensor<IdxType>&)regNewIdx,
789- (Reg::RegTensor<IdxType>&)regNewIdx, maskIdx);785+ maskIdx);
790 if constexpr (sizeof(T) != 1) {786 if constexpr (sizeof(T) != 1) {
791- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, maskValue);787+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, maskValue);
792 } else {788 } else {
793 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);789 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
794- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, maskValue);790+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, maskValue);
795 }791 }
796 }792 }
797- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);793+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
798 // vl 剩余的循环794 // vl 剩余的循环
799 for (uint16_t pTaiIdx = 0; pTaiIdx < lastPadLoops; pTaiIdx++) {795 for (uint16_t pTaiIdx = 0; pTaiIdx < lastPadLoops; pTaiIdx++) {
800 outAddrTmp = curPadOutAddr;796 outAddrTmp = curPadOutAddr;
801 Reg::Adds(regNewIdx, regIdxBk, padLoops * idxOffset - lastPadExcessIdx, maskLastIdx);797 Reg::Adds(regNewIdx, regIdxBk, padLoops * idxOffset - lastPadExcessIdx, maskLastIdx);
802- Reg::DataCopyGather((Reg::RegTensor<CastType>&)regData, curPadInAddr,798+ Reg::Gather((Reg::RegTensor<CastType>&)regData, curPadInAddr, (Reg::RegTensor<IdxType>&)regNewIdx,
803- (Reg::RegTensor<IdxType>&)regNewIdx, maskLastIdx);799+ maskLastIdx);
804 if constexpr (sizeof(T) != 1) {800 if constexpr (sizeof(T) != 1) {
805- Reg::DataCopyUnAlign(outAddrTmp, regData, uReg, lastPadMaskValue);801+ Reg::StoreUnAlign(outAddrTmp, regData, uReg, lastPadMaskValue);
806 } else {802 } else {
807 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);803 Reg::Pack(regDataT, (Reg::RegTensor<CastType>&)regData);
808- Reg::DataCopyUnAlign(outAddrTmp, regDataT, uReg, lastPadMaskValue);804+ Reg::StoreUnAlign(outAddrTmp, regDataT, uReg, lastPadMaskValue);
809 }805 }
810- Reg::DataCopyUnAlignPost(outAddrTmp, uReg, 0);806+ Reg::StoreUnAlignPost(outAddrTmp, uReg, 0);
811 }807 }
812 }808 }
813 }809 }
@@ -820,10 +816,10 @@ private:
820 __aicore__ inline void GatherProcessUb2DFw(const LocalTensor<RangeType>& idxTensor, LocalTensor<T>& inTensor,816 __aicore__ inline void GatherProcessUb2DFw(const LocalTensor<RangeType>& idxTensor, LocalTensor<T>& inTensor,
821 LocalTensor<T>& outTensor, uint16_t ubAxisInCopyNum)817 LocalTensor<T>& outTensor, uint16_t ubAxisInCopyNum)
822 {818 {
823- __local_mem__ RangeType* idxAddrBw = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();819+ __ubuf__ RangeType* idxAddrBw = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
824- __local_mem__ RangeType* idxAddrFw = idxAddrBw + VL_RANGE_CNT;820+ __ubuf__ RangeType* idxAddrFw = idxAddrBw + VL_RANGE_CNT;
825- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();821+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
826- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr();822+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr();
827 823 
828 uint16_t vlSplitLoopIn = vlSplitIn_;824 uint16_t vlSplitLoopIn = vlSplitIn_;
829 RangeType idxOffset = tdPtr_->inStride[dimNum_ - CONST2] * vlSplitLoopIn;825 RangeType idxOffset = tdPtr_->inStride[dimNum_ - CONST2] * vlSplitLoopIn;
@@ -837,7 +833,7 @@ private:
837 __VEC_SCOPE__833 __VEC_SCOPE__
838 {834 {
839 Reg::RegTensor<RangeType> regIdx;835 Reg::RegTensor<RangeType> regIdx;
840- Reg::DataCopy(regIdx, idxAddrFw);836+ Reg::LoadAlign(regIdx, idxAddrFw);
841 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr, outAddr,837 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr, outAddr,
842 regIdx, 0);838 regIdx, 0);
843 }839 }
@@ -852,10 +848,10 @@ private:
852 __aicore__ inline void GatherProcessUb2DBw(const LocalTensor<RangeType>& idxTensor, LocalTensor<T>& inTensor,848 __aicore__ inline void GatherProcessUb2DBw(const LocalTensor<RangeType>& idxTensor, LocalTensor<T>& inTensor,
853 LocalTensor<T>& outTensor, uint16_t ubAxisInCopyNum)849 LocalTensor<T>& outTensor, uint16_t ubAxisInCopyNum)
854 {850 {
855- __local_mem__ RangeType* idxAddrBw = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();851+ __ubuf__ RangeType* idxAddrBw = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
856- __local_mem__ RangeType* idxAddrFw = idxAddrBw + VL_RANGE_CNT;852+ __ubuf__ RangeType* idxAddrFw = idxAddrBw + VL_RANGE_CNT;
857- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();853+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
858- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr() + BLOCK_NUM * CONST2;854+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr() + BLOCK_NUM * CONST2;
859 855 
860 uint16_t vlSplitLoopIn = vlSplitIn_;856 uint16_t vlSplitLoopIn = vlSplitIn_;
861 RangeType idxOffset = tdPtr_->inStride[dimNum_ - CONST2] * vlSplitLoopIn;857 RangeType idxOffset = tdPtr_->inStride[dimNum_ - CONST2] * vlSplitLoopIn;
@@ -873,7 +869,7 @@ private:
873 __VEC_SCOPE__869 __VEC_SCOPE__
874 {870 {
875 Reg::RegTensor<RangeType> regIdxPad;871 Reg::RegTensor<RangeType> regIdxPad;
876- Reg::DataCopy(regIdxPad, idxAddrBw);872+ Reg::LoadAlign(regIdxPad, idxAddrBw);
877 873 
878 VlPaddingCopyProc(1, copyInPadLoops, lastCopyInPadLoops, maskValue, lastCopyInMaskValue, inAddr, outAddr,874 VlPaddingCopyProc(1, copyInPadLoops, lastCopyInPadLoops, maskValue, lastCopyInMaskValue, inAddr, outAddr,
879 regIdxPad, 0, idxOffset, lastPadExcessIdx);875 regIdxPad, 0, idxOffset, lastPadExcessIdx);
@@ -888,10 +884,10 @@ private:
888 if constexpr (IS_FW) {884 if constexpr (IS_FW) {
889 isFw = true;885 isFw = true;
890 }886 }
891- __local_mem__ RangeType* idxAddrBw = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();887+ __ubuf__ RangeType* idxAddrBw = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
892- __local_mem__ RangeType* idxAddrFw = idxAddrBw + VL_RANGE_CNT;888+ __ubuf__ RangeType* idxAddrFw = idxAddrBw + VL_RANGE_CNT;
893- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();889+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
894- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr() + (isFw ? 0 : BLOCK_NUM * CONST2);890+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr() + (isFw ? 0 : BLOCK_NUM * CONST2);
895 891 
896 uint16_t vlSplitLoopIn = vlSplitIn_;892 uint16_t vlSplitLoopIn = vlSplitIn_;
897 uint32_t strideInVl = tdPtr_->inStride[dimNum_ - CONST2];893 uint32_t strideInVl = tdPtr_->inStride[dimNum_ - CONST2];
@@ -971,8 +967,8 @@ private:
971 {967 {
972 Reg::RegTensor<RangeType> regIdxPad;968 Reg::RegTensor<RangeType> regIdxPad;
973 Reg::RegTensor<RangeType> regIdx;969 Reg::RegTensor<RangeType> regIdx;
974- Reg::DataCopy(regIdxPad, idxAddrBw);970+ Reg::LoadAlign(regIdxPad, idxAddrBw);
975- Reg::DataCopy(regIdx, idxAddrFw);971+ Reg::LoadAlign(regIdx, idxAddrFw);
976 Reg::RegTensor<RangeType> regIdxPadFixed;972 Reg::RegTensor<RangeType> regIdxPadFixed;
977 973 
978 Reg::MaskReg maskIdx = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();974 Reg::MaskReg maskIdx = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();
@@ -988,7 +984,7 @@ private:
988 }984 }
989 // H轴左pad985 // H轴左pad
990 uint32_t idxPadOffset = uiIdx * strideInVlO1;986 uint32_t idxPadOffset = uiIdx * strideInVlO1;
991- __local_mem__ T* curInOutAddr = outAddr + fixedIdx * strideOutVlO1;987+ __ubuf__ T* curInOutAddr = outAddr + fixedIdx * strideOutVlO1;
992 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,988 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,
993 inAddr, curInOutAddr, regIdxPadFixed, idxPadOffset, idxOffset, lastLeftPadExcessIdx);989 inAddr, curInOutAddr, regIdxPadFixed, idxPadOffset, idxOffset, lastLeftPadExcessIdx);
994 990 
@@ -1038,10 +1034,10 @@ private:
1038 if constexpr (IS_FW) {1034 if constexpr (IS_FW) {
1039 isFw = true;1035 isFw = true;
1040 }1036 }
1041- __local_mem__ RangeType* idxPadAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();1037+ __ubuf__ RangeType* idxPadAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
1042- __local_mem__ RangeType* idxAddr = idxPadAddr + VL_RANGE_CNT;1038+ __ubuf__ RangeType* idxAddr = idxPadAddr + VL_RANGE_CNT;
1043- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();1039+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
1044- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr() + (isFw ? 0 : BLOCK_NUM * CONST2);1040+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr() + (isFw ? 0 : BLOCK_NUM * CONST2);
1045 1041 
1046 uint16_t vlSplitLoopIn = vlSplitIn_;1042 uint16_t vlSplitLoopIn = vlSplitIn_;
1047 uint16_t ubAxisLeftPadLoops = 0; // ubAxisLeftPadNum; 当前不支持N轴的pad, 只会为01043 uint16_t ubAxisLeftPadLoops = 0; // ubAxisLeftPadNum; 当前不支持N轴的pad, 只会为0
@@ -1144,8 +1140,8 @@ private:
1144 {1140 {
1145 Reg::RegTensor<RangeType> regIdxPad;1141 Reg::RegTensor<RangeType> regIdxPad;
1146 Reg::RegTensor<RangeType> regIdx;1142 Reg::RegTensor<RangeType> regIdx;
1147- Reg::DataCopy(regIdxPad, idxPadAddr);1143+ Reg::LoadAlign(regIdxPad, idxPadAddr);
1148- Reg::DataCopy(regIdx, idxAddr);1144+ Reg::LoadAlign(regIdx, idxAddr);
1149 Reg::RegTensor<RangeType> regIdxPadFixed;1145 Reg::RegTensor<RangeType> regIdxPadFixed;
1150 1146 
1151 Reg::MaskReg maskIdx = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();1147 Reg::MaskReg maskIdx = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();
@@ -1164,14 +1160,14 @@ private:
1164 for (uint16_t i = 0; i < vlO1LeftPadNum; i++) {1160 for (uint16_t i = 0; i < vlO1LeftPadNum; i++) {
1165 // H轴左pad1161 // H轴左pad
1166 uint32_t idxPadOffset = curInOffset + i * strideInVlO1;1162 uint32_t idxPadOffset = curInOffset + i * strideInVlO1;
1167- __local_mem__ T* curPadOutAddr = outAddr + curOutOffset + (vlO1LeftPadNum - 1 - i) * strideOutVlO1;1163+ __ubuf__ T* curPadOutAddr = outAddr + curOutOffset + (vlO1LeftPadNum - 1 - i) * strideOutVlO1;
1168 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,1164 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,
1169 inAddr, curPadOutAddr, regIdxPadFixed, idxPadOffset, idxOffset,1165 inAddr, curPadOutAddr, regIdxPadFixed, idxPadOffset, idxOffset,
1170 lastLeftPadExcessIdx);1166 lastLeftPadExcessIdx);
1171 1167 
1172 // H轴输入个数1168 // H轴输入个数
1173- __local_mem__ T* curOutAddr = outAddr + curOutOffset + (vlO1LeftPadNum - 1 - i) * strideOutVlO1 +1169+ __ubuf__ T* curOutAddr = outAddr + curOutOffset + (vlO1LeftPadNum - 1 - i) * strideOutVlO1 +
1174- vlLeftPadNum * strideOutVl;1170+ vlLeftPadNum * strideOutVl;
1175 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,1171 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,
1176 curOutAddr, regIdx, idxPadOffset);1172 curOutAddr, regIdx, idxPadOffset);
1177 1173 
@@ -1189,14 +1185,13 @@ private:
1189 for (uint16_t i = 0; i < vlO1InNum; i++) {1185 for (uint16_t i = 0; i < vlO1InNum; i++) {
1190 // H轴左pad, VL切3维时退化为C轴左pad1186 // H轴左pad, VL切3维时退化为C轴左pad
1191 uint32_t idxPadOffset = curInOffset + i * strideInVlO1 + modeCOffset2;1187 uint32_t idxPadOffset = curInOffset + i * strideInVlO1 + modeCOffset2;
1192- __local_mem__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;1188+ __ubuf__ T* curPadOutAddr = outAddr + curOutOffset + i * strideOutVlO1;
1193 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,1189 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,
1194 inAddr, curPadOutAddr, regIdxPadFixed, idxPadOffset, idxOffset,1190 inAddr, curPadOutAddr, regIdxPadFixed, idxPadOffset, idxOffset,
1195 lastLeftPadExcessIdx);1191 lastLeftPadExcessIdx);
1196 1192 
1197 // H轴输入有效个数, VL切3维时退化为C轴输入个数1193 // H轴输入有效个数, VL切3维时退化为C轴输入个数
1198- __local_mem__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 +1194+ __ubuf__ T* curOutAddr = outAddr + curOutOffset + i * strideOutVlO1 + vlLeftPadNum * strideOutVl;
1199- vlLeftPadNum * strideOutVl;
1200 idxPadOffset = curInOffset + i * strideInVlO1;1195 idxPadOffset = curInOffset + i * strideInVlO1;
1201 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,1196 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,
1202 curOutAddr, regIdx, idxPadOffset);1197 curOutAddr, regIdx, idxPadOffset);
@@ -1214,13 +1209,13 @@ private:
1214 curOutOffset = fixedIdx * strideOutN + vlO1LeftPadNum * strideOutVlO1 + vlO1InNum * strideOutVlO1;1209 curOutOffset = fixedIdx * strideOutN + vlO1LeftPadNum * strideOutVlO1 + vlO1InNum * strideOutVlO1;
1215 for (uint16_t i = 0; i < vlO1RightPadNum; i++) {1210 for (uint16_t i = 0; i < vlO1RightPadNum; i++) {
1216 uint32_t idxPadOffset = curInOffset + i * strideInVlO1;1211 uint32_t idxPadOffset = curInOffset + i * strideInVlO1;
1217- __local_mem__ T* curPadOutAddr = outAddr + curOutOffset + (vlO1RightPadNum - 1 - i) * strideOutVlO1;1212+ __ubuf__ T* curPadOutAddr = outAddr + curOutOffset + (vlO1RightPadNum - 1 - i) * strideOutVlO1;
1218 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,1213 VlPaddingCopyProc(leftGatherLoops, leftPadLoops, lastLeftPadLoops, maskValue, lastLeftPadMaskValue,
1219 inAddr, curPadOutAddr, regIdxPadFixed, idxPadOffset, idxOffset,1214 inAddr, curPadOutAddr, regIdxPadFixed, idxPadOffset, idxOffset,
1220 lastLeftPadExcessIdx);1215 lastLeftPadExcessIdx);
1221 1216 
1222- __local_mem__ T* curOutAddr = outAddr + curOutOffset + (vlO1RightPadNum - 1 - i) * strideOutVlO1 +1217+ __ubuf__ T* curOutAddr = outAddr + curOutOffset + (vlO1RightPadNum - 1 - i) * strideOutVlO1 +
1223- vlLeftPadNum * strideOutVl;1218+ vlLeftPadNum * strideOutVl;
1224 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,1219 VlInCopyProc(copyInPadLoops, lastCopyInPadLoops, idxOffset, maskValue, lastCopyInMaskValue, inAddr,
1225 curOutAddr, regIdx, idxPadOffset);1220 curOutAddr, regIdx, idxPadOffset);
1226 1221 
Mconversion/pad_v3/op_kernel/arch35/pad_mirror_huge_width.h+6-8
@@ -304,14 +304,13 @@ private:
304 maskReg = AscendC::Reg::UpdateMask<CastType>(leftUbCopyLenVF);304 maskReg = AscendC::Reg::UpdateMask<CastType>(leftUbCopyLenVF);
305 Reg::Arange<RangeType, AscendC::Reg::IndexOrder::DECREASE_ORDER>(305 Reg::Arange<RangeType, AscendC::Reg::IndexOrder::DECREASE_ORDER>(
306 idxReg, (RangeType)(leftIdxStart - rangeStart - k * oneRepeatSize));306 idxReg, (RangeType)(leftIdxStart - rangeStart - k * oneRepeatSize));
307- Reg::DataCopyGather((Reg::RegTensor<CastType>&)dataReg, srcAddr, (Reg::RegTensor<IdxType>&)idxReg,307+ Reg::Gather((Reg::RegTensor<CastType>&)dataReg, srcAddr, (Reg::RegTensor<IdxType>&)idxReg, maskReg);
308- maskReg);
309 if constexpr (sizeof(T) != 1) {308 if constexpr (sizeof(T) != 1) {
310- Reg::DataCopy(ubLeftAddr + k * oneRepeatSize, dataReg, maskReg);309+ Reg::StoreAlign(ubLeftAddr + k * oneRepeatSize, dataReg, maskReg);
311 } else {310 } else {
312 maskRegLowHalf = AscendC::Reg::UpdateMask<T>(leftUbCopyLenVFB8);311 maskRegLowHalf = AscendC::Reg::UpdateMask<T>(leftUbCopyLenVFB8);
313 Reg::Pack(dataB16ToB8Reg, (Reg::RegTensor<CastType>&)dataReg);312 Reg::Pack(dataB16ToB8Reg, (Reg::RegTensor<CastType>&)dataReg);
314- Reg::DataCopy(ubLeftAddr + k * oneRepeatSize, dataB16ToB8Reg, maskRegLowHalf);313+ Reg::StoreAlign(ubLeftAddr + k * oneRepeatSize, dataB16ToB8Reg, maskRegLowHalf);
315 }314 }
316 }315 }
317 }316 }
@@ -323,14 +322,13 @@ private:
323 maskReg = AscendC::Reg::UpdateMask<CastType>(rightUbCopyLenVF);322 maskReg = AscendC::Reg::UpdateMask<CastType>(rightUbCopyLenVF);
324 Reg::Arange<RangeType, AscendC::Reg::IndexOrder::DECREASE_ORDER>(323 Reg::Arange<RangeType, AscendC::Reg::IndexOrder::DECREASE_ORDER>(
325 idxReg, (RangeType)(rightIdxStart - rangeStart - k * oneRepeatSize));324 idxReg, (RangeType)(rightIdxStart - rangeStart - k * oneRepeatSize));
326- Reg::DataCopyGather((Reg::RegTensor<CastType>&)dataReg, srcAddr, (Reg::RegTensor<IdxType>&)idxReg,325+ Reg::Gather((Reg::RegTensor<CastType>&)dataReg, srcAddr, (Reg::RegTensor<IdxType>&)idxReg, maskReg);
327- maskReg);
328 if constexpr (sizeof(T) != 1) {326 if constexpr (sizeof(T) != 1) {
329- Reg::DataCopy(ubRightAddr + k * oneRepeatSize, dataReg, maskReg);327+ Reg::StoreAlign(ubRightAddr + k * oneRepeatSize, dataReg, maskReg);
330 } else {328 } else {
331 maskRegLowHalf = AscendC::Reg::UpdateMask<T>(rightUbCopyLenVFB8);329 maskRegLowHalf = AscendC::Reg::UpdateMask<T>(rightUbCopyLenVFB8);
332 Reg::Pack(dataB16ToB8Reg, (Reg::RegTensor<CastType>&)dataReg);330 Reg::Pack(dataB16ToB8Reg, (Reg::RegTensor<CastType>&)dataReg);
333- Reg::DataCopy(ubRightAddr + k * oneRepeatSize, dataB16ToB8Reg, maskRegLowHalf);331+ Reg::StoreAlign(ubRightAddr + k * oneRepeatSize, dataB16ToB8Reg, maskRegLowHalf);
334 }332 }
335 }333 }
336 }334 }
Mconversion/pad_v3/op_kernel/arch35/pad_mirror_normal_w.h+40-40
@@ -291,7 +291,7 @@ private:
291 291 
292 __aicore__ inline void GenIndex(const LocalTensor<RT>& dst, PadMirrNormalParam& padParam)292 __aicore__ inline void GenIndex(const LocalTensor<RT>& dst, PadMirrNormalParam& padParam)
293 {293 {
294- auto dstAddr = reinterpret_cast<__local_mem__ RT*>(dst.GetPhyAddr());294+ auto dstAddr = reinterpret_cast<__ubuf__ RT*>(dst.GetPhyAddr());
295 const int8_t dimNum = tilingData_->dimNum;295 const int8_t dimNum = tilingData_->dimNum;
296 const uint16_t hasRight = rightNum > 0 ? 1 : 0;296 const uint16_t hasRight = rightNum > 0 ? 1 : 0;
297 const uint16_t noLastRight = rightNum > 1 ? rightNum - 1 : 0;297 const uint16_t noLastRight = rightNum > 1 ? rightNum - 1 : 0;
@@ -335,44 +335,44 @@ private:
335 Reg::Arange<RT, AscendC::Reg::IndexOrder::DECREASE_ORDER>(rightIdx, firstIndexRight + 1);335 Reg::Arange<RT, AscendC::Reg::IndexOrder::DECREASE_ORDER>(rightIdx, firstIndexRight + 1);
336 336 
337 for (uint16_t i = 0; i < leftNum; i++) {337 for (uint16_t i = 0; i < leftNum; i++) {
338- AscendC::Reg::DataCopy(dstAddr + idOffset * VL_ELEMS_R, tempIdx, maskAll);338+ AscendC::Reg::StoreAlign(dstAddr + idOffset * VL_ELEMS_R, tempIdx, maskAll);
339 Adds(tempIdx, tempIdx, -1 * addsScale, maskAll);339 Adds(tempIdx, tempIdx, -1 * addsScale, maskAll);
340 idOffset += 1;340 idOffset += 1;
341 }341 }
342 for (uint16_t i = 0; i < leftCrossNum; i++) {342 for (uint16_t i = 0; i < leftCrossNum; i++) {
343 maskReg = AscendC::Reg::UpdateMask<RT>(leftLen);343 maskReg = AscendC::Reg::UpdateMask<RT>(leftLen);
344- AscendC::Reg::MaskNot(maskReg, maskReg, maskAll);344+ AscendC::Reg::Not(maskReg, maskReg, maskAll);
345- Copy(tempIdx, middleIdx, maskReg);345+ AscendC::Reg::Move(tempIdx, middleIdx, maskReg);
346 maskReg = AscendC::Reg::UpdateMask<RT>(endLLen);346 maskReg = AscendC::Reg::UpdateMask<RT>(endLLen);
347- AscendC::Reg::DataCopy(dstAddr + idOffset * VL_ELEMS_R, tempIdx, maskReg);347+ AscendC::Reg::StoreAlign(dstAddr + idOffset * VL_ELEMS_R, tempIdx, maskReg);
348 AscendC::Reg::Adds(middleIdx, middleIdx, addsScale, maskAll);348 AscendC::Reg::Adds(middleIdx, middleIdx, addsScale, maskAll);
349 idOffset += (1 - middleOffset);349 idOffset += (1 - middleOffset);
350 }350 }
351 maskReg = AscendC::Reg::UpdateMask<RT>(midLen);351 maskReg = AscendC::Reg::UpdateMask<RT>(midLen);
352 // leftcross和rightcross在同一block时，不copy mid352 // leftcross和rightcross在同一block时，不copy mid
353- Copy(tempIdx, middleIdx, maskReg);353+ AscendC::Reg::Move(tempIdx, middleIdx, maskReg);
354 for (uint16_t i = 0; i < middleNum; i++) {354 for (uint16_t i = 0; i < middleNum; i++) {
355- AscendC::Reg::DataCopy(dstAddr + idOffset * VL_ELEMS_R, tempIdx, maskAll);355+ AscendC::Reg::StoreAlign(dstAddr + idOffset * VL_ELEMS_R, tempIdx, maskAll);
356 AscendC::Reg::Adds(tempIdx, tempIdx, addsScale, maskAll);356 AscendC::Reg::Adds(tempIdx, tempIdx, addsScale, maskAll);
357 idOffset += 1;357 idOffset += 1;
358 }358 }
359 for (uint16_t i = 0; i < rightCrossNum; i++) {359 for (uint16_t i = 0; i < rightCrossNum; i++) {
360 maskReg = AscendC::Reg::UpdateMask<RT>(rightLen);360 maskReg = AscendC::Reg::UpdateMask<RT>(rightLen);
361- AscendC::Reg::MaskNot(maskReg, maskReg, maskAll);361+ AscendC::Reg::Not(maskReg, maskReg, maskAll);
362- Copy(tempIdx, rightIdx, maskReg);362+ AscendC::Reg::Move(tempIdx, rightIdx, maskReg);
363 maskReg = AscendC::Reg::UpdateMask<RT>(endRLen);363 maskReg = AscendC::Reg::UpdateMask<RT>(endRLen);
364- AscendC::Reg::DataCopy(dstAddr + idOffset * VL_ELEMS_R, tempIdx, maskReg);364+ AscendC::Reg::StoreAlign(dstAddr + idOffset * VL_ELEMS_R, tempIdx, maskReg);
365 idOffset += 1;365 idOffset += 1;
366 }366 }
367 for (uint16_t i = 0; i < noLastRight; i++) {367 for (uint16_t i = 0; i < noLastRight; i++) {
368 AscendC::Reg::Adds(rightIdx, rightIdx, -1 * addsScale, maskAll);368 AscendC::Reg::Adds(rightIdx, rightIdx, -1 * addsScale, maskAll);
369- AscendC::Reg::DataCopy(dstAddr + idOffset * VL_ELEMS_R, rightIdx, maskAll);369+ AscendC::Reg::StoreAlign(dstAddr + idOffset * VL_ELEMS_R, rightIdx, maskAll);
370 idOffset += 1;370 idOffset += 1;
371 }371 }
372 for (uint16_t i = 0; i < hasRight; i++) {372 for (uint16_t i = 0; i < hasRight; i++) {
373 maskReg = AscendC::Reg::UpdateMask<RT>(endLen);373 maskReg = AscendC::Reg::UpdateMask<RT>(endLen);
374 AscendC::Reg::Adds(rightIdx, rightIdx, -1 * addsScale, maskReg);374 AscendC::Reg::Adds(rightIdx, rightIdx, -1 * addsScale, maskReg);
375- AscendC::Reg::DataCopy(dstAddr + idOffset * VL_ELEMS_R, rightIdx, maskReg);375+ AscendC::Reg::StoreAlign(dstAddr + idOffset * VL_ELEMS_R, rightIdx, maskReg);
376 }376 }
377 }377 }
378 }378 }
@@ -380,9 +380,9 @@ private:
380 __aicore__ inline void GatherProcess(const LocalTensor<T>& dst, const LocalTensor<T>& src,380 __aicore__ inline void GatherProcess(const LocalTensor<T>& dst, const LocalTensor<T>& src,
381 const LocalTensor<RT>& idx, PadMirrNormalParam& padParam)381 const LocalTensor<RT>& idx, PadMirrNormalParam& padParam)
382 {382 {
383- auto dstAddr = reinterpret_cast<__local_mem__ T*>(dst.GetPhyAddr());383+ auto dstAddr = reinterpret_cast<__ubuf__ T*>(dst.GetPhyAddr());
384- auto srcAddr = reinterpret_cast<__local_mem__ T*>(src.GetPhyAddr());384+ auto srcAddr = reinterpret_cast<__ubuf__ T*>(src.GetPhyAddr());
385- auto idxAddr = reinterpret_cast<__local_mem__ RT*>(idx.GetPhyAddr());385+ auto idxAddr = reinterpret_cast<__ubuf__ RT*>(idx.GetPhyAddr());
386 const int8_t dimNum = tilingData_->dimNum;386 const int8_t dimNum = tilingData_->dimNum;
387 const uint16_t padVLNum = tilingData_->outShape[dimNum - 1] / VL_ELEMS_C;387 const uint16_t padVLNum = tilingData_->outShape[dimNum - 1] / VL_ELEMS_C;
388 const uint16_t endMaskLen = tilingData_->outShape[dimNum - 1] % VL_ELEMS_C;388 const uint16_t endMaskLen = tilingData_->outShape[dimNum - 1] % VL_ELEMS_C;
@@ -429,9 +429,9 @@ private:
429 }429 }
430 }430 }
431 431 
432- __aicore__ inline void GatherProcessLine(__local_mem__ T* dstAddr, __local_mem__ T* srcAddr,432+ __aicore__ inline void GatherProcessLine(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, __ubuf__ RT* idxAddr,
433- __local_mem__ RT* idxAddr, uint16_t padVLNum, uint16_t padBLNum,433+ uint16_t padVLNum, uint16_t padBLNum, Reg::MaskReg endMask,
434- Reg::MaskReg endMask, Reg::MaskReg maskAll)434+ Reg::MaskReg maskAll)
435 {435 {
436 __VEC_SCOPE__436 __VEC_SCOPE__
437 {437 {
@@ -440,25 +440,25 @@ private:
440 AscendC::Reg::RegTensor<T> dataT;440 AscendC::Reg::RegTensor<T> dataT;
441 441 
442 for (uint16_t i = 0; i < padVLNum; i++) {442 for (uint16_t i = 0; i < padVLNum; i++) {
443- AscendC::Reg::DataCopy(idxTmp, idxAddr + i * VL_ELEMS_C);443+ AscendC::Reg::LoadAlign(idxTmp, idxAddr + i * VL_ELEMS_C);
444- AscendC::Reg::DataCopyGather((Reg::RegTensor<CastType>&)dataTmp, srcAddr,444+ AscendC::Reg::Gather((Reg::RegTensor<CastType>&)dataTmp, srcAddr, (Reg::RegTensor<IdxType>&)idxTmp,
445- (Reg::RegTensor<IdxType>&)idxTmp, maskAll);445+ maskAll);
446 if constexpr (sizeof(T) != 1) {446 if constexpr (sizeof(T) != 1) {
447- Reg::DataCopy(dstAddr + i * VL_ELEMS_C, dataTmp, maskAll);447+ Reg::StoreAlign(dstAddr + i * VL_ELEMS_C, dataTmp, maskAll);
448 } else {448 } else {
449 Reg::Pack(dataT, (Reg::RegTensor<CastType>&)dataTmp);449 Reg::Pack(dataT, (Reg::RegTensor<CastType>&)dataTmp);
450- Reg::DataCopy(dstAddr + i * VL_ELEMS_C, dataT, maskAll);450+ Reg::StoreAlign(dstAddr + i * VL_ELEMS_C, dataT, maskAll);
451 }451 }
452 }452 }
453 for (uint16_t i = 0; i < padBLNum; i++) {453 for (uint16_t i = 0; i < padBLNum; i++) {
454- AscendC::Reg::DataCopy(idxTmp, idxAddr + padVLNum * VL_ELEMS_C);454+ AscendC::Reg::LoadAlign(idxTmp, idxAddr + padVLNum * VL_ELEMS_C);
455- AscendC::Reg::DataCopyGather((Reg::RegTensor<CastType>&)dataTmp, srcAddr,455+ AscendC::Reg::Gather((Reg::RegTensor<CastType>&)dataTmp, srcAddr, (Reg::RegTensor<IdxType>&)idxTmp,
456- (Reg::RegTensor<IdxType>&)idxTmp, endMask);456+ endMask);
457 if constexpr (sizeof(T) != 1) {457 if constexpr (sizeof(T) != 1) {
458- Reg::DataCopy(dstAddr + padVLNum * VL_ELEMS_C, dataTmp, endMask);458+ Reg::StoreAlign(dstAddr + padVLNum * VL_ELEMS_C, dataTmp, endMask);
459 } else {459 } else {
460 Reg::Pack(dataT, (Reg::RegTensor<CastType>&)dataTmp);460 Reg::Pack(dataT, (Reg::RegTensor<CastType>&)dataTmp);
461- Reg::DataCopy(dstAddr + padVLNum * VL_ELEMS_C, dataT, endMask);461+ Reg::StoreAlign(dstAddr + padVLNum * VL_ELEMS_C, dataT, endMask);
462 }462 }
463 }463 }
464 }464 }
@@ -467,8 +467,8 @@ private:
467 __aicore__ inline void MoveProcess(const LocalTensor<T>& dst, const LocalTensor<T>& src,467 __aicore__ inline void MoveProcess(const LocalTensor<T>& dst, const LocalTensor<T>& src,
468 PadMirrNormalParam& padParam)468 PadMirrNormalParam& padParam)
469 {469 {
470- auto dstAddr = reinterpret_cast<__local_mem__ T*>(dst.GetPhyAddr());470+ auto dstAddr = reinterpret_cast<__ubuf__ T*>(dst.GetPhyAddr());
471- auto srcAddr = reinterpret_cast<__local_mem__ T*>(src.GetPhyAddr());471+ auto srcAddr = reinterpret_cast<__ubuf__ T*>(src.GetPhyAddr());
472 const int8_t dimNum = tilingData_->dimNum;472 const int8_t dimNum = tilingData_->dimNum;
473 const uint16_t dimNNum = (UB_AXES < CONST4) ? 1 : inCopyLen_[dimNum - CONST4];473 const uint16_t dimNNum = (UB_AXES < CONST4) ? 1 : inCopyLen_[dimNum - CONST4];
474 const uint16_t dimCNum = (UB_AXES < CONST3) ? 1 : inCopyLen_[dimNum - CONST3];474 const uint16_t dimCNum = (UB_AXES < CONST3) ? 1 : inCopyLen_[dimNum - CONST3];
@@ -505,27 +505,27 @@ private:
505 }505 }
506 }506 }
507 507 
508- __aicore__ inline void MoveLine(__local_mem__ T* dstAddr, __local_mem__ T* srcAddr, uint16_t padVLNum,508+ __aicore__ inline void MoveLine(__ubuf__ T* dstAddr, __ubuf__ T* srcAddr, uint16_t padVLNum, uint16_t padBLNum,
509- uint16_t padBLNum, Reg::MaskReg endMask)509+ Reg::MaskReg endMask)
510 {510 {
511 __VEC_SCOPE__511 __VEC_SCOPE__
512 {512 {
513 AscendC::Reg::RegTensor<T> vRegTmp;513 AscendC::Reg::RegTensor<T> vRegTmp;
514 AscendC::Reg::MaskReg maskAll = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();514 AscendC::Reg::MaskReg maskAll = AscendC::Reg::CreateMask<T, AscendC::Reg::MaskPattern::ALL>();
515 for (uint16_t i = 0; i < padVLNum; i++) {515 for (uint16_t i = 0; i < padVLNum; i++) {
516- AscendC::Reg::DataCopy(vRegTmp, srcAddr + i * VL_ELEMS);516+ AscendC::Reg::LoadAlign(vRegTmp, srcAddr + i * VL_ELEMS);
517- AscendC::Reg::DataCopy(dstAddr + i * VL_ELEMS, vRegTmp, maskAll);517+ AscendC::Reg::StoreAlign(dstAddr + i * VL_ELEMS, vRegTmp, maskAll);
518 }518 }
519 for (uint16_t i = 0; i < padBLNum; i++) {519 for (uint16_t i = 0; i < padBLNum; i++) {
520- AscendC::Reg::DataCopy(vRegTmp, srcAddr + padVLNum * VL_ELEMS);520+ AscendC::Reg::LoadAlign(vRegTmp, srcAddr + padVLNum * VL_ELEMS);
521- AscendC::Reg::DataCopy(dstAddr + padVLNum * VL_ELEMS, vRegTmp, endMask);521+ AscendC::Reg::StoreAlign(dstAddr + padVLNum * VL_ELEMS, vRegTmp, endMask);
522 }522 }
523 }523 }
524 }524 }
525 525 
526 __aicore__ inline void Pad2DProcess(const LocalTensor<T>& dst, PadMirrNormalParam& padParam)526 __aicore__ inline void Pad2DProcess(const LocalTensor<T>& dst, PadMirrNormalParam& padParam)
527 {527 {
528- auto dstAddr = reinterpret_cast<__local_mem__ T*>(dst.GetPhyAddr());528+ auto dstAddr = reinterpret_cast<__ubuf__ T*>(dst.GetPhyAddr());
529 const int8_t dimNum = tilingData_->dimNum;529 const int8_t dimNum = tilingData_->dimNum;
530 const uint16_t modeOffset = MODE <= 1 ? 0 : 1;530 const uint16_t modeOffset = MODE <= 1 ? 0 : 1;
531 const uint16_t dimNNum = (UB_AXES < CONST4) ? 1 : inCopyLen_[dimNum - CONST4];531 const uint16_t dimNNum = (UB_AXES < CONST4) ? 1 : inCopyLen_[dimNum - CONST4];
@@ -582,7 +582,7 @@ private:
582 582 
583 __aicore__ inline void Pad3DProcess(const LocalTensor<T>& dst, PadMirrNormalParam& padParam)583 __aicore__ inline void Pad3DProcess(const LocalTensor<T>& dst, PadMirrNormalParam& padParam)
584 {584 {
585- auto dstAddr = reinterpret_cast<__local_mem__ T*>(dst.GetPhyAddr());585+ auto dstAddr = reinterpret_cast<__ubuf__ T*>(dst.GetPhyAddr());
586 const int8_t dimNum = tilingData_->dimNum;586 const int8_t dimNum = tilingData_->dimNum;
587 const uint16_t modeOffset = MODE <= 1 ? 0 : 1;587 const uint16_t modeOffset = MODE <= 1 ? 0 : 1;
588 const uint16_t dimNNum = inCopyLen_[dimNum - CONST4];588 const uint16_t dimNNum = inCopyLen_[dimNum - CONST4];
@@ -622,8 +622,8 @@ private:
622 __aicore__ inline void FlipProcess(const LocalTensor<T>& dst, const LocalTensor<T>& src,622 __aicore__ inline void FlipProcess(const LocalTensor<T>& dst, const LocalTensor<T>& src,
623 PadMirrNormalParam& padParam)623 PadMirrNormalParam& padParam)
624 {624 {
625- auto dstAddr = reinterpret_cast<__local_mem__ T*>(dst.GetPhyAddr());625+ auto dstAddr = reinterpret_cast<__ubuf__ T*>(dst.GetPhyAddr());
626- auto srcAddr = reinterpret_cast<__local_mem__ T*>(src.GetPhyAddr());626+ auto srcAddr = reinterpret_cast<__ubuf__ T*>(src.GetPhyAddr());
627 const int8_t dimNum = tilingData_->dimNum;627 const int8_t dimNum = tilingData_->dimNum;
628 const uint16_t dimNNum = (UB_AXES < CONST4) ? 1 : inCopyLen_[dimNum - CONST4];628 const uint16_t dimNNum = (UB_AXES < CONST4) ? 1 : inCopyLen_[dimNum - CONST4];
629 const uint16_t dimCNum = (UB_AXES < CONST3) ? 1 : inCopyLen_[dimNum - CONST3];629 const uint16_t dimCNum = (UB_AXES < CONST3) ? 1 : inCopyLen_[dimNum - CONST3];
Mconversion/pad_v3/op_kernel/arch35/pad_normal_width.h+20-20
@@ -385,52 +385,52 @@ private:
385 uint32_t noPadLen = noPadRightSize;385 uint32_t noPadLen = noPadRightSize;
386 uint32_t outLen = BLK_ELEMS;386 uint32_t outLen = BLK_ELEMS;
387 pMask = AscendC::Reg::UpdateMask<T, Trait>(noPadLen);387 pMask = AscendC::Reg::UpdateMask<T, Trait>(noPadLen);
388- AscendC::Reg::MaskNot(pMask, pMask, maskAll);388+ AscendC::Reg::Not(pMask, pMask, maskAll);
389 outMask = AscendC::Reg::UpdateMask<T, Trait>(outLen);389 outMask = AscendC::Reg::UpdateMask<T, Trait>(outLen);
390 if constexpr (UB_AXES == 2) {390 if constexpr (UB_AXES == 2) {
391 for (uint16_t n = 0; n < dimNNum / 2; n++) {391 for (uint16_t n = 0; n < dimNNum / 2; n++) {
392- AscendC::Reg::DataCopy(vReg, dstAddr + ubInOffset + padRigthFloorAlign + 2 * n * padCHW);392+ AscendC::Reg::LoadAlign(vReg, dstAddr + ubInOffset + padRigthFloorAlign + 2 * n * padCHW);
393 vRegTmp = vReg;393 vRegTmp = vReg;
394 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);394 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);
395- Copy(vReg, vRegTmp, pMask);395+ AscendC::Reg::Move(vReg, vRegTmp, pMask);
396- AscendC::Reg::DataCopy(dstAddr + ubInOffset + padRigthFloorAlign + 2 * n * padCHW, vReg, outMask);396+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + padRigthFloorAlign + 2 * n * padCHW, vReg, outMask);
397- AscendC::Reg::DataCopy(vReg, dstAddr + ubInOffset + padRigthFloorAlign + (2 * n + 1) * padCHW);397+ AscendC::Reg::LoadAlign(vReg, dstAddr + ubInOffset + padRigthFloorAlign + (2 * n + 1) * padCHW);
398 vRegTmp = vReg;398 vRegTmp = vReg;
399 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);399 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);
400- Copy(vReg, vRegTmp, pMask);400+ AscendC::Reg::Move(vReg, vRegTmp, pMask);
401- AscendC::Reg::DataCopy(dstAddr + ubInOffset + padRigthFloorAlign + (2 * n + 1) * padCHW, vReg,401+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + padRigthFloorAlign + (2 * n + 1) * padCHW, vReg,
402- outMask);402+ outMask);
403 }403 }
404 for (uint16_t i = 0; i < dimNNum % 2; i++) {404 for (uint16_t i = 0; i < dimNNum % 2; i++) {
405- AscendC::Reg::DataCopy(vReg, dstAddr + ubInOffset + padRigthFloorAlign + (dimNNum - 1) * padCHW);405+ AscendC::Reg::LoadAlign(vReg, dstAddr + ubInOffset + padRigthFloorAlign + (dimNNum - 1) * padCHW);
406 vRegTmp = vReg;406 vRegTmp = vReg;
407 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);407 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);
408- Copy(vReg, vRegTmp, pMask);408+ AscendC::Reg::Move(vReg, vRegTmp, pMask);
409- AscendC::Reg::DataCopy(dstAddr + ubInOffset + padRigthFloorAlign + (dimNNum - 1) * padCHW, vReg,409+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + padRigthFloorAlign + (dimNNum - 1) * padCHW, vReg,
410- outMask);410+ outMask);
411 }411 }
412 } else if constexpr (UB_AXES == 3) {412 } else if constexpr (UB_AXES == 3) {
413 for (uint16_t n = 0; n < dimNNum; n++) {413 for (uint16_t n = 0; n < dimNNum; n++) {
414 for (uint16_t c = 0; c < dimCNum; c++) {414 for (uint16_t c = 0; c < dimCNum; c++) {
415- AscendC::Reg::DataCopy(vReg,415+ AscendC::Reg::LoadAlign(vReg,
416- dstAddr + ubInOffset + padRigthFloorAlign + n * padCHW + c * padHW);416+ dstAddr + ubInOffset + padRigthFloorAlign + n * padCHW + c * padHW);
417 vRegTmp = vReg;417 vRegTmp = vReg;
418 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);418 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);
419- Copy(vReg, vRegTmp, pMask);419+ AscendC::Reg::Move(vReg, vRegTmp, pMask);
420- AscendC::Reg::DataCopy(dstAddr + ubInOffset + padRigthFloorAlign + n * padCHW + c * padHW, vReg,420+ AscendC::Reg::StoreAlign(dstAddr + ubInOffset + padRigthFloorAlign + n * padCHW + c * padHW,
421- outMask);421+ vReg, outMask);
422 }422 }
423 }423 }
424 } else {424 } else {
425 for (uint16_t n = 0; n < dimNNum; n++) {425 for (uint16_t n = 0; n < dimNNum; n++) {
426 for (uint16_t c = 0; c < dimCNum; c++) {426 for (uint16_t c = 0; c < dimCNum; c++) {
427 for (uint16_t h = 0; h < dimHNum; h++) {427 for (uint16_t h = 0; h < dimHNum; h++) {
428- AscendC::Reg::DataCopy(428+ AscendC::Reg::LoadAlign(
429 vReg, dstAddr + ubInOffset + padRigthFloorAlign + n * padCHW + c * padHW + h * padW);429 vReg, dstAddr + ubInOffset + padRigthFloorAlign + n * padCHW + c * padHW + h * padW);
430 vRegTmp = vReg;430 vRegTmp = vReg;
431 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);431 Duplicate<T, AscendC::Reg::MaskMergeMode::ZEROING, T>(vRegTmp, value, pMask);
432- Copy(vReg, vRegTmp, pMask);432+ AscendC::Reg::Move(vReg, vRegTmp, pMask);
433- AscendC::Reg::DataCopy(433+ AscendC::Reg::StoreAlign(
434 dstAddr + ubInOffset + padRigthFloorAlign + n * padCHW + c * padHW + h * padW, vReg,434 dstAddr + ubInOffset + padRigthFloorAlign + n * padCHW + c * padHW + h * padW, vReg,
435 outMask);435 outMask);
436 }436 }
Mconversion/pad_v3/op_kernel/arch35/pad_scatter.h+20-20
@@ -333,20 +333,20 @@ private:
333 int32_t outStride0 = lastThirdDimInVL_ ? tdPtr_->outStride[dimNum_ - CONST3] : 1;333 int32_t outStride0 = lastThirdDimInVL_ ? tdPtr_->outStride[dimNum_ - CONST3] : 1;
334 int32_t outStride1 = tdPtr_->outStride[dimNum_ - CONST2];334 int32_t outStride1 = tdPtr_->outStride[dimNum_ - CONST2];
335 335 
336- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();336+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
337 337 
338 __VEC_SCOPE__338 __VEC_SCOPE__
339 {339 {
340 Reg::RegTensor<RangeType> indexReg;340 Reg::RegTensor<RangeType> indexReg;
341 Reg::RegTensor<RangeType> validReg;341 Reg::RegTensor<RangeType> validReg;
342- Reg::UnalignReg uReg;342+ Reg::UnalignRegForStore uReg;
343 343 
344 for (uint16_t i = 0; i < loop0; i++) {344 for (uint16_t i = 0; i < loop0; i++) {
345 for (uint16_t j = 0; j < loop1; j++) {345 for (uint16_t j = 0; j < loop1; j++) {
346- __local_mem__ RangeType* idxAddrTmp = idxAddr + i * inStride0 + j * inStride1;346+ __ubuf__ RangeType* idxAddrTmp = idxAddr + i * inStride0 + j * inStride1;
347 Reg::Arange(validReg, startValue + i * outStride0 + j * outStride1);347 Reg::Arange(validReg, startValue + i * outStride0 + j * outStride1);
348- Reg::DataCopyUnAlign(idxAddrTmp, validReg, uReg, lastDimIn);348+ Reg::StoreUnAlign(idxAddrTmp, validReg, uReg, lastDimIn);
349- Reg::DataCopyUnAlignPost(idxAddrTmp, uReg, 0);349+ Reg::StoreUnAlignPost(idxAddrTmp, uReg, 0);
350 }350 }
351 }351 }
352 }352 }
@@ -355,9 +355,9 @@ private:
355 __aicore__ inline void ScatterProcess(const PadScatterParam& scatterParam, const LocalTensor<RangeType>& idxTensor,355 __aicore__ inline void ScatterProcess(const PadScatterParam& scatterParam, const LocalTensor<RangeType>& idxTensor,
356 LocalTensor<T>& inTensor, LocalTensor<T>& outTensor, uint32_t outUbStart)356 LocalTensor<T>& inTensor, LocalTensor<T>& outTensor, uint32_t outUbStart)
357 {357 {
358- __local_mem__ RangeType* idxAddr = (__local_mem__ RangeType*)idxTensor.GetPhyAddr();358+ __ubuf__ RangeType* idxAddr = (__ubuf__ RangeType*)idxTensor.GetPhyAddr();
359- __local_mem__ T* inAddr = (__local_mem__ T*)inTensor.GetPhyAddr();359+ __ubuf__ T* inAddr = (__ubuf__ T*)inTensor.GetPhyAddr();
360- __local_mem__ T* outAddr = (__local_mem__ T*)outTensor.GetPhyAddr();360+ __ubuf__ T* outAddr = (__ubuf__ T*)outTensor.GetPhyAddr();
361 361 
362 uint32_t vlSplitLoopIn = vlSplitIn_;362 uint32_t vlSplitLoopIn = vlSplitIn_;
363 if constexpr (sizeof(T) == 1) {363 if constexpr (sizeof(T) == 1) {
@@ -396,38 +396,38 @@ private:
396 Reg::MaskReg maskIdx = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();396 Reg::MaskReg maskIdx = Reg::CreateMask<RangeType, Reg::MaskPattern::ALL>();
397 Reg::MaskReg maskData;397 Reg::MaskReg maskData;
398 Reg::MaskReg pregT;398 Reg::MaskReg pregT;
399- Reg::UnalignReg uReg;399+ Reg::UnalignRegForLoad uReg;
400 400 
401- Reg::DataCopy(regIdx, idxAddr);401+ Reg::LoadAlign(regIdx, idxAddr);
402 402 
403 for (uint16_t nIdx = 0; nIdx < axisVlO2; nIdx++) {403 for (uint16_t nIdx = 0; nIdx < axisVlO2; nIdx++) {
404 for (uint16_t cIdx = 0; cIdx < axisVlO1; cIdx++) {404 for (uint16_t cIdx = 0; cIdx < axisVlO1; cIdx++) {
405- __local_mem__ T* inAddrTmp = inAddr + nIdx * strideInVlO2 + cIdx * strideInVlO1;405+ __ubuf__ T* inAddrTmp = inAddr + nIdx * strideInVlO2 + cIdx * strideInVlO1;
406 RangeType addsScale = nIdx * strideOutVlO2 + cIdx * strideOutVlO1 + outUbStart;406 RangeType addsScale = nIdx * strideOutVlO2 + cIdx * strideOutVlO1 + outUbStart;
407- Reg::DataCopyUnAlignPre(uReg, inAddrTmp);407+ Reg::LoadUnAlignPre(uReg, inAddrTmp);
408 for (uint16_t hIdx = 0; hIdx < vlSplitLoopCnt; hIdx++) {408 for (uint16_t hIdx = 0; hIdx < vlSplitLoopCnt; hIdx++) {
409 Reg::Adds(regIdxBK, regIdx, (RangeType)(hIdx * idxOffset + addsScale), maskIdx);409 Reg::Adds(regIdxBK, regIdx, (RangeType)(hIdx * idxOffset + addsScale), maskIdx);
410 410 
411- Reg::DataCopyUnAlign(regData, uReg, inAddrTmp, maskValue); // maskValue 实际搬入的长度411+ Reg::LoadUnAlign(regData, uReg, inAddrTmp, maskValue); // maskValue 实际搬入的长度
412 if constexpr (sizeof(T) != 1) {412 if constexpr (sizeof(T) != 1) {
413- Reg::DataCopyScatter(outAddr, regData, (Reg::RegTensor<IdxType>&)regIdxBK, maskMain);413+ Reg::Scatter(outAddr, regData, (Reg::RegTensor<IdxType>&)regIdxBK, maskMain);
414 } else {414 } else {
415 Reg::UnPack((Reg::RegTensor<CastType>&)regDataT, regData);415 Reg::UnPack((Reg::RegTensor<CastType>&)regDataT, regData);
416- Reg::DataCopyScatter(outAddr, regDataT, (Reg::RegTensor<IdxType>&)regIdxBK, maskMain);416+ Reg::Scatter(outAddr, regDataT, (Reg::RegTensor<IdxType>&)regIdxBK, maskMain);
417 }417 }
418 }418 }
419 419 
420 for (uint16_t hTail = 0; hTail < vlSplitTailLoopCnt; hTail++) {420 for (uint16_t hTail = 0; hTail < vlSplitTailLoopCnt; hTail++) {
421 inAddrTmp = inAddr + nIdx * strideInVlO2 + cIdx * strideInVlO1 + vlSplitLoopCnt * maskValue;421 inAddrTmp = inAddr + nIdx * strideInVlO2 + cIdx * strideInVlO1 + vlSplitLoopCnt * maskValue;
422- Reg::DataCopyUnAlignPre(uReg, inAddrTmp);422+ Reg::LoadUnAlignPre(uReg, inAddrTmp);
423 Reg::Adds(regIdxBK, regIdx, (RangeType)(vlSplitLoopCnt * idxOffset + addsScale), maskIdx);423 Reg::Adds(regIdxBK, regIdx, (RangeType)(vlSplitLoopCnt * idxOffset + addsScale), maskIdx);
424- Reg::DataCopyUnAlign(regData, uReg, inAddrTmp,424+ Reg::LoadUnAlign(regData, uReg, inAddrTmp,
425- maskValueTail); // maskValueTail 实际搬入的长度425+ maskValueTail); // maskValueTail 实际搬入的长度
426 if constexpr (sizeof(T) != 1) {426 if constexpr (sizeof(T) != 1) {
427- Reg::DataCopyScatter(outAddr, regData, (Reg::RegTensor<IdxType>&)regIdxBK, maskTail);427+ Reg::Scatter(outAddr, regData, (Reg::RegTensor<IdxType>&)regIdxBK, maskTail);
428 } else {428 } else {
429 Reg::UnPack((Reg::RegTensor<CastType>&)regDataT, regData);429 Reg::UnPack((Reg::RegTensor<CastType>&)regDataT, regData);
430- Reg::DataCopyScatter(outAddr, regDataT, (Reg::RegTensor<IdxType>&)regIdxBK, maskTail);430+ Reg::Scatter(outAddr, regDataT, (Reg::RegTensor<IdxType>&)regIdxBK, maskTail);
431 }431 }
432 }432 }
433 }433 }
Mconversion/pad_v3_grad/examples/test_geir_pad_v3_grad.cpp+3-3
@@ -250,7 +250,7 @@ int main(int argc, char* argv[])
250 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};250 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
251 Status ret = ge::GEInitialize(global_options);251 Status ret = ge::GEInitialize(global_options);
252 if (ret != SUCCESS) {252 if (ret != SUCCESS) {
253- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());253+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
254 return FAILED;254 return FAILED;
255 }255 }
256 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());256 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -301,7 +301,7 @@ int main(int argc, char* argv[])
301 std::vector<ge::Tensor> output;301 std::vector<ge::Tensor> output;
302 ret = session->RunGraph(graph_id, input, output);302 ret = session->RunGraph(graph_id, input, output);
303 if (ret != SUCCESS) {303 if (ret != SUCCESS) {
304- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());304+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
305 delete session;305 delete session;
306 GEFinalize();306 GEFinalize();
307 return FAILED;307 return FAILED;
@@ -319,7 +319,7 @@ int main(int argc, char* argv[])
319 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());319 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
320 ret = ge::GEFinalize();320 ret = ge::GEFinalize();
321 if (ret != SUCCESS) {321 if (ret != SUCCESS) {
322- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());322+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
323 return FAILED;323 return FAILED;
324 }324 }
325 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());325 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mconversion/pad_v3_grad/op_host/arch35/pad_v3_grad_tiling_arch35.cpp+8-8
@@ -142,7 +142,7 @@ void PadV3GradACTiling::GetOptimizeTiling(const PadV3GradUbTileInfo& oldTilingIn
142 // ubPerCoreCnt 不发生变化为前提时，最多循环coreNum+dimNum_次就可以找到最优解, 这里仅做防死循环保护142 // ubPerCoreCnt 不发生变化为前提时，最多循环coreNum+dimNum_次就可以找到最优解, 这里仅做防死循环保护
143 uint32_t maxLoop = coreNum_ + dimNum_;143 uint32_t maxLoop = coreNum_ + dimNum_;
144 uint32_t loops = 0;144 uint32_t loops = 0;
145- bool finded = false;145+ bool found = false;
146 for (uint8_t iDim = oldTilingInfo.ubSplitAxis; iDim < dimNum_; iDim++) {146 for (uint8_t iDim = oldTilingInfo.ubSplitAxis; iDim < dimNum_; iDim++) {
147 if (iDim != oldTilingInfo.ubSplitAxis) {147 if (iDim != oldTilingInfo.ubSplitAxis) {
148 outCount *= tilingData_->outShape[iDim - 1];148 outCount *= tilingData_->outShape[iDim - 1];
@@ -153,7 +153,7 @@ void PadV3GradACTiling::GetOptimizeTiling(const PadV3GradUbTileInfo& oldTilingIn
153 for (int64_t factor = iDimFactor; factor > 0;) {153 for (int64_t factor = iDimFactor; factor > 0;) {
154 loops++;154 loops++;
155 if (loops > maxLoop) {155 if (loops > maxLoop) {
156- finded = true;156+ found = true;
157 OP_LOGD(context_, "loops:%u is bigger than maxLoop:%u", loops, maxLoop);157 OP_LOGD(context_, "loops:%u is bigger than maxLoop:%u", loops, maxLoop);
158 break;158 break;
159 }159 }
@@ -172,14 +172,14 @@ void PadV3GradACTiling::GetOptimizeTiling(const PadV3GradUbTileInfo& oldTilingIn
172 if (oldTilingInfo.ubPerCoreCnt != tmpPerCount) {172 if (oldTilingInfo.ubPerCoreCnt != tmpPerCount) {
173 OP_LOGD(context_, "iDim:%u factor:%ld tmpPerCount:%ld not equal ubPerCoreCnt:%ld", iDim, factor,173 OP_LOGD(context_, "iDim:%u factor:%ld tmpPerCount:%ld not equal ubPerCoreCnt:%ld", iDim, factor,
174 tmpPerCount, oldTilingInfo.ubPerCoreCnt);174 tmpPerCount, oldTilingInfo.ubPerCoreCnt);
175- finded = true;175+ found = true;
176 break;176 break;
177 }177 }
178 178 
179 if (factor * tilingData_->inStride[iDim] * dtypeBytes_ < MIN_PER_UB_SIZE ||179 if (factor * tilingData_->inStride[iDim] * dtypeBytes_ < MIN_PER_UB_SIZE ||
180 tmpFactor * tilingData_->inStride[iDim] * dtypeBytes_ < MIN_PER_UB_SIZE) {180 tmpFactor * tilingData_->inStride[iDim] * dtypeBytes_ < MIN_PER_UB_SIZE) {
181 OP_LOGD(context_, "iDim:%u factor:%ld tmpFactor:%ld in ubSize is too small", iDim, factor, tmpFactor);181 OP_LOGD(context_, "iDim:%u factor:%ld tmpFactor:%ld in ubSize is too small", iDim, factor, tmpFactor);
182- finded = true;182+ found = true;
183 break;183 break;
184 }184 }
185 185 
@@ -193,16 +193,16 @@ void PadV3GradACTiling::GetOptimizeTiling(const PadV3GradUbTileInfo& oldTilingIn
193 OP_LOGD(context_, "current iDim:%u factor:%ld iDimOuter:%ld tmpFactor:%ld tmpCoreNum:%ld usedRate:%f", iDim,193 OP_LOGD(context_, "current iDim:%u factor:%ld iDimOuter:%ld tmpFactor:%ld tmpCoreNum:%ld usedRate:%f", iDim,
194 factor, iDimOuter, tmpFactor, tmpCoreNum, usedRate);194 factor, iDimOuter, tmpFactor, tmpCoreNum, usedRate);
195 if (usedRate >= MIN_USED_CORES_RATIO) {195 if (usedRate >= MIN_USED_CORES_RATIO) {
196- finded = true;196+ found = true;
197 break;197 break;
198 }198 }
199 factor = tmpFactor - 1;199 factor = tmpFactor - 1;
200 }200 }
201 201 
202- OP_LOGD(context_, "iDim:%u ubSplitAxis:%u ubSplitFactor:%u loops:%u finded:%d", iDim, newTilingInfo.ubSplitAxis,202+ OP_LOGD(context_, "iDim:%u ubSplitAxis:%u ubSplitFactor:%u loops:%u found:%d", iDim, newTilingInfo.ubSplitAxis,
203- newTilingInfo.ubSplitFactor, loops, finded);203+ newTilingInfo.ubSplitFactor, loops, found);
204 204 
205- if (finded) {205+ if (found) {
206 break;206 break;
207 }207 }
208 }208 }
Mconversion/pad_v3_grad/op_kernel/arch35/pad_v3_grad_mirror_normal.h+106-109
@@ -295,7 +295,7 @@ private:
295 // 3. Right pad mirror: grad_y[2*outW + leftPad - 2 - w + modeOffset_] if applicable295 // 3. Right pad mirror: grad_y[2*outW + leftPad - 2 - w + modeOffset_] if applicable
296 __aicore__ inline void GradGatherProcess(const LocalTensor<T>& dst)296 __aicore__ inline void GradGatherProcess(const LocalTensor<T>& dst)
297 {297 {
298- __local_mem__ T* dstAddr = reinterpret_cast<__local_mem__ T*>(dst.GetPhyAddr());298+ __ubuf__ T* dstAddr = reinterpret_cast<__ubuf__ T*>(dst.GetPhyAddr());
299 const uint32_t outW = tilingData_->outShape[dimNum_ - 1]; // grad_x W299 const uint32_t outW = tilingData_->outShape[dimNum_ - 1]; // grad_x W
300 const uint32_t inW = tilingData_->inShape[dimNum_ - 1]; // grad_y W300 const uint32_t inW = tilingData_->inShape[dimNum_ - 1]; // grad_y W
301 const uint32_t leftPad = padParam_.padLeft;301 const uint32_t leftPad = padParam_.padLeft;
@@ -330,7 +330,7 @@ private:
330 GradAccumulateHRelatedToTmpBuf(tmpLocal, dimHIn, padWI);330 GradAccumulateHRelatedToTmpBuf(tmpLocal, dimHIn, padWI);
331 331 
332 // Step 3: W 维度梯度累加332 // Step 3: W 维度梯度累加
333- __local_mem__ PromoteDataT* tmpAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(tmpLocal.GetPhyAddr());333+ __ubuf__ PromoteDataT* tmpAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpLocal.GetPhyAddr());
334 for (uint32_t h = 0; h < dimHIn; h++) {334 for (uint32_t h = 0; h < dimHIn; h++) {
335 GradProcessLineFromTmpBuf(dstAddr + h * padWO, tmpAddr + h * padWI, outW, inW, leftPad, rightPad);335 GradProcessLineFromTmpBuf(dstAddr + h * padWO, tmpAddr + h * padWI, outW, inW, leftPad, rightPad);
336 }336 }
@@ -338,7 +338,7 @@ private:
338 // axisNumInUb_=3: UB 内包含 inCopyLen_[C] × inShape[H] × inShape[W]338 // axisNumInUb_=3: UB 内包含 inCopyLen_[C] × inShape[H] × inShape[W]
339 // C 是切分轴，UB 内只有部分 C slice339 // C 是切分轴，UB 内只有部分 C slice
340 LocalTensor<PromoteDataT> tmpLocal = tmpBuf_.Get<PromoteDataT>();340 LocalTensor<PromoteDataT> tmpLocal = tmpBuf_.Get<PromoteDataT>();
341- __local_mem__ PromoteDataT* tmpAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(tmpLocal.GetPhyAddr());341+ __ubuf__ PromoteDataT* tmpAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpLocal.GetPhyAddr());
342 const uint32_t leftPadH = tilingData_->leftPad[dimNum_ - CONST2];342 const uint32_t leftPadH = tilingData_->leftPad[dimNum_ - CONST2];
343 const uint32_t sliceSize = dimHIn * padWI; // 一个 C slice 在 tmpLocal 中的元素数343 const uint32_t sliceSize = dimHIn * padWI; // 一个 C slice 在 tmpLocal 中的元素数
344 344 
@@ -365,7 +365,7 @@ private:
365 // axisNumInUb_=4: UB 内包含 inCopyLen_[N] × inShape[C] × inShape[H] × inShape[W]365 // axisNumInUb_=4: UB 内包含 inCopyLen_[N] × inShape[C] × inShape[H] × inShape[W]
366 // N 是切分轴，C/H/W 完整在 UB 内366 // N 是切分轴，C/H/W 完整在 UB 内
367 LocalTensor<PromoteDataT> tmpLocal = tmpBuf_.Get<PromoteDataT>();367 LocalTensor<PromoteDataT> tmpLocal = tmpBuf_.Get<PromoteDataT>();
368- __local_mem__ PromoteDataT* tmpAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(tmpLocal.GetPhyAddr());368+ __ubuf__ PromoteDataT* tmpAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpLocal.GetPhyAddr());
369 const uint32_t leftPadH = tilingData_->leftPad[dimNum_ - CONST2];369 const uint32_t leftPadH = tilingData_->leftPad[dimNum_ - CONST2];
370 const uint32_t leftPadC = tilingData_->leftPad[dimNum_ - CONST3];370 const uint32_t leftPadC = tilingData_->leftPad[dimNum_ - CONST3];
371 const uint32_t hSliceSize = dimHIn * padWI; // 一个 H slice (一个 C plane)371 const uint32_t hSliceSize = dimHIn * padWI; // 一个 H slice (一个 C plane)
@@ -411,11 +411,11 @@ private:
411 {411 {
412 const uint32_t inW = tilingData_->inShape[dimNum_ - 1];412 const uint32_t inW = tilingData_->inShape[dimNum_ - 1];
413 const uint32_t globalHStart = outIndex_[dimNum_ - CONST2];413 const uint32_t globalHStart = outIndex_[dimNum_ - CONST2];
414- __local_mem__ PromoteDataT* tmpAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(tmpLocal.GetPhyAddr());414+ __ubuf__ PromoteDataT* tmpAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpLocal.GetPhyAddr());
415 415 
416 for (uint32_t h = 0; h < dimHNum; h++) {416 for (uint32_t h = 0; h < dimHNum; h++) {
417 uint32_t globalH = globalHStart + h;417 uint32_t globalH = globalHStart + h;
418- __local_mem__ PromoteDataT* lineAddr = tmpAddr + h * padWI;418+ __ubuf__ PromoteDataT* lineAddr = tmpAddr + h * padWI;
419 419 
420 // 1. 纯 H 镜像420 // 1. 纯 H 镜像
421 if (has2DPadding) {421 if (has2DPadding) {
@@ -440,7 +440,7 @@ private:
440 }440 }
441 441 
442 // 副pad: C×H 组合 — 对每个 mirrorC 位置，处理 H 镜像442 // 副pad: C×H 组合 — 对每个 mirrorC 位置，处理 H 镜像
443- __aicore__ inline void ProcessCxHSubPad(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t inW)443+ __aicore__ inline void ProcessCxHSubPad(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t inW)
444 {444 {
445 const uint32_t globalC = outIndex_[dimNum_ - CONST3];445 const uint32_t globalC = outIndex_[dimNum_ - CONST3];
446 MirrorList cList = CollectMirrorPositions(globalC, tilingData_->outShape[dimNum_ - CONST3],446 MirrorList cList = CollectMirrorPositions(globalC, tilingData_->outShape[dimNum_ - CONST3],
@@ -453,7 +453,7 @@ private:
453 }453 }
454 454 
455 // 副pad: N×H 相关组合 — 对每个 mirrorN 位置，处理 N×H 和 N×C×H455 // 副pad: N×H 相关组合 — 对每个 mirrorN 位置，处理 N×H 和 N×C×H
456- __aicore__ inline void ProcessNxHSubPad(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t inW)456+ __aicore__ inline void ProcessNxHSubPad(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t inW)
457 {457 {
458 const uint32_t globalN = outIndex_[dimNum_ - CONST4];458 const uint32_t globalN = outIndex_[dimNum_ - CONST4];
459 MirrorList nList = CollectMirrorPositions(globalN, tilingData_->outShape[dimNum_ - CONST4],459 MirrorList nList = CollectMirrorPositions(globalN, tilingData_->outShape[dimNum_ - CONST4],
@@ -471,7 +471,7 @@ private:
471 }471 }
472 472 
473 // 副pad: N×C×H 组合 — 对给定 mirrorN，检查 C 镜像条件，处理 N×C×H473 // 副pad: N×C×H 组合 — 对给定 mirrorN，检查 C 镜像条件，处理 N×C×H
474- __aicore__ inline void ProcessNxCxHSubPad(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t mirrorN,474+ __aicore__ inline void ProcessNxCxHSubPad(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t mirrorN,
475 uint32_t inW)475 uint32_t inW)
476 {476 {
477 const uint32_t globalC = outIndex_[dimNum_ - CONST3];477 const uint32_t globalC = outIndex_[dimNum_ - CONST3];
@@ -485,7 +485,7 @@ private:
485 }485 }
486 486 
487 // 副pad: D5×H 相关组合 — 对每个 mirrorD5，处理 D5×H, D5×C×H, D5×N×H, D5×N×C×H487 // 副pad: D5×H 相关组合 — 对每个 mirrorD5，处理 D5×H, D5×C×H, D5×N×H, D5×N×C×H
488- __aicore__ inline void ProcessD5xHSubPad(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t inW)488+ __aicore__ inline void ProcessD5xHSubPad(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t inW)
489 {489 {
490 const uint32_t globalD5 = outIndex_[dimNum_ - CONST5];490 const uint32_t globalD5 = outIndex_[dimNum_ - CONST5];
491 MirrorList d5List = CollectMirrorPositions(globalD5, tilingData_->outShape[dimNum_ - CONST5],491 MirrorList d5List = CollectMirrorPositions(globalD5, tilingData_->outShape[dimNum_ - CONST5],
@@ -507,7 +507,7 @@ private:
507 }507 }
508 508 
509 // D5×H 组合镜像: 给定 mirrorD5，检查 H 镜像条件509 // D5×H 组合镜像: 给定 mirrorD5，检查 H 镜像条件
510- __aicore__ inline void ProcessD5xHCombinedMirror(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH,510+ __aicore__ inline void ProcessD5xHCombinedMirror(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH,
511 uint32_t mirrorD5, uint32_t inW)511 uint32_t mirrorD5, uint32_t inW)
512 {512 {
513 if (!has2DPadding) {513 if (!has2DPadding) {
@@ -532,8 +532,8 @@ private:
532 }532 }
533 533 
534 // D5×C×H 副pad: 给定 mirrorD5，检查 C 镜像条件，对每个 mirrorC 处理 H 镜像534 // D5×C×H 副pad: 给定 mirrorD5，检查 C 镜像条件，对每个 mirrorC 处理 H 镜像
535- __aicore__ inline void ProcessD5xCxHSubPad(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH,535+ __aicore__ inline void ProcessD5xCxHSubPad(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t mirrorD5,
536- uint32_t mirrorD5, uint32_t inW)536+ uint32_t inW)
537 {537 {
538 const uint32_t globalC = outIndex_[dimNum_ - CONST3];538 const uint32_t globalC = outIndex_[dimNum_ - CONST3];
539 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];539 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];
@@ -558,8 +558,8 @@ private:
558 }558 }
559 559 
560 // D5×N×H 副pad (含 D5×N×C×H): 给定 mirrorD5，检查 N 镜像条件560 // D5×N×H 副pad (含 D5×N×C×H): 给定 mirrorD5，检查 N 镜像条件
561- __aicore__ inline void ProcessD5xNxHSubPad(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH,561+ __aicore__ inline void ProcessD5xNxHSubPad(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t mirrorD5,
562- uint32_t mirrorD5, uint32_t inW)562+ uint32_t inW)
563 {563 {
564 const uint32_t globalN = outIndex_[dimNum_ - CONST4];564 const uint32_t globalN = outIndex_[dimNum_ - CONST4];
565 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];565 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];
@@ -589,8 +589,8 @@ private:
589 }589 }
590 590 
591 // D5×N×C×H 副pad: 给定 mirrorD5 和 mirrorN，检查 C 和 H 镜像条件591 // D5×N×C×H 副pad: 给定 mirrorD5 和 mirrorN，检查 C 和 H 镜像条件
592- __aicore__ inline void ProcessD5xNxCxHSubPad(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH,592+ __aicore__ inline void ProcessD5xNxCxHSubPad(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t mirrorD5,
593- uint32_t mirrorD5, uint32_t mirrorN, uint32_t inW)593+ uint32_t mirrorN, uint32_t inW)
594 {594 {
595 const uint32_t globalC = outIndex_[dimNum_ - CONST3];595 const uint32_t globalC = outIndex_[dimNum_ - CONST3];
596 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];596 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];
@@ -615,7 +615,7 @@ private:
615 }615 }
616 616 
617 // H 维度镜像处理 (高维索引不变，只改变 H 索引)617 // H 维度镜像处理 (高维索引不变，只改变 H 索引)
618- __aicore__ inline void ProcessHDimMirrorAtCurrentHighDim(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH,618+ __aicore__ inline void ProcessHDimMirrorAtCurrentHighDim(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH,
619 uint32_t inW)619 uint32_t inW)
620 {620 {
621 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];621 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];
@@ -642,7 +642,7 @@ private:
642 }642 }
643 643 
644 // C 维度镜像处理644 // C 维度镜像处理
645- __aicore__ inline void ProcessCDimMirror(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t inW)645+ __aicore__ inline void ProcessCDimMirror(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t inW)
646 {646 {
647 const uint32_t globalC = outIndex_[dimNum_ - CONST3];647 const uint32_t globalC = outIndex_[dimNum_ - CONST3];
648 const uint32_t outC = tilingData_->outShape[dimNum_ - CONST3];648 const uint32_t outC = tilingData_->outShape[dimNum_ - CONST3];
@@ -682,8 +682,8 @@ private:
682 }682 }
683 683 
684 // C×H 组合镜像处理684 // C×H 组合镜像处理
685- __aicore__ inline void ProcessCxHCombinedMirror(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH,685+ __aicore__ inline void ProcessCxHCombinedMirror(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t mirrorC,
686- uint32_t mirrorC, uint32_t inW)686+ uint32_t inW)
687 {687 {
688 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];688 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];
689 const uint32_t leftPadH = tilingData_->leftPad[dimNum_ - CONST2];689 const uint32_t leftPadH = tilingData_->leftPad[dimNum_ - CONST2];
@@ -712,8 +712,8 @@ private:
712 }712 }
713 713 
714 // N×H 组合镜像714 // N×H 组合镜像
715- __aicore__ inline void ProcessNxHCombinedMirror(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH,715+ __aicore__ inline void ProcessNxHCombinedMirror(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t mirrorN,
716- uint32_t mirrorN, uint32_t inW)716+ uint32_t inW)
717 {717 {
718 if (!has2DPadding)718 if (!has2DPadding)
719 return;719 return;
@@ -743,8 +743,8 @@ private:
743 }743 }
744 744 
745 // N×C 组合镜像 (包含 N×C×H)745 // N×C 组合镜像 (包含 N×C×H)
746- __aicore__ inline void ProcessNxCCombinedMirror(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH,746+ __aicore__ inline void ProcessNxCCombinedMirror(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t mirrorN,
747- uint32_t mirrorN, uint32_t inW)747+ uint32_t inW)
748 {748 {
749 const uint32_t globalC = outIndex_[dimNum_ - CONST3];749 const uint32_t globalC = outIndex_[dimNum_ - CONST3];
750 const uint32_t outC = tilingData_->outShape[dimNum_ - CONST3];750 const uint32_t outC = tilingData_->outShape[dimNum_ - CONST3];
@@ -782,7 +782,7 @@ private:
782 }782 }
783 783 
784 // N×C×H 组合镜像784 // N×C×H 组合镜像
785- __aicore__ inline void ProcessNxCxHCombinedMirror(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH,785+ __aicore__ inline void ProcessNxCxHCombinedMirror(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH,
786 uint32_t mirrorN, uint32_t mirrorC, uint32_t inW)786 uint32_t mirrorN, uint32_t mirrorC, uint32_t inW)
787 {787 {
788 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];788 const uint32_t outH = tilingData_->outShape[dimNum_ - CONST2];
@@ -810,7 +810,7 @@ private:
810 }810 }
811 811 
812 // 第5维镜像处理 (简化版，只处理单维度镜像)812 // 第5维镜像处理 (简化版，只处理单维度镜像)
813- __aicore__ inline void ProcessDim5Mirror(__local_mem__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t inW)813+ __aicore__ inline void ProcessDim5Mirror(__ubuf__ PromoteDataT* lineAddr, uint32_t globalH, uint32_t inW)
814 {814 {
815 const uint32_t globalD5 = outIndex_[dimNum_ - CONST5];815 const uint32_t globalD5 = outIndex_[dimNum_ - CONST5];
816 const uint32_t outD5 = tilingData_->outShape[dimNum_ - CONST5];816 const uint32_t outD5 = tilingData_->outShape[dimNum_ - CONST5];
@@ -841,8 +841,7 @@ private:
841 841 
842 // 从 GM 拷贝镜像行到 srcLocal (inQueue_)，然后整行累加到目标行842 // 从 GM 拷贝镜像行到 srcLocal (inQueue_)，然后整行累加到目标行
843 // 使用当前高维索引 (inIndex_)，只改变 H 索引843 // 使用当前高维索引 (inIndex_)，只改变 H 索引
844- __aicore__ inline void CopyAndAddMirrorLineFromGM(__local_mem__ PromoteDataT* dstLineAddr, uint32_t hIdx,844+ __aicore__ inline void CopyAndAddMirrorLineFromGM(__ubuf__ PromoteDataT* dstLineAddr, uint32_t hIdx, uint32_t inW)
845- uint32_t inW)
846 {845 {
847 // 计算 GM 地址：使用当前高维索引，只改变 H846 // 计算 GM 地址：使用当前高维索引，只改变 H
848 uint64_t mirrorAddr = 0;847 uint64_t mirrorAddr = 0;
@@ -855,7 +854,7 @@ private:
855 }854 }
856 855 
857 // 从 GM 拷贝镜像行，指定 C 索引856 // 从 GM 拷贝镜像行，指定 C 索引
858- __aicore__ inline void CopyAndAddMirrorLineFromGMWithC(__local_mem__ PromoteDataT* dstLineAddr, uint32_t cIdx,857+ __aicore__ inline void CopyAndAddMirrorLineFromGMWithC(__ubuf__ PromoteDataT* dstLineAddr, uint32_t cIdx,
859 uint32_t hIdx, uint32_t inW)858 uint32_t hIdx, uint32_t inW)
860 {859 {
861 uint64_t mirrorAddr = 0;860 uint64_t mirrorAddr = 0;
@@ -872,7 +871,7 @@ private:
872 }871 }
873 872 
874 // 从 GM 拷贝镜像行，指定 N 和 C 索引873 // 从 GM 拷贝镜像行，指定 N 和 C 索引
875- __aicore__ inline void CopyAndAddMirrorLineFromGMWithNC(__local_mem__ PromoteDataT* dstLineAddr, uint32_t nIdx,874+ __aicore__ inline void CopyAndAddMirrorLineFromGMWithNC(__ubuf__ PromoteDataT* dstLineAddr, uint32_t nIdx,
876 uint32_t cIdx, uint32_t hIdx, uint32_t inW)875 uint32_t cIdx, uint32_t hIdx, uint32_t inW)
877 {876 {
878 uint64_t mirrorAddr = 0;877 uint64_t mirrorAddr = 0;
@@ -891,7 +890,7 @@ private:
891 }890 }
892 891 
893 // 从 GM 拷贝镜像行，指定第5维、N 和 C 索引892 // 从 GM 拷贝镜像行，指定第5维、N 和 C 索引
894- __aicore__ inline void CopyAndAddMirrorLineFromGMWithD5NC(__local_mem__ PromoteDataT* dstLineAddr, uint32_t d5Idx,893+ __aicore__ inline void CopyAndAddMirrorLineFromGMWithD5NC(__ubuf__ PromoteDataT* dstLineAddr, uint32_t d5Idx,
895 uint32_t nIdx, uint32_t cIdx, uint32_t hIdx, uint32_t inW)894 uint32_t nIdx, uint32_t cIdx, uint32_t hIdx, uint32_t inW)
896 {895 {
897 uint64_t mirrorAddr = 0;896 uint64_t mirrorAddr = 0;
@@ -908,8 +907,8 @@ private:
908 }907 }
909 908 
910 // tmpLocal 内两行 PromoteDataT (float32) 相加: dstLine[i] += srcLine[i]909 // tmpLocal 内两行 PromoteDataT (float32) 相加: dstLine[i] += srcLine[i]
911- __aicore__ inline void AddLocalLineInTmpBuf(__local_mem__ PromoteDataT* dstLineAddr,910+ __aicore__ inline void AddLocalLineInTmpBuf(__ubuf__ PromoteDataT* dstLineAddr, __ubuf__ PromoteDataT* srcLineAddr,
912- __local_mem__ PromoteDataT* srcLineAddr, uint32_t inW)911+ uint32_t inW)
913 {912 {
914 constexpr uint32_t VL_ELEMS_FLOAT = VL_SIZE / sizeof(PromoteDataT);913 constexpr uint32_t VL_ELEMS_FLOAT = VL_SIZE / sizeof(PromoteDataT);
915 constexpr uint32_t BL_ELEMS_FLOAT = UB_BLOCK / sizeof(T);914 constexpr uint32_t BL_ELEMS_FLOAT = UB_BLOCK / sizeof(T);
@@ -925,17 +924,17 @@ private:
925 924 
926 for (uint16_t i = 0; i < loopCount; i++) {925 for (uint16_t i = 0; i < loopCount; i++) {
927 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);926 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);
928- AscendC::Reg::DataCopy(dstReg, dstLineAddr + i * VL_ELEMS_FLOAT);927+ AscendC::Reg::LoadAlign(dstReg, dstLineAddr + i * VL_ELEMS_FLOAT);
929- AscendC::Reg::DataCopy(srcReg, srcLineAddr + i * VL_ELEMS_FLOAT);928+ AscendC::Reg::LoadAlign(srcReg, srcLineAddr + i * VL_ELEMS_FLOAT);
930 AscendC::Reg::Add(dstReg, dstReg, srcReg, mask);929 AscendC::Reg::Add(dstReg, dstReg, srcReg, mask);
931- AscendC::Reg::DataCopy(dstLineAddr + i * VL_ELEMS_FLOAT, dstReg, mask);930+ AscendC::Reg::StoreAlign(dstLineAddr + i * VL_ELEMS_FLOAT, dstReg, mask);
932 }931 }
933 }932 }
934 }933 }
935 // tmpLocal 内两行 PromoteDataT (float32) 相加: dstLine[i] = dstLine[i] + srcLine[i] + srcLine[j]934 // tmpLocal 内两行 PromoteDataT (float32) 相加: dstLine[i] = dstLine[i] + srcLine[i] + srcLine[j]
936- __aicore__ inline void AddLocalUpAndDownLineInTmpBuf(__local_mem__ PromoteDataT* dstLineAddr,935+ __aicore__ inline void AddLocalUpAndDownLineInTmpBuf(__ubuf__ PromoteDataT* dstLineAddr,
937- __local_mem__ PromoteDataT* srcUpLineAddr,936+ __ubuf__ PromoteDataT* srcUpLineAddr,
938- __local_mem__ PromoteDataT* srcDownLineAddr, uint32_t inW)937+ __ubuf__ PromoteDataT* srcDownLineAddr, uint32_t inW)
939 {938 {
940 constexpr uint32_t VL_ELEMS_FLOAT = VL_SIZE / sizeof(PromoteDataT);939 constexpr uint32_t VL_ELEMS_FLOAT = VL_SIZE / sizeof(PromoteDataT);
941 constexpr uint32_t BL_ELEMS_FLOAT = UB_BLOCK / sizeof(T);940 constexpr uint32_t BL_ELEMS_FLOAT = UB_BLOCK / sizeof(T);
@@ -952,12 +951,12 @@ private:
952 951 
953 for (uint16_t i = 0; i < loopCount; i++) {952 for (uint16_t i = 0; i < loopCount; i++) {
954 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);953 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);
955- AscendC::Reg::DataCopy(dstReg, dstLineAddr + i * VL_ELEMS_FLOAT);954+ AscendC::Reg::LoadAlign(dstReg, dstLineAddr + i * VL_ELEMS_FLOAT);
956- AscendC::Reg::DataCopy(srcUpReg, srcUpLineAddr + i * VL_ELEMS_FLOAT);955+ AscendC::Reg::LoadAlign(srcUpReg, srcUpLineAddr + i * VL_ELEMS_FLOAT);
957- AscendC::Reg::DataCopy(srcDownReg, srcDownLineAddr + i * VL_ELEMS_FLOAT);956+ AscendC::Reg::LoadAlign(srcDownReg, srcDownLineAddr + i * VL_ELEMS_FLOAT);
958 AscendC::Reg::Add(dstReg, dstReg, srcUpReg, mask);957 AscendC::Reg::Add(dstReg, dstReg, srcUpReg, mask);
959 AscendC::Reg::Add(dstReg, dstReg, srcDownReg, mask);958 AscendC::Reg::Add(dstReg, dstReg, srcDownReg, mask);
960- AscendC::Reg::DataCopy(dstLineAddr + i * VL_ELEMS_FLOAT, dstReg, mask);959+ AscendC::Reg::StoreAlign(dstLineAddr + i * VL_ELEMS_FLOAT, dstReg, mask);
961 }960 }
962 }961 }
963 }962 }
@@ -978,11 +977,10 @@ private:
978 return;977 return;
979 }978 }
980 979 
981- __local_mem__ PromoteDataT* tmpAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(tmpLocal.GetPhyAddr()) +980+ __ubuf__ PromoteDataT* tmpAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpLocal.GetPhyAddr()) + cOffset;
982- cOffset;
983 981 
984 for (uint32_t h = 0; h < outH; h++) {982 for (uint32_t h = 0; h < outH; h++) {
985- __local_mem__ PromoteDataT* selfAddr = tmpAddr + (h + leftPadH) * padWI;983+ __ubuf__ PromoteDataT* selfAddr = tmpAddr + (h + leftPadH) * padWI;
986 bool hasTopMirror = (modeOffset_ == 0) ? (h > 0 && h <= leftPadH) : (h < leftPadH);984 bool hasTopMirror = (modeOffset_ == 0) ? (h > 0 && h <= leftPadH) : (h < leftPadH);
987 bool hasBottomMirror = (modeOffset_ == 0) ? (rightPadH > 0 && h >= outH - rightPadH - 1 && h <= outH - 2) :985 bool hasBottomMirror = (modeOffset_ == 0) ? (rightPadH > 0 && h >= outH - rightPadH - 1 && h <= outH - 2) :
988 (rightPadH > 0 && h >= outH - rightPadH);986 (rightPadH > 0 && h >= outH - rightPadH);
@@ -1022,10 +1020,10 @@ private:
1022 return;1020 return;
1023 }1021 }
1024 1022 
1025- __local_mem__ PromoteDataT* tmpAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(tmpLocal.GetPhyAddr());1023+ __ubuf__ PromoteDataT* tmpAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpLocal.GetPhyAddr());
1026 1024 
1027 for (uint32_t c = 0; c < outC; c++) {1025 for (uint32_t c = 0; c < outC; c++) {
1028- __local_mem__ PromoteDataT* selfAddr = tmpAddr + (c + leftPadC) * cSliceSize;1026+ __ubuf__ PromoteDataT* selfAddr = tmpAddr + (c + leftPadC) * cSliceSize;
1029 1027 
1030 bool hasTopMirror = (modeOffset_ == 0) ? (c > 0 && c <= leftPadC) : (c < leftPadC);1028 bool hasTopMirror = (modeOffset_ == 0) ? (c > 0 && c <= leftPadC) : (c < leftPadC);
1031 bool hasBottomMirror = (modeOffset_ == 0) ? (rightPadC > 0 && c >= outC - rightPadC - 1 && c <= outC - 2) :1029 bool hasBottomMirror = (modeOffset_ == 0) ? (rightPadC > 0 && c >= outC - rightPadC - 1 && c <= outC - 2) :
@@ -1578,8 +1576,7 @@ private:
1578 }1576 }
1579 1577 
1580 // 通用的从 GM 地址拷贝并累加一行数据1578 // 通用的从 GM 地址拷贝并累加一行数据
1581- __aicore__ inline void CopyAndAddLineFromGMAddr(__local_mem__ PromoteDataT* dstLineAddr, uint64_t gmAddr,1579+ __aicore__ inline void CopyAndAddLineFromGMAddr(__ubuf__ PromoteDataT* dstLineAddr, uint64_t gmAddr, uint32_t inW)
1582- uint32_t inW)
1583 {1580 {
1584 // Step 1: 从 GM 拷贝镜像行到 srcLocal1581 // Step 1: 从 GM 拷贝镜像行到 srcLocal
1585 LocalTensor<T> inUbLocal = inQueue_.AllocTensor<T>();1582 LocalTensor<T> inUbLocal = inQueue_.AllocTensor<T>();
@@ -1596,7 +1593,7 @@ private:
1596 // Step 2: 使用 VF 指令进行 Cast 和累加1593 // Step 2: 使用 VF 指令进行 Cast 和累加
1597 LocalTensor<T> inUbLocal2 = inQueue_.DeQue<T>();1594 LocalTensor<T> inUbLocal2 = inQueue_.DeQue<T>();
1598 constexpr uint32_t VL_ELEMS_FLOAT = VL_SIZE / sizeof(PromoteDataT);1595 constexpr uint32_t VL_ELEMS_FLOAT = VL_SIZE / sizeof(PromoteDataT);
1599- __local_mem__ T* srcAddr = reinterpret_cast<__local_mem__ T*>(inUbLocal2.GetPhyAddr());1596+ __ubuf__ T* srcAddr = reinterpret_cast<__ubuf__ T*>(inUbLocal2.GetPhyAddr());
1600 uint16_t loopCount = CeilDiv(inWAlign, VL_ELEMS_FLOAT);1597 uint16_t loopCount = CeilDiv(inWAlign, VL_ELEMS_FLOAT);
1601 1598 
1602 if constexpr (IsSameType<T, PromoteDataT>::value) {1599 if constexpr (IsSameType<T, PromoteDataT>::value) {
@@ -1610,10 +1607,10 @@ private:
1610 1607 
1611 for (uint16_t i = 0; i < loopCount; i++) {1608 for (uint16_t i = 0; i < loopCount; i++) {
1612 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);1609 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);
1613- AscendC::Reg::DataCopy(dstReg, dstLineAddr + i * VL_ELEMS_FLOAT);1610+ AscendC::Reg::LoadAlign(dstReg, dstLineAddr + i * VL_ELEMS_FLOAT);
1614- AscendC::Reg::DataCopy(srcReg, srcAddr + i * VL_ELEMS_FLOAT);1611+ AscendC::Reg::LoadAlign(srcReg, srcAddr + i * VL_ELEMS_FLOAT);
1615 AscendC::Reg::Add(dstReg, dstReg, srcReg, mask);1612 AscendC::Reg::Add(dstReg, dstReg, srcReg, mask);
1616- AscendC::Reg::DataCopy(dstLineAddr + i * VL_ELEMS_FLOAT, dstReg, mask);1613+ AscendC::Reg::StoreAlign(dstLineAddr + i * VL_ELEMS_FLOAT, dstReg, mask);
1617 }1614 }
1618 }1615 }
1619 } else {1616 } else {
@@ -1629,14 +1626,14 @@ private:
1629 for (uint16_t i = 0; i < loopCount; i++) {1626 for (uint16_t i = 0; i < loopCount; i++) {
1630 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);1627 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);
1631 // 使用 DIST_UNPACK_B16 模式读取 B16 类型数据到寄存器1628 // 使用 DIST_UNPACK_B16 模式读取 B16 类型数据到寄存器
1632- AscendC::Reg::DataCopy<T, AscendC::Reg::LoadDist::DIST_UNPACK_B16>(srcReg,1629+ AscendC::Reg::LoadAlign<T, AscendC::Reg::LoadDist::DIST_UNPACK_B16>(srcReg,
1633- srcAddr + i * VL_ELEMS_FLOAT);1630+ srcAddr + i * VL_ELEMS_FLOAT);
1634 // Cast 到 PromoteDataT (float)1631 // Cast 到 PromoteDataT (float)
1635 AscendC::Reg::Cast<PromoteDataT, T, CAST_TRAIT_0>(srcCastReg, srcReg, mask);1632 AscendC::Reg::Cast<PromoteDataT, T, CAST_TRAIT_0>(srcCastReg, srcReg, mask);
1636 // 读取目标数据并累加1633 // 读取目标数据并累加
1637- AscendC::Reg::DataCopy(dstReg, dstLineAddr + i * VL_ELEMS_FLOAT);1634+ AscendC::Reg::LoadAlign(dstReg, dstLineAddr + i * VL_ELEMS_FLOAT);
1638 AscendC::Reg::Add(dstReg, dstReg, srcCastReg, mask);1635 AscendC::Reg::Add(dstReg, dstReg, srcCastReg, mask);
1639- AscendC::Reg::DataCopy(dstLineAddr + i * VL_ELEMS_FLOAT, dstReg, mask);1636+ AscendC::Reg::StoreAlign(dstLineAddr + i * VL_ELEMS_FLOAT, dstReg, mask);
1640 }1637 }
1641 }1638 }
1642 }1639 }
@@ -1650,8 +1647,8 @@ private:
1650 LocalTensor<T> inUbLocal = inQueue_.DeQue<T>();1647 LocalTensor<T> inUbLocal = inQueue_.DeQue<T>();
1651 constexpr uint32_t VL_ELEMS_FLOAT = VL_SIZE / sizeof(PromoteDataT);1648 constexpr uint32_t VL_ELEMS_FLOAT = VL_SIZE / sizeof(PromoteDataT);
1652 uint16_t loopCount = CeilDiv(totalLen, VL_ELEMS_FLOAT);1649 uint16_t loopCount = CeilDiv(totalLen, VL_ELEMS_FLOAT);
1653- __local_mem__ PromoteDataT* tmpAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(tmpLocal.GetPhyAddr());1650+ __ubuf__ PromoteDataT* tmpAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpLocal.GetPhyAddr());
1654- __local_mem__ T* srcAddr = reinterpret_cast<__local_mem__ T*>(inUbLocal.GetPhyAddr());1651+ __ubuf__ T* srcAddr = reinterpret_cast<__ubuf__ T*>(inUbLocal.GetPhyAddr());
1655 1652 
1656 if constexpr (IsSameType<T, PromoteDataT>::value) {1653 if constexpr (IsSameType<T, PromoteDataT>::value) {
1657 __VEC_SCOPE__1654 __VEC_SCOPE__
@@ -1662,10 +1659,10 @@ private:
1662 AscendC::Reg::RegTensor<PromoteDataT> srcReg;1659 AscendC::Reg::RegTensor<PromoteDataT> srcReg;
1663 for (uint16_t i = 0; i < loopCount; i++) {1660 for (uint16_t i = 0; i < loopCount; i++) {
1664 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);1661 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);
1665- AscendC::Reg::DataCopy(dstReg, tmpAddr + i * VL_ELEMS_FLOAT);1662+ AscendC::Reg::LoadAlign(dstReg, tmpAddr + i * VL_ELEMS_FLOAT);
1666- AscendC::Reg::DataCopy(srcReg, srcAddr + i * VL_ELEMS_FLOAT);1663+ AscendC::Reg::LoadAlign(srcReg, srcAddr + i * VL_ELEMS_FLOAT);
1667 AscendC::Reg::Add(dstReg, dstReg, srcReg, mask);1664 AscendC::Reg::Add(dstReg, dstReg, srcReg, mask);
1668- AscendC::Reg::DataCopy(tmpAddr + i * VL_ELEMS_FLOAT, dstReg, mask);1665+ AscendC::Reg::StoreAlign(tmpAddr + i * VL_ELEMS_FLOAT, dstReg, mask);
1669 }1666 }
1670 }1667 }
1671 } else {1668 } else {
@@ -1678,12 +1675,12 @@ private:
1678 AscendC::Reg::RegTensor<T> srcReg;1675 AscendC::Reg::RegTensor<T> srcReg;
1679 for (uint16_t i = 0; i < loopCount; i++) {1676 for (uint16_t i = 0; i < loopCount; i++) {
1680 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);1677 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);
1681- AscendC::Reg::DataCopy<T, AscendC::Reg::LoadDist::DIST_UNPACK_B16>(srcReg,1678+ AscendC::Reg::LoadAlign<T, AscendC::Reg::LoadDist::DIST_UNPACK_B16>(srcReg,
1682- srcAddr + i * VL_ELEMS_FLOAT);1679+ srcAddr + i * VL_ELEMS_FLOAT);
1683 AscendC::Reg::Cast<PromoteDataT, T, CAST_TRAIT_0>(srcCastReg, srcReg, mask);1680 AscendC::Reg::Cast<PromoteDataT, T, CAST_TRAIT_0>(srcCastReg, srcReg, mask);
1684- AscendC::Reg::DataCopy(dstReg, tmpAddr + i * VL_ELEMS_FLOAT);1681+ AscendC::Reg::LoadAlign(dstReg, tmpAddr + i * VL_ELEMS_FLOAT);
1685 AscendC::Reg::Add(dstReg, dstReg, srcCastReg, mask);1682 AscendC::Reg::Add(dstReg, dstReg, srcCastReg, mask);
1686- AscendC::Reg::DataCopy(tmpAddr + i * VL_ELEMS_FLOAT, dstReg, mask);1683+ AscendC::Reg::StoreAlign(tmpAddr + i * VL_ELEMS_FLOAT, dstReg, mask);
1687 }1684 }
1688 }1685 }
1689 }1686 }
@@ -1833,8 +1830,8 @@ private:
1833 // tmpAddr: PromoteDataT 类型 (float)，包含原始 grad_y 数据 + 高维镜像累加结果1830 // tmpAddr: PromoteDataT 类型 (float)，包含原始 grad_y 数据 + 高维镜像累加结果
1834 // dstAddr: 输出 grad_x (T 类型)1831 // dstAddr: 输出 grad_x (T 类型)
1835 // 使用 VF 指令和 gather 进行向量化处理1832 // 使用 VF 指令和 gather 进行向量化处理
1836- __aicore__ inline void GradProcessLineFromTmpBuf(__local_mem__ T* dstAddr, __local_mem__ PromoteDataT* tmpAddr,1833+ __aicore__ inline void GradProcessLineFromTmpBuf(__ubuf__ T* dstAddr, __ubuf__ PromoteDataT* tmpAddr, uint32_t outW,
1837- uint32_t outW, uint32_t inW, uint32_t leftPad, uint32_t rightPad)1834+ uint32_t inW, uint32_t leftPad, uint32_t rightPad)
1838 {1835 {
1839 constexpr uint32_t VL_ELEMS_FLOAT = VL_SIZE / sizeof(PromoteDataT);1836 constexpr uint32_t VL_ELEMS_FLOAT = VL_SIZE / sizeof(PromoteDataT);
1840 // using IdxType = uint32_t; // float 对应 uint32_t 索引1837 // using IdxType = uint32_t; // float 对应 uint32_t 索引
@@ -1861,10 +1858,10 @@ private:
1861 1858 
1862 uint32_t mainMaskLen = VL_ELEMS_FLOAT;1859 uint32_t mainMaskLen = VL_ELEMS_FLOAT;
1863 uint32_t tailMaskLen = leftTailLen;1860 uint32_t tailMaskLen = leftTailLen;
1864- __local_mem__ PromoteDataT* srcStartAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(1861+ __ubuf__ PromoteDataT* srcStartAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpAddr + leftStart +
1865- tmpAddr + leftStart + leftPad);1862+ leftPad);
1866- __local_mem__ PromoteDataT* dstStartAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(1863+ __ubuf__ PromoteDataT* dstStartAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpAddr + leftStart +
1867- tmpAddr + leftStart + leftPad);1864+ leftPad);
1868 __VEC_SCOPE__1865 __VEC_SCOPE__
1869 {1866 {
1870 AscendC::Reg::RegTensor<PromoteDataT> selfReg;1867 AscendC::Reg::RegTensor<PromoteDataT> selfReg;
@@ -1873,39 +1870,39 @@ private:
1873 AscendC::Reg::RegTensor<uint32_t> idxReg;1870 AscendC::Reg::RegTensor<uint32_t> idxReg;
1874 AscendC::Reg::RegTensor<int32_t> arangeReg;1871 AscendC::Reg::RegTensor<int32_t> arangeReg;
1875 AscendC::Reg::RegTensor<uint32_t> baseIdxReg;1872 AscendC::Reg::RegTensor<uint32_t> baseIdxReg;
1876- AscendC::Reg::UnalignReg uSrc;1873+ AscendC::Reg::UnalignRegForLoad uSrc;
1877- AscendC::Reg::UnalignReg uDst;1874+ AscendC::Reg::UnalignRegForStore uDst;
1878 1875 
1879 AscendC::Reg::MaskReg maskMain = AscendC::Reg::UpdateMask<PromoteDataT>(mainMaskLen);1876 AscendC::Reg::MaskReg maskMain = AscendC::Reg::UpdateMask<PromoteDataT>(mainMaskLen);
1880 AscendC::Reg::MaskReg maskTail = AscendC::Reg::UpdateMask<PromoteDataT>(tailMaskLen);1877 AscendC::Reg::MaskReg maskTail = AscendC::Reg::UpdateMask<PromoteDataT>(tailMaskLen);
1881 1878 
1882 AscendC::Reg::Arange(arangeReg, 0);1879 AscendC::Reg::Arange(arangeReg, 0);
1883 idxReg = reinterpret_cast<AscendC::Reg::RegTensor<uint32_t>&>(arangeReg);1880 idxReg = reinterpret_cast<AscendC::Reg::RegTensor<uint32_t>&>(arangeReg);
1884- AscendC::Reg::DataCopyUnAlignPre(uSrc, srcStartAddr);1881+ AscendC::Reg::LoadUnAlignPre(uSrc, srcStartAddr);
1885 1882 
1886 for (uint16_t i = 0; i < leftMainLoops; i++) {1883 for (uint16_t i = 0; i < leftMainLoops; i++) {
1887 uint32_t curStart = leftStart + i * VL_ELEMS_FLOAT;1884 uint32_t curStart = leftStart + i * VL_ELEMS_FLOAT;
1888- AscendC::Reg::DataCopyUnAlign(selfReg, uSrc, srcStartAddr, VL_ELEMS_FLOAT);1885+ AscendC::Reg::LoadUnAlign(selfReg, uSrc, srcStartAddr, VL_ELEMS_FLOAT);
1889 1886 
1890 uint32_t baseIdx = static_cast<uint32_t>(leftPad - modeOffset_ - curStart);1887 uint32_t baseIdx = static_cast<uint32_t>(leftPad - modeOffset_ - curStart);
1891 AscendC::Reg::Duplicate(baseIdxReg, baseIdx);1888 AscendC::Reg::Duplicate(baseIdxReg, baseIdx);
1892 AscendC::Reg::Sub(baseIdxReg, baseIdxReg, idxReg, maskMain);1889 AscendC::Reg::Sub(baseIdxReg, baseIdxReg, idxReg, maskMain);
1893- AscendC::Reg::DataCopyGather(mirrorReg, tmpAddr, baseIdxReg, maskMain);1890+ AscendC::Reg::Gather(mirrorReg, tmpAddr, baseIdxReg, maskMain);
1894 1891 
1895 AscendC::Reg::Add(resultReg, selfReg, mirrorReg, maskMain);1892 AscendC::Reg::Add(resultReg, selfReg, mirrorReg, maskMain);
1896- AscendC::Reg::DataCopyUnAlign(dstStartAddr, resultReg, uDst, VL_ELEMS_FLOAT);1893+ AscendC::Reg::StoreUnAlign(dstStartAddr, resultReg, uDst, VL_ELEMS_FLOAT);
1897 }1894 }
1898 uint32_t curStart = leftStart + leftMainLoops * VL_ELEMS_FLOAT;1895 uint32_t curStart = leftStart + leftMainLoops * VL_ELEMS_FLOAT;
1899- AscendC::Reg::DataCopyUnAlign(selfReg, uSrc, srcStartAddr, leftTailLen);1896+ AscendC::Reg::LoadUnAlign(selfReg, uSrc, srcStartAddr, leftTailLen);
1900 1897 
1901 uint32_t baseIdx = static_cast<uint32_t>(leftPad - modeOffset_ - curStart);1898 uint32_t baseIdx = static_cast<uint32_t>(leftPad - modeOffset_ - curStart);
1902 AscendC::Reg::Duplicate(baseIdxReg, baseIdx);1899 AscendC::Reg::Duplicate(baseIdxReg, baseIdx);
1903 AscendC::Reg::Sub(baseIdxReg, baseIdxReg, idxReg, maskTail);1900 AscendC::Reg::Sub(baseIdxReg, baseIdxReg, idxReg, maskTail);
1904- AscendC::Reg::DataCopyGather(mirrorReg, tmpAddr, baseIdxReg, maskTail);1901+ AscendC::Reg::Gather(mirrorReg, tmpAddr, baseIdxReg, maskTail);
1905 1902 
1906 AscendC::Reg::Add(resultReg, selfReg, mirrorReg, maskTail);1903 AscendC::Reg::Add(resultReg, selfReg, mirrorReg, maskTail);
1907- AscendC::Reg::DataCopyUnAlign(dstStartAddr, resultReg, uDst, leftTailLen);1904+ AscendC::Reg::StoreUnAlign(dstStartAddr, resultReg, uDst, leftTailLen);
1908- AscendC::Reg::DataCopyUnAlignPost(dstStartAddr, uDst, 0);1905+ AscendC::Reg::StoreUnAlignPost(dstStartAddr, uDst, 0);
1909 }1906 }
1910 }1907 }
1911 1908 
@@ -1917,10 +1914,10 @@ private:
1917 1914 
1918 uint32_t mainMaskLen = VL_ELEMS_FLOAT;1915 uint32_t mainMaskLen = VL_ELEMS_FLOAT;
1919 uint32_t tailMaskLen = rightTailLen;1916 uint32_t tailMaskLen = rightTailLen;
1920- __local_mem__ PromoteDataT* srcStartAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(1917+ __ubuf__ PromoteDataT* srcStartAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpAddr + rightStart +
1921- tmpAddr + rightStart + leftPad);1918+ leftPad);
1922- __local_mem__ PromoteDataT* dstStartAddr = reinterpret_cast<__local_mem__ PromoteDataT*>(1919+ __ubuf__ PromoteDataT* dstStartAddr = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpAddr + rightStart +
1923- tmpAddr + rightStart + leftPad);1920+ leftPad);
1924 __VEC_SCOPE__1921 __VEC_SCOPE__
1925 {1922 {
1926 AscendC::Reg::RegTensor<PromoteDataT> selfReg;1923 AscendC::Reg::RegTensor<PromoteDataT> selfReg;
@@ -1929,47 +1926,47 @@ private:
1929 AscendC::Reg::RegTensor<uint32_t> idxReg;1926 AscendC::Reg::RegTensor<uint32_t> idxReg;
1930 AscendC::Reg::RegTensor<int32_t> arangeReg;1927 AscendC::Reg::RegTensor<int32_t> arangeReg;
1931 AscendC::Reg::RegTensor<uint32_t> baseIdxReg;1928 AscendC::Reg::RegTensor<uint32_t> baseIdxReg;
1932- AscendC::Reg::UnalignReg uSrc;1929+ AscendC::Reg::UnalignRegForLoad uSrc;
1933- AscendC::Reg::UnalignReg uDst;1930+ AscendC::Reg::UnalignRegForStore uDst;
1934 1931 
1935 AscendC::Reg::MaskReg maskMain = AscendC::Reg::UpdateMask<PromoteDataT>(mainMaskLen);1932 AscendC::Reg::MaskReg maskMain = AscendC::Reg::UpdateMask<PromoteDataT>(mainMaskLen);
1936 AscendC::Reg::MaskReg maskTail = AscendC::Reg::UpdateMask<PromoteDataT>(tailMaskLen);1933 AscendC::Reg::MaskReg maskTail = AscendC::Reg::UpdateMask<PromoteDataT>(tailMaskLen);
1937 1934 
1938 AscendC::Reg::Arange(arangeReg, 0);1935 AscendC::Reg::Arange(arangeReg, 0);
1939 idxReg = reinterpret_cast<AscendC::Reg::RegTensor<uint32_t>&>(arangeReg);1936 idxReg = reinterpret_cast<AscendC::Reg::RegTensor<uint32_t>&>(arangeReg);
1940- AscendC::Reg::DataCopyUnAlignPre(uSrc, srcStartAddr);1937+ AscendC::Reg::LoadUnAlignPre(uSrc, srcStartAddr);
1941 1938 
1942 for (uint16_t i = 0; i < rightMainLoops; i++) {1939 for (uint16_t i = 0; i < rightMainLoops; i++) {
1943 uint32_t curStart = rightStart + i * VL_ELEMS_FLOAT;1940 uint32_t curStart = rightStart + i * VL_ELEMS_FLOAT;
1944- AscendC::Reg::DataCopyUnAlign(selfReg, uSrc, srcStartAddr, VL_ELEMS_FLOAT);1941+ AscendC::Reg::LoadUnAlign(selfReg, uSrc, srcStartAddr, VL_ELEMS_FLOAT);
1945 1942 
1946 uint32_t baseIdx = static_cast<uint32_t>(2 * outW + leftPad - 2 + modeOffset_ - curStart);1943 uint32_t baseIdx = static_cast<uint32_t>(2 * outW + leftPad - 2 + modeOffset_ - curStart);
1947 AscendC::Reg::Duplicate(baseIdxReg, baseIdx);1944 AscendC::Reg::Duplicate(baseIdxReg, baseIdx);
1948 AscendC::Reg::Sub(baseIdxReg, baseIdxReg, idxReg, maskMain);1945 AscendC::Reg::Sub(baseIdxReg, baseIdxReg, idxReg, maskMain);
1949- AscendC::Reg::DataCopyGather(mirrorReg, tmpAddr, baseIdxReg, maskMain);1946+ AscendC::Reg::Gather(mirrorReg, tmpAddr, baseIdxReg, maskMain);
1950 1947 
1951 AscendC::Reg::Add(resultReg, selfReg, mirrorReg, maskMain);1948 AscendC::Reg::Add(resultReg, selfReg, mirrorReg, maskMain);
1952- AscendC::Reg::DataCopyUnAlign(dstStartAddr, resultReg, uDst, VL_ELEMS_FLOAT);1949+ AscendC::Reg::StoreUnAlign(dstStartAddr, resultReg, uDst, VL_ELEMS_FLOAT);
1953 }1950 }
1954 uint32_t curStart = rightStart + rightMainLoops * VL_ELEMS_FLOAT;1951 uint32_t curStart = rightStart + rightMainLoops * VL_ELEMS_FLOAT;
1955- AscendC::Reg::DataCopyUnAlign(selfReg, uSrc, srcStartAddr, rightTailLen);1952+ AscendC::Reg::LoadUnAlign(selfReg, uSrc, srcStartAddr, rightTailLen);
1956 1953 
1957 uint32_t baseIdx = static_cast<uint32_t>(2 * outW + leftPad - 2 + modeOffset_ - curStart);1954 uint32_t baseIdx = static_cast<uint32_t>(2 * outW + leftPad - 2 + modeOffset_ - curStart);
1958 AscendC::Reg::Duplicate(baseIdxReg, baseIdx);1955 AscendC::Reg::Duplicate(baseIdxReg, baseIdx);
1959 AscendC::Reg::Sub(baseIdxReg, baseIdxReg, idxReg, maskTail);1956 AscendC::Reg::Sub(baseIdxReg, baseIdxReg, idxReg, maskTail);
1960- AscendC::Reg::DataCopyGather(mirrorReg, tmpAddr, baseIdxReg, maskTail);1957+ AscendC::Reg::Gather(mirrorReg, tmpAddr, baseIdxReg, maskTail);
1961 1958 
1962 AscendC::Reg::Add(resultReg, selfReg, mirrorReg, maskTail);1959 AscendC::Reg::Add(resultReg, selfReg, mirrorReg, maskTail);
1963- AscendC::Reg::DataCopyUnAlign(dstStartAddr, resultReg, uDst, rightTailLen);1960+ AscendC::Reg::StoreUnAlign(dstStartAddr, resultReg, uDst, rightTailLen);
1964- AscendC::Reg::DataCopyUnAlignPost(dstStartAddr, uDst, 0);1961+ AscendC::Reg::StoreUnAlignPost(dstStartAddr, uDst, 0);
1965 }1962 }
1966 }1963 }
1967 1964 
1968 // ========== 阶段2: 从 tmpAddr+leftPad 非对齐读 outW 个元素，对齐搬出到 dstAddr ==========1965 // ========== 阶段2: 从 tmpAddr+leftPad 非对齐读 outW 个元素，对齐搬出到 dstAddr ==========
1969 1966 
1970 uint16_t outLoopCount = CeilDiv(outW, VL_ELEMS_FLOAT);1967 uint16_t outLoopCount = CeilDiv(outW, VL_ELEMS_FLOAT);
1971- __local_mem__ PromoteDataT* srcAddr2 = reinterpret_cast<__local_mem__ PromoteDataT*>(tmpAddr + leftPad);1968+ __ubuf__ PromoteDataT* srcAddr2 = reinterpret_cast<__ubuf__ PromoteDataT*>(tmpAddr + leftPad);
1972- __local_mem__ T* dstAddr2 = reinterpret_cast<__local_mem__ T*>(dstAddr);1969+ __ubuf__ T* dstAddr2 = reinterpret_cast<__ubuf__ T*>(dstAddr);
1973 1970 
1974 if constexpr (IsSameType<T, PromoteDataT>::value) {1971 if constexpr (IsSameType<T, PromoteDataT>::value) {
1975 // float: 非对齐读 → DataCopy 对齐写1972 // float: 非对齐读 → DataCopy 对齐写
@@ -1978,12 +1975,12 @@ private:
1978 uint32_t remainLen = outW;1975 uint32_t remainLen = outW;
1979 AscendC::Reg::MaskReg mask;1976 AscendC::Reg::MaskReg mask;
1980 AscendC::Reg::RegTensor<PromoteDataT> dataReg;1977 AscendC::Reg::RegTensor<PromoteDataT> dataReg;
1981- AscendC::Reg::UnalignReg uSrc;1978+ AscendC::Reg::UnalignRegForLoad uSrc;
1982- AscendC::Reg::DataCopyUnAlignPre(uSrc, srcAddr2);1979+ AscendC::Reg::LoadUnAlignPre(uSrc, srcAddr2);
1983 for (uint16_t i = 0; i < outLoopCount; i++) {1980 for (uint16_t i = 0; i < outLoopCount; i++) {
1984 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);1981 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);
1985- AscendC::Reg::DataCopyUnAlign(dataReg, uSrc, srcAddr2, VL_ELEMS_FLOAT);1982+ AscendC::Reg::LoadUnAlign(dataReg, uSrc, srcAddr2, VL_ELEMS_FLOAT);
1986- AscendC::Reg::DataCopy(dstAddr2 + i * VL_ELEMS_FLOAT, dataReg, mask);1983+ AscendC::Reg::StoreAlign(dstAddr2 + i * VL_ELEMS_FLOAT, dataReg, mask);
1987 }1984 }
1988 }1985 }
1989 } else {1986 } else {
@@ -1994,14 +1991,14 @@ private:
1994 AscendC::Reg::MaskReg mask;1991 AscendC::Reg::MaskReg mask;
1995 AscendC::Reg::RegTensor<PromoteDataT> dataReg;1992 AscendC::Reg::RegTensor<PromoteDataT> dataReg;
1996 AscendC::Reg::RegTensor<T> outReg;1993 AscendC::Reg::RegTensor<T> outReg;
1997- AscendC::Reg::UnalignReg uSrc;1994+ AscendC::Reg::UnalignRegForLoad uSrc;
1998- AscendC::Reg::DataCopyUnAlignPre(uSrc, srcAddr2);1995+ AscendC::Reg::LoadUnAlignPre(uSrc, srcAddr2);
1999 for (uint16_t i = 0; i < outLoopCount; i++) {1996 for (uint16_t i = 0; i < outLoopCount; i++) {
2000 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);1997 mask = AscendC::Reg::UpdateMask<PromoteDataT>(remainLen);
2001- AscendC::Reg::DataCopyUnAlign(dataReg, uSrc, srcAddr2, VL_ELEMS_FLOAT);1998+ AscendC::Reg::LoadUnAlign(dataReg, uSrc, srcAddr2, VL_ELEMS_FLOAT);
2002 AscendC::Reg::Cast<T, PromoteDataT, CAST_TRAIT_1>(outReg, dataReg, mask);1999 AscendC::Reg::Cast<T, PromoteDataT, CAST_TRAIT_1>(outReg, dataReg, mask);
2003- AscendC::Reg::DataCopy<T, AscendC::Reg::StoreDist::DIST_PACK_B32>(dstAddr2 + i * VL_ELEMS_FLOAT,2000+ AscendC::Reg::StoreAlign<T, AscendC::Reg::StoreDist::DIST_PACK_B32>(dstAddr2 + i * VL_ELEMS_FLOAT,
2004- outReg, mask);2001+ outReg, mask);
2005 }2002 }
2006 }2003 }
2007 }2004 }
Mconversion/pad_v3_grad_replication/op_kernel/arch35/pad_v3_grad_replication.h+45-45
@@ -291,24 +291,24 @@ private:
291 maskB16 = Reg::UpdateMask<T>(tail16);291 maskB16 = Reg::UpdateMask<T>(tail16);
292 maskLo = Reg::UpdateMask<PromoteT>(tailLo);292 maskLo = Reg::UpdateMask<PromoteT>(tailLo);
293 maskHi = Reg::UpdateMask<PromoteT>(tailHi);293 maskHi = Reg::UpdateMask<PromoteT>(tailHi);
294- Reg::DataCopy(vregB16, b16Ptr + off);294+ Reg::LoadAlign(vregB16, b16Ptr + off);
295 Reg::Cast<PromoteT, T, CAST_TRAIT_PROMOTE_ZERO>(vregF1, vregB16, maskB16);295 Reg::Cast<PromoteT, T, CAST_TRAIT_PROMOTE_ZERO>(vregF1, vregB16, maskB16);
296 Reg::Cast<PromoteT, T, CAST_TRAIT_PROMOTE_ONE>(vregF2, vregB16, maskB16);296 Reg::Cast<PromoteT, T, CAST_TRAIT_PROMOTE_ONE>(vregF2, vregB16, maskB16);
297 Reg::Interleave(vregF32Lo, vregF32Hi, vregF1, vregF2);297 Reg::Interleave(vregF32Lo, vregF32Hi, vregF1, vregF2);
298- Reg::DataCopy(f32Ptr + off, vregF32Lo, maskLo);298+ Reg::StoreAlign(f32Ptr + off, vregF32Lo, maskLo);
299- Reg::DataCopy(f32Ptr + off + VL_F32, vregF32Hi, maskHi);299+ Reg::StoreAlign(f32Ptr + off + VL_F32, vregF32Hi, maskHi);
300 }300 }
301 // Step 2: non-tail chunks backward (loops-2 ... 0)301 // Step 2: non-tail chunks backward (loops-2 ... 0)
302 maskB16 = Reg::CreateMask<T, Reg::MaskPattern::ALL>();302 maskB16 = Reg::CreateMask<T, Reg::MaskPattern::ALL>();
303 for (uint16_t i = 0; i < nonTailCnt; i++) {303 for (uint16_t i = 0; i < nonTailCnt; i++) {
304 uint32_t off = (uint32_t)(loops - 1 - i - hasTail) * FULL;304 uint32_t off = (uint32_t)(loops - 1 - i - hasTail) * FULL;
305 305 
306- Reg::DataCopy(vregB16, b16Ptr + off);306+ Reg::LoadAlign(vregB16, b16Ptr + off);
307 Reg::Cast<PromoteT, T, CAST_TRAIT_PROMOTE_ZERO>(vregF1, vregB16, maskB16);307 Reg::Cast<PromoteT, T, CAST_TRAIT_PROMOTE_ZERO>(vregF1, vregB16, maskB16);
308 Reg::Cast<PromoteT, T, CAST_TRAIT_PROMOTE_ONE>(vregF2, vregB16, maskB16);308 Reg::Cast<PromoteT, T, CAST_TRAIT_PROMOTE_ONE>(vregF2, vregB16, maskB16);
309 Reg::Interleave(vregF32Lo, vregF32Hi, vregF1, vregF2);309 Reg::Interleave(vregF32Lo, vregF32Hi, vregF1, vregF2);
310- Reg::DataCopy(f32Ptr + off, vregF32Lo, maskB16);310+ Reg::StoreAlign(f32Ptr + off, vregF32Lo, maskB16);
311- Reg::DataCopy(f32Ptr + off + VL_F32, vregF32Hi, maskB16);311+ Reg::StoreAlign(f32Ptr + off + VL_F32, vregF32Hi, maskB16);
312 }312 }
313 }313 }
314 }314 }
@@ -657,7 +657,7 @@ private:
657 if (srcCnt == 0 || sliceElems == 0)657 if (srcCnt == 0 || sliceElems == 0)
658 return;658 return;
659 659 
660- auto baseAddr = reinterpret_cast<__local_mem__ DType*>(data.GetPhyAddr());660+ auto baseAddr = reinterpret_cast<__ubuf__ DType*>(data.GetPhyAddr());
661 constexpr uint32_t VL = VREG_BYTES / sizeof(DType);661 constexpr uint32_t VL = VREG_BYTES / sizeof(DType);
662 const uint16_t loopCount = (uint16_t)CeilDiv((uint32_t)sliceElems, VL);662 const uint16_t loopCount = (uint16_t)CeilDiv((uint32_t)sliceElems, VL);
663 663 
@@ -668,12 +668,12 @@ private:
668 Reg::RegTensor<DType> vregDst, vregSrc;668 Reg::RegTensor<DType> vregDst, vregSrc;
669 for (uint16_t i = 0; i < loopCount; i++) {669 for (uint16_t i = 0; i < loopCount; i++) {
670 mask = Reg::UpdateMask<DType>(remain);670 mask = Reg::UpdateMask<DType>(remain);
671- Reg::DataCopy(vregDst, baseAddr + dstOffsetElems + i * VL);671+ Reg::LoadAlign(vregDst, baseAddr + dstOffsetElems + i * VL);
672 for (uint16_t j = 0; j < (uint16_t)srcCnt; j++) {672 for (uint16_t j = 0; j < (uint16_t)srcCnt; j++) {
673- Reg::DataCopy(vregSrc, baseAddr + srcStartElems + j * srcStrideElems + i * VL);673+ Reg::LoadAlign(vregSrc, baseAddr + srcStartElems + j * srcStrideElems + i * VL);
674 Reg::Add(vregDst, vregDst, vregSrc, mask);674 Reg::Add(vregDst, vregDst, vregSrc, mask);
675 }675 }
676- Reg::DataCopy(baseAddr + dstOffsetElems + i * VL, vregDst, mask);676+ Reg::StoreAlign(baseAddr + dstOffsetElems + i * VL, vregDst, mask);
677 }677 }
678 }678 }
679 }679 }
@@ -834,7 +834,7 @@ private:
834 Reg::Sub<Idx32>(ik, quot, tmpReg, maskF32);834 Reg::Sub<Idx32>(ik, quot, tmpReg, maskF32);
835 Reg::Muls(tmpReg, ik, eS0, maskF32);835 Reg::Muls(tmpReg, ik, eS0, maskF32);
836 Reg::Add<Idx32>(baseIdx, baseIdx, tmpReg, maskF32);836 Reg::Add<Idx32>(baseIdx, baseIdx, tmpReg, maskF32);
837- Reg::Copy(quot, qNext);837+ Reg::Move(quot, qNext);
838 if constexpr (kEffAxes >= 3) {838 if constexpr (kEffAxes >= 3) {
839 Reg::Duplicate(dExt, eE1, maskF32);839 Reg::Duplicate(dExt, eE1, maskF32);
840 Reg::Div<Idx32>(qNext, quot, dExt, maskF32);840 Reg::Div<Idx32>(qNext, quot, dExt, maskF32);
@@ -842,7 +842,7 @@ private:
842 Reg::Sub<Idx32>(ik, quot, tmpReg, maskF32);842 Reg::Sub<Idx32>(ik, quot, tmpReg, maskF32);
843 Reg::Muls(tmpReg, ik, eS1, maskF32);843 Reg::Muls(tmpReg, ik, eS1, maskF32);
844 Reg::Add<Idx32>(baseIdx, baseIdx, tmpReg, maskF32);844 Reg::Add<Idx32>(baseIdx, baseIdx, tmpReg, maskF32);
845- Reg::Copy(quot, qNext);845+ Reg::Move(quot, qNext);
846 if constexpr (kEffAxes >= 4) {846 if constexpr (kEffAxes >= 4) {
847 Reg::Duplicate(dExt, eE2, maskF32);847 Reg::Duplicate(dExt, eE2, maskF32);
848 Reg::Div<Idx32>(qNext, quot, dExt, maskF32);848 Reg::Div<Idx32>(qNext, quot, dExt, maskF32);
@@ -850,7 +850,7 @@ private:
850 Reg::Sub<Idx32>(ik, quot, tmpReg, maskF32);850 Reg::Sub<Idx32>(ik, quot, tmpReg, maskF32);
851 Reg::Muls(tmpReg, ik, eS2, maskF32);851 Reg::Muls(tmpReg, ik, eS2, maskF32);
852 Reg::Add<Idx32>(baseIdx, baseIdx, tmpReg, maskF32);852 Reg::Add<Idx32>(baseIdx, baseIdx, tmpReg, maskF32);
853- Reg::Copy(quot, qNext);853+ Reg::Move(quot, qNext);
854 if constexpr (kEffAxes >= 5) {854 if constexpr (kEffAxes >= 5) {
855 Reg::Duplicate(dExt, eE3, maskF32);855 Reg::Duplicate(dExt, eE3, maskF32);
856 Reg::Div<Idx32>(qNext, quot, dExt, maskF32);856 Reg::Div<Idx32>(qNext, quot, dExt, maskF32);
@@ -858,7 +858,7 @@ private:
858 Reg::Sub<Idx32>(ik, quot, tmpReg, maskF32);858 Reg::Sub<Idx32>(ik, quot, tmpReg, maskF32);
859 Reg::Muls(tmpReg, ik, eS3, maskF32);859 Reg::Muls(tmpReg, ik, eS3, maskF32);
860 Reg::Add<Idx32>(baseIdx, baseIdx, tmpReg, maskF32);860 Reg::Add<Idx32>(baseIdx, baseIdx, tmpReg, maskF32);
861- Reg::Copy(quot, qNext);861+ Reg::Move(quot, qNext);
862 Reg::Muls(tmpReg, quot, eS4, maskF32);862 Reg::Muls(tmpReg, quot, eS4, maskF32);
863 Reg::Add<Idx32>(baseIdx, baseIdx, tmpReg, maskF32);863 Reg::Add<Idx32>(baseIdx, baseIdx, tmpReg, maskF32);
864 } else {864 } else {
@@ -880,10 +880,10 @@ private:
880 880 
881 // ======== Phase A: 左边界 ========881 // ======== Phase A: 左边界 ========
882 Reg::Adds(idxF32, baseIdx, (Idx32)pL, maskF32);882 Reg::Adds(idxF32, baseIdx, (Idx32)pL, maskF32);
883- Reg::DataCopyGather(vregF32, dataAddr, idxF32, maskF32);883+ Reg::Gather(vregF32, dataAddr, idxF32, maskF32);
884 for (uint16_t k = 0; k < phaseA_pLu; k++) {884 for (uint16_t k = 0; k < phaseA_pLu; k++) {
885 Reg::Adds(idxF32, baseIdx, (Idx32)k, maskF32);885 Reg::Adds(idxF32, baseIdx, (Idx32)k, maskF32);
886- Reg::DataCopyGather(vregPadF32, dataAddr, idxF32, maskF32);886+ Reg::Gather(vregPadF32, dataAddr, idxF32, maskF32);
887 Reg::Add(vregF32, vregF32, vregPadF32, maskF32);887 Reg::Add(vregF32, vregF32, vregPadF32, maskF32);
888 }888 }
889 // F32→B16 cast + Select889 // F32→B16 cast + Select
@@ -897,13 +897,13 @@ private:
897 (Reg::RegTensor<Idx16>&)tmpHalf, maskB16);897 (Reg::RegTensor<Idx16>&)tmpHalf, maskB16);
898 Reg::Muls(idxB16, (Reg::RegTensor<Idx16>&)tmpRange16, (Idx16)dN1, maskB16);898 Reg::Muls(idxB16, (Reg::RegTensor<Idx16>&)tmpRange16, (Idx16)dN1, maskB16);
899 Reg::Adds(idxB16, idxB16, (Idx16)((Rng16)b * (Rng16)VL_F32 * (Rng16)dN1), maskB16);899 Reg::Adds(idxB16, idxB16, (Idx16)((Rng16)b * (Rng16)VL_F32 * (Rng16)dN1), maskB16);
900- Reg::DataCopyScatter(outputAddr, vregScatter, idxB16, maskB16);900+ Reg::Scatter(outputAddr, vregScatter, idxB16, maskB16);
901 901 
902 // ======== Phase B: 中间 ========902 // ======== Phase B: 中间 ========
903 for (uint16_t i = 0; i < midCount; i++) {903 for (uint16_t i = 0; i < midCount; i++) {
904 const uint16_t iN1 = i + 1;904 const uint16_t iN1 = i + 1;
905 Reg::Adds(idxF32, baseIdx, (Idx32)((Rng32)iN1 + (Rng32)pL), maskF32);905 Reg::Adds(idxF32, baseIdx, (Idx32)((Rng32)iN1 + (Rng32)pL), maskF32);
906- Reg::DataCopyGather(vregF32, dataAddr, idxF32, maskF32);906+ Reg::Gather(vregF32, dataAddr, idxF32, maskF32);
907 Reg::Cast<T, PromoteT, CAST_TRAIT_DOWN_ZERO>(vregB16Lo, vregF32, maskB16);907 Reg::Cast<T, PromoteT, CAST_TRAIT_DOWN_ZERO>(vregB16Lo, vregF32, maskB16);
908 Reg::Cast<T, PromoteT, CAST_TRAIT_DOWN_ONE>(vregB16Hi, vregF32, maskB16);908 Reg::Cast<T, PromoteT, CAST_TRAIT_DOWN_ONE>(vregB16Hi, vregF32, maskB16);
909 Reg::Select(vregScatter, vregB16Lo, vregB16Hi, selMaskLo);909 Reg::Select(vregScatter, vregB16Lo, vregB16Hi, selMaskLo);
@@ -913,20 +913,20 @@ private:
913 (Reg::RegTensor<Idx16>&)tmpHalf, maskB16);913 (Reg::RegTensor<Idx16>&)tmpHalf, maskB16);
914 Reg::Muls(idxB16, (Reg::RegTensor<Idx16>&)tmpRange16, (Idx16)dN1, maskB16);914 Reg::Muls(idxB16, (Reg::RegTensor<Idx16>&)tmpRange16, (Idx16)dN1, maskB16);
915 Reg::Adds(idxB16, idxB16, (Idx16)((Rng16)b * (Rng16)VL_F32 * (Rng16)dN1 + (Rng16)iN1), maskB16);915 Reg::Adds(idxB16, idxB16, (Idx16)((Rng16)b * (Rng16)VL_F32 * (Rng16)dN1 + (Rng16)iN1), maskB16);
916- Reg::DataCopyScatter(outputAddr, vregScatter, idxB16, maskB16);916+ Reg::Scatter(outputAddr, vregScatter, idxB16, maskB16);
917 }917 }
918 918 
919 // ======== Phase C: 右边界 ========919 // ======== Phase C: 右边界 ========
920 Reg::Adds(idxF32, baseIdx, (Idx32)((Rng32)pL + (Rng32)iRight), maskF32);920 Reg::Adds(idxF32, baseIdx, (Idx32)((Rng32)pL + (Rng32)iRight), maskF32);
921- Reg::DataCopyGather(vregF32, dataAddr, idxF32, maskF32);921+ Reg::Gather(vregF32, dataAddr, idxF32, maskF32);
922 for (uint16_t k = 0; k < combPadCnt; k++) {922 for (uint16_t k = 0; k < combPadCnt; k++) {
923 Reg::Adds(idxF32, baseIdx, (Idx32)k, maskF32);923 Reg::Adds(idxF32, baseIdx, (Idx32)k, maskF32);
924- Reg::DataCopyGather(vregPadF32, dataAddr, idxF32, maskF32);924+ Reg::Gather(vregPadF32, dataAddr, idxF32, maskF32);
925 Reg::Add(vregF32, vregF32, vregPadF32, maskF32);925 Reg::Add(vregF32, vregF32, vregPadF32, maskF32);
926 }926 }
927 for (uint16_t k = 0; k < pRu; k++) {927 for (uint16_t k = 0; k < pRu; k++) {
928 Reg::Adds(idxF32, baseIdx, (Idx32)(rightPadStart + (Rng32)k), maskF32);928 Reg::Adds(idxF32, baseIdx, (Idx32)(rightPadStart + (Rng32)k), maskF32);
929- Reg::DataCopyGather(vregPadF32, dataAddr, idxF32, maskF32);929+ Reg::Gather(vregPadF32, dataAddr, idxF32, maskF32);
930 Reg::Add(vregF32, vregF32, vregPadF32, maskF32);930 Reg::Add(vregF32, vregF32, vregPadF32, maskF32);
931 }931 }
932 Reg::Cast<T, PromoteT, CAST_TRAIT_DOWN_ZERO>(vregB16Lo, vregF32, maskB16);932 Reg::Cast<T, PromoteT, CAST_TRAIT_DOWN_ZERO>(vregB16Lo, vregF32, maskB16);
@@ -938,7 +938,7 @@ private:
938 (Reg::RegTensor<Idx16>&)tmpHalf, maskB16);938 (Reg::RegTensor<Idx16>&)tmpHalf, maskB16);
939 Reg::Muls(idxB16, (Reg::RegTensor<Idx16>&)tmpRange16, (Idx16)dN1, maskB16);939 Reg::Muls(idxB16, (Reg::RegTensor<Idx16>&)tmpRange16, (Idx16)dN1, maskB16);
940 Reg::Adds(idxB16, idxB16, (Idx16)((Rng16)b * (Rng16)VL_F32 * (Rng16)dN1 + (Rng16)iRight), maskB16);940 Reg::Adds(idxB16, idxB16, (Idx16)((Rng16)b * (Rng16)VL_F32 * (Rng16)dN1 + (Rng16)iRight), maskB16);
941- Reg::DataCopyScatter(outputAddr, vregScatter, idxB16, maskB16);941+ Reg::Scatter(outputAddr, vregScatter, idxB16, maskB16);
942 }942 }
943 }943 }
944 }944 }
@@ -1031,7 +1031,7 @@ private:
1031 Reg::Sub<IndexT>(ik, quot, tmpReg, mask);1031 Reg::Sub<IndexT>(ik, quot, tmpReg, mask);
1032 Reg::Muls(tmpReg, ik, eS0, mask);1032 Reg::Muls(tmpReg, ik, eS0, mask);
1033 Reg::Add<IndexT>(baseIdx, baseIdx, tmpReg, mask);1033 Reg::Add<IndexT>(baseIdx, baseIdx, tmpReg, mask);
1034- Reg::Copy(quot, qNext);1034+ Reg::Move(quot, qNext);
1035 if constexpr (kEffAxes >= 3) {1035 if constexpr (kEffAxes >= 3) {
1036 Reg::Duplicate(dExt, eE1, mask);1036 Reg::Duplicate(dExt, eE1, mask);
1037 Reg::Div<IndexT>(qNext, quot, dExt, mask);1037 Reg::Div<IndexT>(qNext, quot, dExt, mask);
@@ -1039,7 +1039,7 @@ private:
1039 Reg::Sub<IndexT>(ik, quot, tmpReg, mask);1039 Reg::Sub<IndexT>(ik, quot, tmpReg, mask);
1040 Reg::Muls(tmpReg, ik, eS1, mask);1040 Reg::Muls(tmpReg, ik, eS1, mask);
1041 Reg::Add<IndexT>(baseIdx, baseIdx, tmpReg, mask);1041 Reg::Add<IndexT>(baseIdx, baseIdx, tmpReg, mask);
1042- Reg::Copy(quot, qNext);1042+ Reg::Move(quot, qNext);
1043 if constexpr (kEffAxes >= 4) {1043 if constexpr (kEffAxes >= 4) {
1044 Reg::Duplicate(dExt, eE2, mask);1044 Reg::Duplicate(dExt, eE2, mask);
1045 Reg::Div<IndexT>(qNext, quot, dExt, mask);1045 Reg::Div<IndexT>(qNext, quot, dExt, mask);
@@ -1047,7 +1047,7 @@ private:
1047 Reg::Sub<IndexT>(ik, quot, tmpReg, mask);1047 Reg::Sub<IndexT>(ik, quot, tmpReg, mask);
1048 Reg::Muls(tmpReg, ik, eS2, mask);1048 Reg::Muls(tmpReg, ik, eS2, mask);
1049 Reg::Add<IndexT>(baseIdx, baseIdx, tmpReg, mask);1049 Reg::Add<IndexT>(baseIdx, baseIdx, tmpReg, mask);
1050- Reg::Copy(quot, qNext);1050+ Reg::Move(quot, qNext);
1051 if constexpr (kEffAxes >= 5) {1051 if constexpr (kEffAxes >= 5) {
1052 Reg::Duplicate(dExt, eE3, mask);1052 Reg::Duplicate(dExt, eE3, mask);
1053 Reg::Div<IndexT>(qNext, quot, dExt, mask);1053 Reg::Div<IndexT>(qNext, quot, dExt, mask);
@@ -1055,7 +1055,7 @@ private:
1055 Reg::Sub<IndexT>(ik, quot, tmpReg, mask);1055 Reg::Sub<IndexT>(ik, quot, tmpReg, mask);
1056 Reg::Muls(tmpReg, ik, eS3, mask);1056 Reg::Muls(tmpReg, ik, eS3, mask);
1057 Reg::Add<IndexT>(baseIdx, baseIdx, tmpReg, mask);1057 Reg::Add<IndexT>(baseIdx, baseIdx, tmpReg, mask);
1058- Reg::Copy(quot, qNext);1058+ Reg::Move(quot, qNext);
1059 Reg::Muls(tmpReg, quot, eS4, mask);1059 Reg::Muls(tmpReg, quot, eS4, mask);
1060 Reg::Add<IndexT>(baseIdx, baseIdx, tmpReg, mask);1060 Reg::Add<IndexT>(baseIdx, baseIdx, tmpReg, mask);
1061 } else {1061 } else {
@@ -1078,19 +1078,19 @@ private:
1078 // ======== Phase A: 左边界（iN1=0） ========1078 // ======== Phase A: 左边界（iN1=0） ========
1079 Reg::Adds(idx, baseIdx, (IndexT)pL, mask);1079 Reg::Adds(idx, baseIdx, (IndexT)pL, mask);
1080 if constexpr (sizeof(T) == 1) {1080 if constexpr (sizeof(T) == 1) {
1081- Reg::DataCopyGather((Reg::RegTensor<CastT>&)vregT, dataAddr, idx, mask);1081+ Reg::Gather((Reg::RegTensor<CastT>&)vregT, dataAddr, idx, mask);
1082 } else {1082 } else {
1083- Reg::DataCopyGather(vregT, dataAddr, idx, mask);1083+ Reg::Gather(vregT, dataAddr, idx, mask);
1084 }1084 }
1085 1085 
1086 for (uint16_t k = 0; k < phaseA_pLu; k++) {1086 for (uint16_t k = 0; k < phaseA_pLu; k++) {
1087 Reg::Adds(idx, baseIdx, (IndexT)k, mask);1087 Reg::Adds(idx, baseIdx, (IndexT)k, mask);
1088 if constexpr (sizeof(T) == 1) {1088 if constexpr (sizeof(T) == 1) {
1089- Reg::DataCopyGather((Reg::RegTensor<CastT>&)vregPadT, dataAddr, idx, mask);1089+ Reg::Gather((Reg::RegTensor<CastT>&)vregPadT, dataAddr, idx, mask);
1090 Reg::Add((Reg::RegTensor<CastT>&)vregT, (Reg::RegTensor<CastT>&)vregT,1090 Reg::Add((Reg::RegTensor<CastT>&)vregT, (Reg::RegTensor<CastT>&)vregT,
1091 (Reg::RegTensor<CastT>&)vregPadT, mask);1091 (Reg::RegTensor<CastT>&)vregPadT, mask);
1092 } else {1092 } else {
1093- Reg::DataCopyGather(vregPadT, dataAddr, idx, mask);1093+ Reg::Gather(vregPadT, dataAddr, idx, mask);
1094 Reg::Add(vregT, vregT, vregPadT, mask);1094 Reg::Add(vregT, vregT, vregPadT, mask);
1095 }1095 }
1096 }1096 }
@@ -1102,9 +1102,9 @@ private:
1102 if constexpr (sizeof(T) == 1) {1102 if constexpr (sizeof(T) == 1) {
1103 Reg::Pack(vregOut, (Reg::RegTensor<CastT>&)vregT);1103 Reg::Pack(vregOut, (Reg::RegTensor<CastT>&)vregT);
1104 Reg::UnPack((Reg::RegTensor<CastT>&)vregScatter, vregOut);1104 Reg::UnPack((Reg::RegTensor<CastT>&)vregScatter, vregOut);
1105- Reg::DataCopyScatter(outputAddr, vregScatter, idx, mask);1105+ Reg::Scatter(outputAddr, vregScatter, idx, mask);
1106 } else {1106 } else {
1107- Reg::DataCopyScatter(outputAddr, vregT, idx, mask);1107+ Reg::Scatter(outputAddr, vregT, idx, mask);
1108 }1108 }
1109 1109 
1110 // ======== Phase B: 中间（iN1 ∈ [1, dN1-1)） ========1110 // ======== Phase B: 中间（iN1 ∈ [1, dN1-1)） ========
@@ -1112,9 +1112,9 @@ private:
1112 const uint16_t iN1 = (uint16_t)(i + 1);1112 const uint16_t iN1 = (uint16_t)(i + 1);
1113 Reg::Adds(idx, baseIdx, (IndexT)((RangeT)iN1 + (RangeT)pL), mask);1113 Reg::Adds(idx, baseIdx, (IndexT)((RangeT)iN1 + (RangeT)pL), mask);
1114 if constexpr (sizeof(T) == 1) {1114 if constexpr (sizeof(T) == 1) {
1115- Reg::DataCopyGather((Reg::RegTensor<CastT>&)vregT, dataAddr, idx, mask);1115+ Reg::Gather((Reg::RegTensor<CastT>&)vregT, dataAddr, idx, mask);
1116 } else {1116 } else {
1117- Reg::DataCopyGather(vregT, dataAddr, idx, mask);1117+ Reg::Gather(vregT, dataAddr, idx, mask);
1118 }1118 }
1119 1119 
1120 Reg::Arange(tmpRange, (RangeT)0);1120 Reg::Arange(tmpRange, (RangeT)0);
@@ -1123,29 +1123,29 @@ private:
1123 if constexpr (sizeof(T) == 1) {1123 if constexpr (sizeof(T) == 1) {
1124 Reg::Pack(vregOut, (Reg::RegTensor<CastT>&)vregT);1124 Reg::Pack(vregOut, (Reg::RegTensor<CastT>&)vregT);
1125 Reg::UnPack((Reg::RegTensor<CastT>&)vregScatter, vregOut);1125 Reg::UnPack((Reg::RegTensor<CastT>&)vregScatter, vregOut);
1126- Reg::DataCopyScatter(outputAddr, vregScatter, idx, mask);1126+ Reg::Scatter(outputAddr, vregScatter, idx, mask);
1127 } else {1127 } else {
1128- Reg::DataCopyScatter(outputAddr, vregT, idx, mask);1128+ Reg::Scatter(outputAddr, vregT, idx, mask);
1129 }1129 }
1130 }1130 }
1131 1131 
1132 // ======== Phase C: 右边界（iN1 = dN1-1） ========1132 // ======== Phase C: 右边界（iN1 = dN1-1） ========
1133 Reg::Adds(idx, baseIdx, (IndexT)((RangeT)pL + (RangeT)iRight), mask);1133 Reg::Adds(idx, baseIdx, (IndexT)((RangeT)pL + (RangeT)iRight), mask);
1134 if constexpr (sizeof(T) == 1) {1134 if constexpr (sizeof(T) == 1) {
1135- Reg::DataCopyGather((Reg::RegTensor<CastT>&)vregT, dataAddr, idx, mask);1135+ Reg::Gather((Reg::RegTensor<CastT>&)vregT, dataAddr, idx, mask);
1136 } else {1136 } else {
1137- Reg::DataCopyGather(vregT, dataAddr, idx, mask);1137+ Reg::Gather(vregT, dataAddr, idx, mask);
1138 }1138 }
1139 1139 
1140 // dN1==1: re-accumulate left padding (otherwise lost by Phase C overwrite)1140 // dN1==1: re-accumulate left padding (otherwise lost by Phase C overwrite)
1141 for (uint16_t k = 0; k < combPadCnt; k++) {1141 for (uint16_t k = 0; k < combPadCnt; k++) {
1142 Reg::Adds(idx, baseIdx, (IndexT)k, mask);1142 Reg::Adds(idx, baseIdx, (IndexT)k, mask);
1143 if constexpr (sizeof(T) == 1) {1143 if constexpr (sizeof(T) == 1) {
1144- Reg::DataCopyGather((Reg::RegTensor<CastT>&)vregPadT, dataAddr, idx, mask);1144+ Reg::Gather((Reg::RegTensor<CastT>&)vregPadT, dataAddr, idx, mask);
1145 Reg::Add((Reg::RegTensor<CastT>&)vregT, (Reg::RegTensor<CastT>&)vregT,1145 Reg::Add((Reg::RegTensor<CastT>&)vregT, (Reg::RegTensor<CastT>&)vregT,
1146 (Reg::RegTensor<CastT>&)vregPadT, mask);1146 (Reg::RegTensor<CastT>&)vregPadT, mask);
1147 } else {1147 } else {
1148- Reg::DataCopyGather(vregPadT, dataAddr, idx, mask);1148+ Reg::Gather(vregPadT, dataAddr, idx, mask);
1149 Reg::Add(vregT, vregT, vregPadT, mask);1149 Reg::Add(vregT, vregT, vregPadT, mask);
1150 }1150 }
1151 }1151 }
@@ -1153,11 +1153,11 @@ private:
1153 for (uint16_t k = 0; k < pRu; k++) {1153 for (uint16_t k = 0; k < pRu; k++) {
1154 Reg::Adds(idx, baseIdx, (IndexT)(rightPadStart + (RangeT)k), mask);1154 Reg::Adds(idx, baseIdx, (IndexT)(rightPadStart + (RangeT)k), mask);
1155 if constexpr (sizeof(T) == 1) {1155 if constexpr (sizeof(T) == 1) {
1156- Reg::DataCopyGather((Reg::RegTensor<CastT>&)vregPadT, dataAddr, idx, mask);1156+ Reg::Gather((Reg::RegTensor<CastT>&)vregPadT, dataAddr, idx, mask);
1157 Reg::Add((Reg::RegTensor<CastT>&)vregT, (Reg::RegTensor<CastT>&)vregT,1157 Reg::Add((Reg::RegTensor<CastT>&)vregT, (Reg::RegTensor<CastT>&)vregT,
1158 (Reg::RegTensor<CastT>&)vregPadT, mask);1158 (Reg::RegTensor<CastT>&)vregPadT, mask);
1159 } else {1159 } else {
1160- Reg::DataCopyGather(vregPadT, dataAddr, idx, mask);1160+ Reg::Gather(vregPadT, dataAddr, idx, mask);
1161 Reg::Add(vregT, vregT, vregPadT, mask);1161 Reg::Add(vregT, vregT, vregPadT, mask);
1162 }1162 }
1163 }1163 }
@@ -1168,9 +1168,9 @@ private:
1168 if constexpr (sizeof(T) == 1) {1168 if constexpr (sizeof(T) == 1) {
1169 Reg::Pack(vregOut, (Reg::RegTensor<CastT>&)vregT);1169 Reg::Pack(vregOut, (Reg::RegTensor<CastT>&)vregT);
1170 Reg::UnPack((Reg::RegTensor<CastT>&)vregScatter, vregOut);1170 Reg::UnPack((Reg::RegTensor<CastT>&)vregScatter, vregOut);
1171- Reg::DataCopyScatter(outputAddr, vregScatter, idx, mask);1171+ Reg::Scatter(outputAddr, vregScatter, idx, mask);
1172 } else {1172 } else {
1173- Reg::DataCopyScatter(outputAddr, vregT, idx, mask);1173+ Reg::Scatter(outputAddr, vregT, idx, mask);
1174 }1174 }
1175 }1175 }
1176 }1176 }
Mconversion/space_to_depth/examples/test_geir_space_to_depth.cpp+3-3
@@ -218,7 +218,7 @@ int main(int argc, char* argv[])
218 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};218 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
219 Status ret = ge::GEInitialize(global_options);219 Status ret = ge::GEInitialize(global_options);
220 if (ret != SUCCESS) {220 if (ret != SUCCESS) {
221- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());221+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
222 return FAILED;222 return FAILED;
223 }223 }
224 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());224 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -269,7 +269,7 @@ int main(int argc, char* argv[])
269 std::vector<ge::Tensor> output;269 std::vector<ge::Tensor> output;
270 ret = session->RunGraph(graph_id, input, output);270 ret = session->RunGraph(graph_id, input, output);
271 if (ret != SUCCESS) {271 if (ret != SUCCESS) {
272- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());272+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
273 delete session;273 delete session;
274 GEFinalize();274 GEFinalize();
275 return FAILED;275 return FAILED;
@@ -287,7 +287,7 @@ int main(int argc, char* argv[])
287 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());287 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
288 ret = ge::GEFinalize();288 ret = ge::GEFinalize();
289 if (ret != SUCCESS) {289 if (ret != SUCCESS) {
290- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());290+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
291 return FAILED;291 return FAILED;
292 }292 }
293 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());293 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mconversion/space_to_depth/op_host/arch35/space_to_depth_tiling_arch35.cpp+3-3
@@ -184,9 +184,9 @@ ge::graphStatus SpaceToDepthTilingForAscendC(gert::TilingContext* context,
184 compileInfo.transposeCompilerInfo.ubSize = transposeCompileInfo->ubSize;184 compileInfo.transposeCompilerInfo.ubSize = transposeCompileInfo->ubSize;
185 185 
186 TransposeNddmaTiling transposeTilingObject(context);186 TransposeNddmaTiling transposeTilingObject(context);
187- OP_CHECK_IF((transposeTilingObject.TilingForReleatedTranspose(context, &tilingData.transposeOpTiling,187+ OP_CHECK_IF((transposeTilingObject.TilingForRelatedTranspose(context, &tilingData.transposeOpTiling,
188- &compileInfo.transposeCompilerInfo,188+ &compileInfo.transposeCompilerInfo,
189- inputShapeInfo) == ge::GRAPH_FAILED),189+ inputShapeInfo) == ge::GRAPH_FAILED),
190 OP_LOGE(context->GetNodeName(), "Transpose Tiling failed"), return ge::GRAPH_FAILED);190 OP_LOGE(context->GetNodeName(), "Transpose Tiling failed"), return ge::GRAPH_FAILED);
191 191 
192 tilingData.SaveToBuffer(context->GetRawTilingData()->GetData(), context->GetRawTilingData()->GetCapacity());192 tilingData.SaveToBuffer(context->GetRawTilingData()->GetData(), context->GetRawTilingData()->GetCapacity());
Mconversion/transpose/examples/test_geir_permute.cpp+4-4
@@ -202,7 +202,7 @@ int main(int argc, char* argv[])
202 map<AscendString, AscendString> globalOptions = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};202 map<AscendString, AscendString> globalOptions = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
203 Status ret = ge::GEInitialize(globalOptions);203 Status ret = ge::GEInitialize(globalOptions);
204 if (ret != SUCCESS) {204 if (ret != SUCCESS) {
205- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());205+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
206 return FAILED;206 return FAILED;
207 }207 }
208 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());208 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -241,7 +241,7 @@ int main(int argc, char* argv[])
241 printf("%s - INFO - [XIR]: Start to add compute graph to ir session\n", GetTime().c_str());241 printf("%s - INFO - [XIR]: Start to add compute graph to ir session\n", GetTime().c_str());
242 ret = session->AddGraph(graphId, graph, graphOptions);242 ret = session->AddGraph(graphId, graph, graphOptions);
243 if (ret != SUCCESS) {243 if (ret != SUCCESS) {
244- printf("%s - INFO - [XIR]: Add graph failed\n", GetTime().c_str());244+ printf("%s - ERROR - [XIR]: Add graph failed\n", GetTime().c_str());
245 delete session;245 delete session;
246 ge::GEFinalize();246 ge::GEFinalize();
247 return FAILED;247 return FAILED;
@@ -256,7 +256,7 @@ int main(int argc, char* argv[])
256 vector<Tensor> output;256 vector<Tensor> output;
257 ret = session->RunGraph(graphId, input, output);257 ret = session->RunGraph(graphId, input, output);
258 if (ret != SUCCESS) {258 if (ret != SUCCESS) {
259- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());259+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
260 delete session;260 delete session;
261 ge::GEFinalize();261 ge::GEFinalize();
262 return FAILED;262 return FAILED;
@@ -274,7 +274,7 @@ int main(int argc, char* argv[])
274 delete session;274 delete session;
275 ret = ge::GEFinalize();275 ret = ge::GEFinalize();
276 if (ret != SUCCESS) {276 if (ret != SUCCESS) {
277- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());277+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
278 return FAILED;278 return FAILED;
279 }279 }
280 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());280 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mconversion/transpose/op_host/arch35/transpose_tiling_arch35.cpp+10-11
@@ -82,7 +82,7 @@ ge::graphStatus TransposeNddmaTiling::Init(const int64_t& coreNum, const int64_t
82ge::graphStatus TransposeNddmaTiling::RunTranposelTiling()82ge::graphStatus TransposeNddmaTiling::RunTranposelTiling()
83{83{
84 OP_LOGD(tilingContext_->GetNodeName(), "Start running Tiling4Transpose.");84 OP_LOGD(tilingContext_->GetNodeName(), "Start running Tiling4Transpose.");
85- if (!isReleatedTranspsoe_) {85+ if (!isRelatedTranspose_) {
86 OP_CHECK_IF(GetShapeInfo() != ge::GRAPH_SUCCESS,86 OP_CHECK_IF(GetShapeInfo() != ge::GRAPH_SUCCESS,
87 OP_LOGE(tilingContext_->GetNodeName(), "Failed to get shape info!"), return ge::GRAPH_FAILED);87 OP_LOGE(tilingContext_->GetNodeName(), "Failed to get shape info!"), return ge::GRAPH_FAILED);
88 }88 }
@@ -102,7 +102,7 @@ ge::graphStatus TransposeNddmaTiling::RunTranposelTiling()
102 return ge::GRAPH_SUCCESS);102 return ge::GRAPH_SUCCESS);
103 103 
104 SetIsLastAxisTranspose();104 SetIsLastAxisTranspose();
105- if (!isReleatedTranspsoe_ && shapeInfo_.isLastAxisTranspose) {105+ if (!isRelatedTranspose_ && shapeInfo_.isLastAxisTranspose) {
106 TransWithGather::PlatInfo platInfo{coreNum_, ubSize_, cacheLineSize_, ubBlockSize_};106 TransWithGather::PlatInfo platInfo{coreNum_, ubSize_, cacheLineSize_, ubBlockSize_};
107 TransWithGather::TransposeGatherTiling gatherTiling(tilingContext_, platInfo, shapeInfo_);107 TransWithGather::TransposeGatherTiling gatherTiling(tilingContext_, platInfo, shapeInfo_);
108 OP_CHECK_IF(gatherTiling.DoTiling() == ge::GRAPH_SUCCESS,108 OP_CHECK_IF(gatherTiling.DoTiling() == ge::GRAPH_SUCCESS,
@@ -151,7 +151,7 @@ ge::graphStatus TransposeNddmaTiling::TryVCONVTiling()
151 auto platformInfo = tilingContext_->GetPlatformInfo();151 auto platformInfo = tilingContext_->GetPlatformInfo();
152 auto ascendcPlatform = platform_ascendc::PlatformAscendC(platformInfo);152 auto ascendcPlatform = platform_ascendc::PlatformAscendC(platformInfo);
153 auto arch = ascendcPlatform.GetCurNpuArch();153 auto arch = ascendcPlatform.GetCurNpuArch();
154- if (!isReleatedTranspsoe_ && arch == NpuArch::DAV_5102) {154+ if (!isRelatedTranspose_ && arch == NpuArch::DAV_5102) {
155 SMALL_SHAPE_BYTES_THRES_HOLD = SMALL_SHAPE_BYTES_THRES_HOLD_DAV_5102;155 SMALL_SHAPE_BYTES_THRES_HOLD = SMALL_SHAPE_BYTES_THRES_HOLD_DAV_5102;
156 if (shapeInfo_.reducedPerm[0] == 1 && shapeInfo_.reducedPerm[1] == 0 && shapeInfo_.dim == VCONV_DIM_NUM &&156 if (shapeInfo_.reducedPerm[0] == 1 && shapeInfo_.reducedPerm[1] == 0 && shapeInfo_.dim == VCONV_DIM_NUM &&
157 shapeInfo_.eleLenInBytes == VCONV_DSIZE && shapeInfo_.reducedInShape[0] > DIM_FIVE) {157 shapeInfo_.eleLenInBytes == VCONV_DSIZE && shapeInfo_.reducedInShape[0] > DIM_FIVE) {
@@ -1646,7 +1646,7 @@ void TransposeNddmaTiling::FillTilingData()
1646 tilingData_.transposeOpTiling.set_inUbTailSrcShape(inUbTailSrcShape_);1646 tilingData_.transposeOpTiling.set_inUbTailSrcShape(inUbTailSrcShape_);
1647 tilingData_.transposeOpTiling.set_inUbTailDstShape(inUbTailDstShape_);1647 tilingData_.transposeOpTiling.set_inUbTailDstShape(inUbTailDstShape_);
1648 1648 
1649- if (!isReleatedTranspsoe_) {1649+ if (!isRelatedTranspose_) {
1650 tilingData_.SaveToBuffer(tilingContext_->GetRawTilingData()->GetData(),1650 tilingData_.SaveToBuffer(tilingContext_->GetRawTilingData()->GetData(),
1651 tilingContext_->GetRawTilingData()->GetCapacity());1651 tilingContext_->GetRawTilingData()->GetCapacity());
1652 tilingContext_->GetRawTilingData()->SetDataSize(tilingData_.GetDataSize());1652 tilingContext_->GetRawTilingData()->SetDataSize(tilingData_.GetDataSize());
@@ -1678,23 +1678,22 @@ void TransposeNddmaTiling::PrintTilingData()
1678 tilingData_.transposeOpTiling.get_ubSize(), tilingData_.transposeOpTiling.get_totalNddmaNum());1678 tilingData_.transposeOpTiling.get_ubSize(), tilingData_.transposeOpTiling.get_totalNddmaNum());
1679}1679}
1680 1680 
1681-ge::graphStatus TransposeNddmaTiling::TilingForReleatedTranspose(gert::TilingContext* context,1681+ge::graphStatus TransposeNddmaTiling::TilingForRelatedTranspose(gert::TilingContext* context,
1682- TransposeOpTilingData* tilingData,1682+ TransposeOpTilingData* tilingData,
1683- TransposeCompilerInfo* compilerInfo,1683+ TransposeCompilerInfo* compilerInfo, ShapeInfo& opInput)
1684- ShapeInfo& opInput)
1685{1684{
1686- OP_LOGD(context->GetNodeName(), "Start TilingForReleatedTranspose.");1685+ OP_LOGD(context->GetNodeName(), "Start TilingForRelatedTranspose.");
1687 TransposeNddmaTiling tilingObject(context);1686 TransposeNddmaTiling tilingObject(context);
1688 OP_CHECK_NULL_WITH_CONTEXT(context, tilingData);1687 OP_CHECK_NULL_WITH_CONTEXT(context, tilingData);
1689 tilingObject.tilingContext_ = context;1688 tilingObject.tilingContext_ = context;
1690 tilingObject.tilingData_.transposeOpTiling = *tilingData;1689 tilingObject.tilingData_.transposeOpTiling = *tilingData;
1691 tilingObject.shapeInfo_ = opInput;1690 tilingObject.shapeInfo_ = opInput;
1692 1691 
1693- tilingObject.isReleatedTranspsoe_ = true;1692+ tilingObject.isRelatedTranspose_ = true;
1694 if (tilingObject.Init(compilerInfo->coreNum, compilerInfo->ubSize) != ge::GRAPH_SUCCESS) {1693 if (tilingObject.Init(compilerInfo->coreNum, compilerInfo->ubSize) != ge::GRAPH_SUCCESS) {
1695 return ge::GRAPH_FAILED;1694 return ge::GRAPH_FAILED;
1696 }1695 }
1697- OP_LOGD(context->GetNodeName(), "tilingObject.isReleatedTranspsoe_: %d", tilingObject.isReleatedTranspsoe_);1696+ OP_LOGD(context->GetNodeName(), "tilingObject.isRelatedTranspose_: %d", tilingObject.isRelatedTranspose_);
1698 return tilingObject.RunTranposelTiling();1697 return tilingObject.RunTranposelTiling();
1699}1698}
1700 1699 
Mconversion/transpose/op_host/arch35/transpose_tiling_arch35.h+3-3
@@ -197,8 +197,8 @@ public:
197 explicit TransposeNddmaTiling(gert::TilingContext* context) : tilingContext_(context) {};197 explicit TransposeNddmaTiling(gert::TilingContext* context) : tilingContext_(context) {};
198 ge::graphStatus Init(const int64_t& coreNum, const int64_t& ubSize);198 ge::graphStatus Init(const int64_t& coreNum, const int64_t& ubSize);
199 ge::graphStatus RunTranposelTiling();199 ge::graphStatus RunTranposelTiling();
200- ge::graphStatus TilingForReleatedTranspose(gert::TilingContext* context, TransposeOpTilingData* tilingData,200+ ge::graphStatus TilingForRelatedTranspose(gert::TilingContext* context, TransposeOpTilingData* tilingData,
201- TransposeCompilerInfo* compilerInfo, ShapeInfo& opInput);201+ TransposeCompilerInfo* compilerInfo, ShapeInfo& opInput);
202 202 
203private:203private:
204 template <typename T>204 template <typename T>
@@ -286,7 +286,7 @@ private:
286 int64_t inUbTailSrcShape_[NDDMA_MAX_DIM_NUM] = {0};286 int64_t inUbTailSrcShape_[NDDMA_MAX_DIM_NUM] = {0};
287 int64_t inUbTailDstShape_[NDDMA_MAX_DIM_NUM] = {0};287 int64_t inUbTailDstShape_[NDDMA_MAX_DIM_NUM] = {0};
288 288 
289- bool isReleatedTranspsoe_ = false;289+ bool isRelatedTranspose_ = false;
290};290};
291} // namespace optiling291} // namespace optiling
292 292 
Mmath/erfc/examples/test_aclnn_erfc.cpp+2-2
@@ -171,7 +171,7 @@ int main()
171 std::vector<float> expectData = {1.0, 0.157299, 0.004678, 0.000022};171 std::vector<float> expectData = {1.0, 0.157299, 0.004678, 0.000022};
172 for (int64_t i = 0; i < size; i++) {172 for (int64_t i = 0; i < size; i++) {
173 if (std::fabs(resultData[i] - expectData[i]) > 1e-6) {173 if (std::fabs(resultData[i] - expectData[i]) > 1e-6) {
174- LOG_PRINT("result[%ld] check failed: got %f, expect %f\n", i, resultData[i], expectData[i]);174+ LOG_PRINT("result[%ld] check failed: got %f, expected %f\n", i, resultData[i], expectData[i]);
175 return 1;175 return 1;
176 }176 }
177 }177 }
@@ -186,7 +186,7 @@ int main()
186 }186 }
187 for (int64_t i = 0; i < inplaceSize; i++) {187 for (int64_t i = 0; i < inplaceSize; i++) {
188 if (std::fabs(inplaceResultData[i] - expectData[i]) > 1e-6) {188 if (std::fabs(inplaceResultData[i] - expectData[i]) > 1e-6) {
189- LOG_PRINT("inplaceResult[%ld] check failed: got %f, expect %f\n", i, inplaceResultData[i], expectData[i]);189+ LOG_PRINT("inplaceResult[%ld] check failed: got %f, expected %f\n", i, inplaceResultData[i], expectData[i]);
190 return 1;190 return 1;
191 }191 }
192 }192 }
Mmath/erfc/examples/test_geir_erfc.cpp+3-3
@@ -192,7 +192,7 @@ int InitializeAndSetupGraph(Graph& graph, std::vector<ge::Tensor>& input, DataTy
192 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};192 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
193 Status ret = ge::GEInitialize(global_options);193 Status ret = ge::GEInitialize(global_options);
194 if (ret != SUCCESS) {194 if (ret != SUCCESS) {
195- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());195+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
196 return FAILED;196 return FAILED;
197 }197 }
198 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());198 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -238,7 +238,7 @@ int ExecuteGraph(Graph& graph, std::vector<ge::Tensor>& input, std::vector<ge::T
238 238 
239 ret = session->RunGraph(graph_id, input, output);239 ret = session->RunGraph(graph_id, input, output);
240 if (ret != SUCCESS) {240 if (ret != SUCCESS) {
241- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());241+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
242 delete session;242 delete session;
243 GEFinalize();243 GEFinalize();
244 return FAILED;244 return FAILED;
@@ -315,7 +315,7 @@ int main(int argc, char* argv[])
315 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());315 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
316 Status ret = ge::GEFinalize();316 Status ret = ge::GEFinalize();
317 if (ret != SUCCESS) {317 if (ret != SUCCESS) {
318- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());318+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
319 return FAILED;319 return FAILED;
320 }320 }
321 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());321 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mmath/get_shape/examples/test_geir_get_shape.cpp+3-3
@@ -256,7 +256,7 @@ int main(int argc, char* argv[])
256 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};256 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
257 Status ret = ge::GEInitialize(global_options);257 Status ret = ge::GEInitialize(global_options);
258 if (ret != SUCCESS) {258 if (ret != SUCCESS) {
259- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());259+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
260 return FAILED;260 return FAILED;
261 }261 }
262 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());262 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -304,7 +304,7 @@ int main(int argc, char* argv[])
304 std::vector<ge::Tensor> output;304 std::vector<ge::Tensor> output;
305 ret = session->RunGraph(graph_id, input, output);305 ret = session->RunGraph(graph_id, input, output);
306 if (ret != SUCCESS) {306 if (ret != SUCCESS) {
307- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());307+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
308 delete session;308 delete session;
309 GEFinalize();309 GEFinalize();
310 return FAILED;310 return FAILED;
@@ -322,7 +322,7 @@ int main(int argc, char* argv[])
322 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());322 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
323 ret = ge::GEFinalize();323 ret = ge::GEFinalize();
324 if (ret != SUCCESS) {324 if (ret != SUCCESS) {
325- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());325+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
326 return FAILED;326 return FAILED;
327 }327 }
328 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());328 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mmath/histogram_fixed_width/examples/test_geir_histogram_fixed_width.cpp+3-3
@@ -187,7 +187,7 @@ int main(int argc, char* argv[])
187 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};187 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
188 Status ret = ge::GEInitialize(global_options);188 Status ret = ge::GEInitialize(global_options);
189 if (ret != SUCCESS) {189 if (ret != SUCCESS) {
190- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());190+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
191 return FAILED;191 return FAILED;
192 }192 }
193 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());193 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -238,7 +238,7 @@ int main(int argc, char* argv[])
238 std::vector<ge::Tensor> output;238 std::vector<ge::Tensor> output;
239 ret = session->RunGraph(graph_id, input, output);239 ret = session->RunGraph(graph_id, input, output);
240 if (ret != SUCCESS) {240 if (ret != SUCCESS) {
241- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());241+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
242 delete session;242 delete session;
243 GEFinalize();243 GEFinalize();
244 return FAILED;244 return FAILED;
@@ -280,7 +280,7 @@ int main(int argc, char* argv[])
280 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());280 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
281 ret = ge::GEFinalize();281 ret = ge::GEFinalize();
282 if (ret != SUCCESS) {282 if (ret != SUCCESS) {
283- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());283+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
284 return FAILED;284 return FAILED;
285 }285 }
286 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());286 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mmath/sinc/examples/test_geir_sinc.cpp+3-3
@@ -190,7 +190,7 @@ int InitializeAndSetupGraph(Graph& graph, std::vector<ge::Tensor>& input, DataTy
190 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};190 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
191 Status ret = ge::GEInitialize(global_options);191 Status ret = ge::GEInitialize(global_options);
192 if (ret != SUCCESS) {192 if (ret != SUCCESS) {
193- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());193+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
194 return FAILED;194 return FAILED;
195 }195 }
196 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());196 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -236,7 +236,7 @@ int ExecuteGraph(Graph& graph, std::vector<ge::Tensor>& input, std::vector<ge::T
236 236 
237 ret = session->RunGraph(graph_id, input, output);237 ret = session->RunGraph(graph_id, input, output);
238 if (ret != SUCCESS) {238 if (ret != SUCCESS) {
239- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());239+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
240 delete session;240 delete session;
241 GEFinalize();241 GEFinalize();
242 return FAILED;242 return FAILED;
@@ -313,7 +313,7 @@ int main(int argc, char* argv[])
313 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());313 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
314 Status ret = ge::GEFinalize();314 Status ret = ge::GEFinalize();
315 if (ret != SUCCESS) {315 if (ret != SUCCESS) {
316- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());316+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
317 return FAILED;317 return FAILED;
318 }318 }
319 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());319 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mmath/tile/examples/test_geir_tile.cpp+99-74
@@ -41,50 +41,48 @@ using std::map;
41using std::string;41using std::string;
42using std::vector;42using std::vector;
43 43 
44-#define ADD_INPUT(inputIndex, inputName, inputDtype, inputShape, inputValues) \44+#define ADD_INPUT(inputIndex, inputName, inputDtype, inputShape, inputValues) \
45- do { \45+ do { \
46- std::string name##inputIndex = "placeholder" + std::to_string(inputIndex); \46+ std::string name##inputIndex = "placeholder" + std::to_string(inputIndex); \
47- auto placeholder##inputIndex = op::Data(name##inputIndex.c_str()).set_attr_index(inputIndex - 1); \47+ auto placeholder##inputIndex = op::Data(name##inputIndex.c_str()).set_attr_index(inputIndex - 1); \
48- TensorDesc placeholder##inputIndex##_desc = \48+ TensorDesc placeholder##inputIndex##_desc = TensorDesc(ge::Shape(inputShape), FORMAT_ND, inputDtype); \
49- TensorDesc(ge::Shape(inputShape), FORMAT_ND, inputDtype); \49+ placeholder##inputIndex##_desc.SetPlacement(ge::kPlacementHost); \
50- placeholder##inputIndex##_desc.SetPlacement(ge::kPlacementHost); \50+ placeholder##inputIndex##_desc.SetFormat(FORMAT_ND); \
51- placeholder##inputIndex##_desc.SetFormat(FORMAT_ND); \51+ Tensor tensor_placeholder##inputIndex; \
52- Tensor tensor_placeholder##inputIndex; \52+ ret = GenData(inputShape, tensor_placeholder##inputIndex, placeholder##inputIndex##_desc, inputDtype, \
53- ret = GenData(inputShape, tensor_placeholder##inputIndex, \53+ inputValues); \
54- placeholder##inputIndex##_desc, inputDtype, inputValues); \54+ if (ret != SUCCESS) { \
55- if (ret != SUCCESS) { \55+ printf("%s - ERROR - [XIR]: Generate input data failed\n", GetTime().c_str()); \
56- printf("%s - ERROR - [XIR]: Generate input data failed\n", GetTime().c_str()); \56+ return FAILED; \
57- return FAILED; \57+ } \
58- } \58+ placeholder##inputIndex.update_input_desc_x(placeholder##inputIndex##_desc); \
59- placeholder##inputIndex.update_input_desc_x(placeholder##inputIndex##_desc); \59+ placeholder##inputIndex.update_output_desc_y(placeholder##inputIndex##_desc); \
60- placeholder##inputIndex.update_output_desc_y(placeholder##inputIndex##_desc); \60+ input.push_back(tensor_placeholder##inputIndex); \
61- input.push_back(tensor_placeholder##inputIndex); \61+ graph.AddOp(placeholder##inputIndex); \
62- graph.AddOp(placeholder##inputIndex); \62+ tile1.set_input_##inputName(placeholder##inputIndex); \
63- tile1.set_input_##inputName(placeholder##inputIndex); \63+ inputs.push_back(placeholder##inputIndex); \
64- inputs.push_back(placeholder##inputIndex); \
65 } while (0)64 } while (0)
66 65 
67-#define ADD_CONST_INPUT(inputIndex, inputName, inputDtype, inputShape, inputValues) \66+#define ADD_CONST_INPUT(inputIndex, inputName, inputDtype, inputShape, inputValues) \
68- do { \67+ do { \
69- std::string name##inputIndex = "placeholder" + std::to_string(inputIndex); \68+ std::string name##inputIndex = "placeholder" + std::to_string(inputIndex); \
70- auto placeholder##inputIndex = op::Const(name##inputIndex.c_str()); \69+ auto placeholder##inputIndex = op::Const(name##inputIndex.c_str()); \
71- TensorDesc placeholder##inputIndex##_desc = \70+ TensorDesc placeholder##inputIndex##_desc = TensorDesc(ge::Shape(inputShape), FORMAT_ND, inputDtype); \
72- TensorDesc(ge::Shape(inputShape), FORMAT_ND, inputDtype); \71+ placeholder##inputIndex##_desc.SetPlacement(ge::kPlacementHost); \
73- placeholder##inputIndex##_desc.SetPlacement(ge::kPlacementHost); \72+ placeholder##inputIndex##_desc.SetFormat(FORMAT_ND); \
74- placeholder##inputIndex##_desc.SetFormat(FORMAT_ND); \73+ Tensor tensor_placeholder##inputIndex; \
75- Tensor tensor_placeholder##inputIndex; \74+ ret = GenData(inputShape, tensor_placeholder##inputIndex, placeholder##inputIndex##_desc, inputDtype, \
76- ret = GenData(inputShape, tensor_placeholder##inputIndex, \75+ inputValues); \
77- placeholder##inputIndex##_desc, inputDtype, inputValues); \76+ if (ret != SUCCESS) { \
78- if (ret != SUCCESS) { \77+ printf("%s - ERROR - [XIR]: Generate input data failed\n", GetTime().c_str()); \
79- printf("%s - ERROR - [XIR]: Generate input data failed\n", GetTime().c_str()); \78+ return FAILED; \
80- return FAILED; \79+ } \
81- } \80+ placeholder##inputIndex.SetAttr("value", tensor_placeholder##inputIndex); \
82- placeholder##inputIndex.SetAttr("value", tensor_placeholder##inputIndex); \81+ placeholder##inputIndex.update_output_desc_y(placeholder##inputIndex##_desc); \
83- placeholder##inputIndex.update_output_desc_y(placeholder##inputIndex##_desc); \82+ graph.AddOp(placeholder##inputIndex); \
84- graph.AddOp(placeholder##inputIndex); \83+ tile1.set_input_##inputName(placeholder##inputIndex); \
85- tile1.set_input_##inputName(placeholder##inputIndex); \84+ tile1.update_input_desc_##inputName(placeholder##inputIndex##_desc); \
86- tile1.update_input_desc_##inputName(placeholder##inputIndex##_desc); \85+ inputs.push_back(placeholder##inputIndex); \
87- inputs.push_back(placeholder##inputIndex); \
88 } while (0)86 } while (0)
89 87 
90string GetTime()88string GetTime()
@@ -99,24 +97,35 @@ string GetTime()
99uint32_t GetDataTypeSize(DataType dt)97uint32_t GetDataTypeSize(DataType dt)
100{98{
101 switch (dt) {99 switch (dt) {
102- case ge::DT_BOOL: return 1U;100+ case ge::DT_BOOL:
103- case ge::DT_INT8: return 1U;101+ return 1U;
104- case ge::DT_UINT8: return 1U;102+ case ge::DT_INT8:
105- case ge::DT_INT16: return 2U;103+ return 1U;
106- case ge::DT_UINT16: return 2U;104+ case ge::DT_UINT8:
107- case ge::DT_INT32: return 4U;105+ return 1U;
108- case ge::DT_UINT32: return 4U;106+ case ge::DT_INT16:
109- case ge::DT_INT64: return 8U;107+ return 2U;
110- case ge::DT_UINT64: return 8U;108+ case ge::DT_UINT16:
111- case ge::DT_FLOAT: return 4U;109+ return 2U;
112- case ge::DT_DOUBLE: return 8U;110+ case ge::DT_INT32:
113- default: return 0U;111+ return 4U;
112+ case ge::DT_UINT32:
113+ return 4U;
114+ case ge::DT_INT64:
115+ return 8U;
116+ case ge::DT_UINT64:
117+ return 8U;
118+ case ge::DT_FLOAT:
119+ return 4U;
120+ case ge::DT_DOUBLE:
121+ return 8U;
122+ default:
123+ return 0U;
114 }124 }
115}125}
116 126 
117-int32_t GenData(127+int32_t GenData(const vector<int64_t>& shapes, Tensor& inputTensor, TensorDesc& inputTensorDesc, DataType dataType,
118- const vector<int64_t>& shapes, Tensor& inputTensor, TensorDesc& inputTensorDesc,128+ const vector<double>& values)
119- DataType dataType, const vector<double>& values)
120{129{
121 uint32_t typeSize = GetDataTypeSize(dataType);130 uint32_t typeSize = GetDataTypeSize(dataType);
122 if (typeSize == 0U) {131 if (typeSize == 0U) {
@@ -127,7 +136,9 @@ int32_t GenData(
127 136 
128 inputTensorDesc.SetRealDimCnt(shapes.size());137 inputTensorDesc.SetRealDimCnt(shapes.size());
129 size_t size = 1;138 size_t size = 1;
130- for (uint32_t i = 0; i < shapes.size(); i++) { size *= shapes[i]; }139+ for (uint32_t i = 0; i < shapes.size(); i++) {
140+ size *= shapes[i];
141+ }
131 if (size != values.size()) {142 if (size != values.size()) {
132 printf("ERROR: GenData shape size %zu != values size %zu\n", size, values.size());143 printf("ERROR: GenData shape size %zu != values size %zu\n", size, values.size());
133 return FAILED;144 return FAILED;
@@ -135,62 +146,75 @@ int32_t GenData(
135 146 
136 uint32_t dataLen = size * typeSize;147 uint32_t dataLen = size * typeSize;
137 uint8_t* pData = new (std::nothrow) uint8_t[dataLen];148 uint8_t* pData = new (std::nothrow) uint8_t[dataLen];
138- if (pData == nullptr) { return FAILED; }149+ if (pData == nullptr) {
150+ return FAILED;
151+ }
139 152 
140 switch (dataType) {153 switch (dataType) {
141 case ge::DT_BOOL: {154 case ge::DT_BOOL: {
142 bool* data = reinterpret_cast<bool*>(pData);155 bool* data = reinterpret_cast<bool*>(pData);
143- for (size_t i = 0; i < size; ++i) data[i] = (values[i] != 0);156+ for (size_t i = 0; i < size; ++i)
157+ data[i] = (values[i] != 0);
144 break;158 break;
145 }159 }
146 case ge::DT_INT8: {160 case ge::DT_INT8: {
147 int8_t* data = reinterpret_cast<int8_t*>(pData);161 int8_t* data = reinterpret_cast<int8_t*>(pData);
148- for (size_t i = 0; i < size; ++i) data[i] = static_cast<int8_t>(values[i]);162+ for (size_t i = 0; i < size; ++i)
163+ data[i] = static_cast<int8_t>(values[i]);
149 break;164 break;
150 }165 }
151 case ge::DT_UINT8: {166 case ge::DT_UINT8: {
152 uint8_t* data = pData;167 uint8_t* data = pData;
153- for (size_t i = 0; i < size; ++i) data[i] = static_cast<uint8_t>(values[i]);168+ for (size_t i = 0; i < size; ++i)
169+ data[i] = static_cast<uint8_t>(values[i]);
154 break;170 break;
155 }171 }
156 case ge::DT_INT16: {172 case ge::DT_INT16: {
157 int16_t* data = reinterpret_cast<int16_t*>(pData);173 int16_t* data = reinterpret_cast<int16_t*>(pData);
158- for (size_t i = 0; i < size; ++i) data[i] = static_cast<int16_t>(values[i]);174+ for (size_t i = 0; i < size; ++i)
175+ data[i] = static_cast<int16_t>(values[i]);
159 break;176 break;
160 }177 }
161 case ge::DT_UINT16: {178 case ge::DT_UINT16: {
162 uint16_t* data = reinterpret_cast<uint16_t*>(pData);179 uint16_t* data = reinterpret_cast<uint16_t*>(pData);
163- for (size_t i = 0; i < size; ++i) data[i] = static_cast<uint16_t>(values[i]);180+ for (size_t i = 0; i < size; ++i)
181+ data[i] = static_cast<uint16_t>(values[i]);
164 break;182 break;
165 }183 }
166 case ge::DT_INT32: {184 case ge::DT_INT32: {
167 int32_t* data = reinterpret_cast<int32_t*>(pData);185 int32_t* data = reinterpret_cast<int32_t*>(pData);
168- for (size_t i = 0; i < size; ++i) data[i] = static_cast<int32_t>(values[i]);186+ for (size_t i = 0; i < size; ++i)
187+ data[i] = static_cast<int32_t>(values[i]);
169 break;188 break;
170 }189 }
171 case ge::DT_UINT32: {190 case ge::DT_UINT32: {
172 uint32_t* data = reinterpret_cast<uint32_t*>(pData);191 uint32_t* data = reinterpret_cast<uint32_t*>(pData);
173- for (size_t i = 0; i < size; ++i) data[i] = static_cast<uint32_t>(values[i]);192+ for (size_t i = 0; i < size; ++i)
193+ data[i] = static_cast<uint32_t>(values[i]);
174 break;194 break;
175 }195 }
176 case ge::DT_INT64: {196 case ge::DT_INT64: {
177 int64_t* data = reinterpret_cast<int64_t*>(pData);197 int64_t* data = reinterpret_cast<int64_t*>(pData);
178- for (size_t i = 0; i < size; ++i) data[i] = static_cast<int64_t>(values[i]);198+ for (size_t i = 0; i < size; ++i)
199+ data[i] = static_cast<int64_t>(values[i]);
179 break;200 break;
180 }201 }
181 case ge::DT_UINT64: {202 case ge::DT_UINT64: {
182 uint64_t* data = reinterpret_cast<uint64_t*>(pData);203 uint64_t* data = reinterpret_cast<uint64_t*>(pData);
183- for (size_t i = 0; i < size; ++i) data[i] = static_cast<uint64_t>(values[i]);204+ for (size_t i = 0; i < size; ++i)
205+ data[i] = static_cast<uint64_t>(values[i]);
184 break;206 break;
185 }207 }
186 case ge::DT_FLOAT: {208 case ge::DT_FLOAT: {
187 float* data = reinterpret_cast<float*>(pData);209 float* data = reinterpret_cast<float*>(pData);
188- for (size_t i = 0; i < size; ++i) data[i] = static_cast<float>(values[i]);210+ for (size_t i = 0; i < size; ++i)
211+ data[i] = static_cast<float>(values[i]);
189 break;212 break;
190 }213 }
191 case ge::DT_DOUBLE: {214 case ge::DT_DOUBLE: {
192 double* data = reinterpret_cast<double*>(pData);215 double* data = reinterpret_cast<double*>(pData);
193- for (size_t i = 0; i < size; ++i) data[i] = values[i];216+ for (size_t i = 0; i < size; ++i)
217+ data[i] = values[i];
194 break;218 break;
195 }219 }
196 // FLOAT16/BF16/COMPLEX blocked by typeSize==0 check above220 // FLOAT16/BF16/COMPLEX blocked by typeSize==0 check above
@@ -214,7 +238,8 @@ int32_t WriteDataToFile(const string& binFile, uint64_t dataSize, uint8_t* input
214 return SUCCESS;238 return SUCCESS;
215}239}
216 240 
217-int CreateOppInGraph(DataType inDtype, vector<Tensor>& input, vector<Operator>& inputs, vector<Operator>& outputs, Graph& graph)241+int CreateOppInGraph(DataType inDtype, vector<Tensor>& input, vector<Operator>& inputs, vector<Operator>& outputs,
242+ Graph& graph)
218{243{
219 Status ret = SUCCESS;244 Status ret = SUCCESS;
220 auto tile1 = op::Tile("tile1");245 auto tile1 = op::Tile("tile1");
@@ -237,7 +262,7 @@ int main(int argc, char* argv[])
237 map<AscendString, AscendString> globalOptions = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};262 map<AscendString, AscendString> globalOptions = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
238 Status ret = ge::GEInitialize(globalOptions);263 Status ret = ge::GEInitialize(globalOptions);
239 if (ret != SUCCESS) {264 if (ret != SUCCESS) {
240- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());265+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
241 return FAILED;266 return FAILED;
242 }267 }
243 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());268 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -337,9 +362,9 @@ int main(int argc, char* argv[])
337 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());362 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
338 ret = ge::GEFinalize();363 ret = ge::GEFinalize();
339 if (ret != SUCCESS) {364 if (ret != SUCCESS) {
340- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());365+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
341 return FAILED;366 return FAILED;
342 }367 }
343 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());368 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
344 return SUCCESS;369 return SUCCESS;
345-}370+}
Mmath/tile/op_api/aclnn_repeat.cpp+1-1
@@ -205,7 +205,7 @@ aclnnStatus aclnnRepeatGetWorkspaceSize(const aclTensor* self, const aclIntArray
205 return ACLNN_SUCCESS;205 return ACLNN_SUCCESS;
206 }206 }
207 if (self->GetStorageFormat() != Format::FORMAT_ND) {207 if (self->GetStorageFormat() != Format::FORMAT_ND) {
208- OP_LOGW("Format only support ND");208+ OP_LOGW("Format only supports ND");
209 }209 }
210 if (repeats->Size() == 0) {210 if (repeats->Size() == 0) {
211 auto viewCopyOut = l0op::ViewCopy(self, out, uniqueExecutor.get());211 auto viewCopyOut = l0op::ViewCopy(self, out, uniqueExecutor.get());
Mmath/tile/op_host/arch35/tile_tiling_arch35.cpp+3-3
@@ -110,7 +110,7 @@ static ge::graphStatus GetShapeInfo(const gert::TilingContext* context, gert::Sh
110 }110 }
111 ConvertTileAxis2BroadcastToAxis(inShape, outShape);111 ConvertTileAxis2BroadcastToAxis(inShape, outShape);
112 112 
113- OP_LOGI(context->GetNodeName(), "The broadcastTo input and output after conversion is: %s and %s",113+ OP_LOGI(context->GetNodeName(), "The broadcastTo input and output after conversion are: %s and %s",
114 Shape2String(inShape).c_str(), Shape2String(outShape).c_str());114 Shape2String(inShape).c_str(), Shape2String(outShape).c_str());
115 115 
116 if (brcto::DeleteOneSizeAxis(context, inShape, outShape) != ge::GRAPH_SUCCESS) {116 if (brcto::DeleteOneSizeAxis(context, inShape, outShape) != ge::GRAPH_SUCCESS) {
@@ -119,7 +119,7 @@ static ge::graphStatus GetShapeInfo(const gert::TilingContext* context, gert::Sh
119 OP_LOGE_FOR_INVALID_SHAPES_WITH_REASON(context->GetNodeName(), "x and y", shapeMsg.c_str(), reasonMsg.c_str());119 OP_LOGE_FOR_INVALID_SHAPES_WITH_REASON(context->GetNodeName(), "x and y", shapeMsg.c_str(), reasonMsg.c_str());
120 return ge::GRAPH_FAILED;120 return ge::GRAPH_FAILED;
121 }121 }
122- OP_LOGI(context->GetNodeName(), "The reshaped input and output is: %s and %s", Shape2String(inShape).c_str(),122+ OP_LOGI(context->GetNodeName(), "The reshaped input and output are: %s and %s", Shape2String(inShape).c_str(),
123 Shape2String(outShape).c_str());123 Shape2String(outShape).c_str());
124 124 
125 if (brcto::MergeAxis(context, inShape, outShape) != ge::GRAPH_SUCCESS) {125 if (brcto::MergeAxis(context, inShape, outShape) != ge::GRAPH_SUCCESS) {
@@ -128,7 +128,7 @@ static ge::graphStatus GetShapeInfo(const gert::TilingContext* context, gert::Sh
128 OP_LOGE_FOR_INVALID_SHAPES_WITH_REASON(context->GetNodeName(), "x and y", shapeMsg.c_str(), reasonMsg.c_str());128 OP_LOGE_FOR_INVALID_SHAPES_WITH_REASON(context->GetNodeName(), "x and y", shapeMsg.c_str(), reasonMsg.c_str());
129 return ge::GRAPH_FAILED;129 return ge::GRAPH_FAILED;
130 }130 }
131- OP_LOGI(context->GetNodeName(), "The merged input and output is: %s and %s", Shape2String(inShape).c_str(),131+ OP_LOGI(context->GetNodeName(), "The merged input and output are: %s and %s", Shape2String(inShape).c_str(),
132 Shape2String(outShape).c_str());132 Shape2String(outShape).c_str());
133 133 
134 return ge::GRAPH_SUCCESS;134 return ge::GRAPH_SUCCESS;
Mmath/tile/op_host/tile_infershape.cpp+1-1
@@ -88,7 +88,7 @@ static ge::graphStatus InferShape4Tile(gert::InferShapeContext* context)
88 DataType data_type = multiples_tensor->GetDataType();88 DataType data_type = multiples_tensor->GetDataType();
89 OP_CHECK_IF(89 OP_CHECK_IF(
90 (data_type != DT_INT32) && (data_type != DT_INT64),90 (data_type != DT_INT32) && (data_type != DT_INT64),
91- OP_LOGE(context->GetNodeName(), "multiples's dtype %s must be in (int32,int64)!", ToString(data_type).c_str()),91+ OP_LOGE(context->GetNodeName(), "multiples' dtype %s must be in (int32,int64)!", ToString(data_type).c_str()),
92 return ge::GRAPH_FAILED);92 return ge::GRAPH_FAILED);
93 93 
94 if (data_type == DT_INT32) {94 if (data_type == DT_INT32) {
Mmath/truncate_div/examples/test_geir_truncate_div.cpp+3-3
@@ -207,7 +207,7 @@ int main(int argc, char* argv[])
207 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};207 std::map<AscendString, AscendString> global_options = {{"ge.exec.deviceId", "0"}, {"ge.graphRunMode", "1"}};
208 Status ret = ge::GEInitialize(global_options);208 Status ret = ge::GEInitialize(global_options);
209 if (ret != SUCCESS) {209 if (ret != SUCCESS) {
210- printf("%s - INFO - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());210+ printf("%s - ERROR - [XIR]: Initialize ge using ge global options failed\n", GetTime().c_str());
211 return FAILED;211 return FAILED;
212 }212 }
213 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());213 printf("%s - INFO - [XIR]: Initialize ge using ge global options success\n", GetTime().c_str());
@@ -258,7 +258,7 @@ int main(int argc, char* argv[])
258 std::vector<ge::Tensor> output;258 std::vector<ge::Tensor> output;
259 ret = session->RunGraph(graph_id, input, output);259 ret = session->RunGraph(graph_id, input, output);
260 if (ret != SUCCESS) {260 if (ret != SUCCESS) {
261- printf("%s - INFO - [XIR]: Run graph failed\n", GetTime().c_str());261+ printf("%s - ERROR - [XIR]: Run graph failed\n", GetTime().c_str());
262 delete session;262 delete session;
263 GEFinalize();263 GEFinalize();
264 return FAILED;264 return FAILED;
@@ -276,7 +276,7 @@ int main(int argc, char* argv[])
276 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());276 printf("%s - INFO - [XIR]: Start to finalize ir graph session\n", GetTime().c_str());
277 ret = ge::GEFinalize();277 ret = ge::GEFinalize();
278 if (ret != SUCCESS) {278 if (ret != SUCCESS) {
279- printf("%s - INFO - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());279+ printf("%s - ERROR - [XIR]: Finalize ir graph session failed\n", GetTime().c_str());
280 return FAILED;280 return FAILED;
281 }281 }
282 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());282 printf("%s - INFO - [XIR]: Finalize ir graph session success\n", GetTime().c_str());
Mmath/truncate_div/op_kernel/arch35/truncate_div_dag.h+17-17
@@ -60,7 +60,7 @@ struct TruncCustom : public Vec::ElemwiseUnaryOP<T, T> {
60 for (uint16_t loopIdx = 0; loopIdx < loopNum; loopIdx++) {60 for (uint16_t loopIdx = 0; loopIdx < loopNum; loopIdx++) {
61 mask = Reg::UpdateMask<T, Reg::RegTraitNumOne>(count);61 mask = Reg::UpdateMask<T, Reg::RegTraitNumOne>(count);
62 // OpCopyIn62 // OpCopyIn
63- Reg::DataCopy(vregInput, (__ubuf__ T*)(srcAddr + loopIdx * vlSize));63+ Reg::LoadAlign(vregInput, (__ubuf__ T*)(srcAddr + loopIdx * vlSize));
64 64 
65 Reg::Truncate<T, RoundMode::CAST_TRUNC, Reg::MaskMergeMode::ZEROING>(vregOutput, vregInput, mask);65 Reg::Truncate<T, RoundMode::CAST_TRUNC, Reg::MaskMergeMode::ZEROING>(vregOutput, vregInput, mask);
66 Reg::Duplicate(vregOutInt, UINT32_SIGN, mask);66 Reg::Duplicate(vregOutInt, UINT32_SIGN, mask);
@@ -68,7 +68,7 @@ struct TruncCustom : public Vec::ElemwiseUnaryOP<T, T> {
68 Reg::Or(vregOutInt, vregOutInt, (Reg::RegTensor<uint32_t>&)vregOutput, mask);68 Reg::Or(vregOutInt, vregOutInt, (Reg::RegTensor<uint32_t>&)vregOutput, mask);
69 69 
70 // OpCopyOut70 // OpCopyOut
71- Reg::DataCopy((__ubuf__ T*)(dstAddr + loopIdx * vlSize), (Reg::RegTensor<T>&)vregOutInt, mask);71+ Reg::StoreAlign((__ubuf__ T*)(dstAddr + loopIdx * vlSize), (Reg::RegTensor<T>&)vregOutInt, mask);
72 }72 }
73 }73 }
74 } else {74 } else {
@@ -78,7 +78,7 @@ struct TruncCustom : public Vec::ElemwiseUnaryOP<T, T> {
78 for (uint16_t loopIdx = 0; loopIdx < loopNum; loopIdx++) {78 for (uint16_t loopIdx = 0; loopIdx < loopNum; loopIdx++) {
79 mask = Reg::UpdateMask<T, Reg::RegTraitNumOne>(count);79 mask = Reg::UpdateMask<T, Reg::RegTraitNumOne>(count);
80 // OpCopyIn80 // OpCopyIn
81- Reg::DataCopy(vregInput, (__ubuf__ T*)(srcAddr + loopIdx * vlSize));81+ Reg::LoadAlign(vregInput, (__ubuf__ T*)(srcAddr + loopIdx * vlSize));
82 82 
83 Reg::Truncate<T, RoundMode::CAST_TRUNC, Reg::MaskMergeMode::ZEROING>(vregOutput, vregInput, mask);83 Reg::Truncate<T, RoundMode::CAST_TRUNC, Reg::MaskMergeMode::ZEROING>(vregOutput, vregInput, mask);
84 Reg::Duplicate(vregOutInt, UINT16_SIGN, mask);84 Reg::Duplicate(vregOutInt, UINT16_SIGN, mask);
@@ -86,7 +86,7 @@ struct TruncCustom : public Vec::ElemwiseUnaryOP<T, T> {
86 Reg::Or(vregOutInt, vregOutInt, (Reg::RegTensor<uint16_t>&)vregOutput, mask);86 Reg::Or(vregOutInt, vregOutInt, (Reg::RegTensor<uint16_t>&)vregOutput, mask);
87 87 
88 // OpCopyOut88 // OpCopyOut
89- Reg::DataCopy((__ubuf__ T*)(dstAddr + loopIdx * vlSize), (Reg::RegTensor<T>&)vregOutInt, mask);89+ Reg::StoreAlign((__ubuf__ T*)(dstAddr + loopIdx * vlSize), (Reg::RegTensor<T>&)vregOutInt, mask);
90 }90 }
91 }91 }
92 }92 }
@@ -110,14 +110,14 @@ struct CastOverFlow : public Vec::ElemwiseUnaryOP<R, T> {
110 Reg::MaskReg preg0;110 Reg::MaskReg preg0;
111 uint32_t size = count;111 uint32_t size = count;
112 uint16_t vfLoopNum = (size + (VECTOR_REG_WIDTH / sizeof(T)) - 1) / (VECTOR_REG_WIDTH / sizeof(T));112 uint16_t vfLoopNum = (size + (VECTOR_REG_WIDTH / sizeof(T)) - 1) / (VECTOR_REG_WIDTH / sizeof(T));
113- __local_mem__ T* bufferIn0Addr = (__local_mem__ T*)src.GetPhyAddr();113+ __ubuf__ T* bufferIn0Addr = (__ubuf__ T*)src.GetPhyAddr();
114- __local_mem__ R* bufferOut0Addr = (__local_mem__ R*)dst.GetPhyAddr();114+ __ubuf__ R* bufferOut0Addr = (__ubuf__ R*)dst.GetPhyAddr();
115 for (uint16_t i = 0; i < vfLoopNum; i++) {115 for (uint16_t i = 0; i < vfLoopNum; i++) {
116 preg0 = Reg::UpdateMask<T>(size);116 preg0 = Reg::UpdateMask<T>(size);
117- Reg::DataCopy<T, Reg::LoadDist::DIST_NORM>(vreg0, bufferIn0Addr + i * (VECTOR_REG_WIDTH / sizeof(T)));117+ Reg::LoadAlign<T, Reg::LoadDist::DIST_NORM>(vreg0, bufferIn0Addr + i * (VECTOR_REG_WIDTH / sizeof(T)));
118 Reg::Cast<R, T, castTrait3>(vreg1, vreg0, preg0);118 Reg::Cast<R, T, castTrait3>(vreg1, vreg0, preg0);
119- Reg::DataCopy<R, Reg::StoreDist::DIST_PACK_B16>(bufferOut0Addr + i * (VECTOR_REG_WIDTH / sizeof(T)),119+ Reg::StoreAlign<R, Reg::StoreDist::DIST_PACK_B16>(bufferOut0Addr + i * (VECTOR_REG_WIDTH / sizeof(T)),
120- vreg1, preg0);120+ vreg1, preg0);
121 }121 }
122 }122 }
123 SetCtrlSpr<SAT_POS, SAT_POS>(1);123 SetCtrlSpr<SAT_POS, SAT_POS>(1);
@@ -134,10 +134,10 @@ struct TruncIntPostCompute : public Vec::ElemwiseTernaryOP<T, T, T, T> {
134#ifdef __CCE_AICORE__134#ifdef __CCE_AICORE__
135 constexpr uint32_t VECTOR_LENGTH = GetVRegSize();135 constexpr uint32_t VECTOR_LENGTH = GetVRegSize();
136 constexpr uint32_t VL_T = VECTOR_LENGTH / sizeof(T);136 constexpr uint32_t VL_T = VECTOR_LENGTH / sizeof(T);
137- __local_mem__ T* input1Addr = (__local_mem__ T*)input1.GetPhyAddr();137+ __ubuf__ T* input1Addr = (__ubuf__ T*)input1.GetPhyAddr();
138- __local_mem__ T* input2Addr = (__local_mem__ T*)input2.GetPhyAddr();138+ __ubuf__ T* input2Addr = (__ubuf__ T*)input2.GetPhyAddr();
139- __local_mem__ T* divAddr = (__local_mem__ T*)div.GetPhyAddr();139+ __ubuf__ T* divAddr = (__ubuf__ T*)div.GetPhyAddr();
140- __local_mem__ T* dstAddr = (__local_mem__ T*)dst.GetPhyAddr();140+ __ubuf__ T* dstAddr = (__ubuf__ T*)dst.GetPhyAddr();
141 uint16_t loopTimes = CeilDiv(count, VL_T);141 uint16_t loopTimes = CeilDiv(count, VL_T);
142 142 
143 __VEC_SCOPE__143 __VEC_SCOPE__
@@ -157,12 +157,12 @@ struct TruncIntPostCompute : public Vec::ElemwiseTernaryOP<T, T, T, T> {
157 157 
158 for (uint16_t j = 0; j < loopTimes; j++) {158 for (uint16_t j = 0; j < loopTimes; j++) {
159 preg = Reg::UpdateMask<T>(sregMask);159 preg = Reg::UpdateMask<T>(sregMask);
160- Reg::DataCopy<T, Reg::LoadDist::DIST_NORM>(input2Value, input2Addr + VL_T * j);160+ Reg::LoadAlign<T, Reg::LoadDist::DIST_NORM>(input2Value, input2Addr + VL_T * j);
161- Reg::DataCopy<T, Reg::LoadDist::DIST_NORM>(divValue, divAddr + VL_T * j);161+ Reg::LoadAlign<T, Reg::LoadDist::DIST_NORM>(divValue, divAddr + VL_T * j);
162- Reg::DataCopy<T, Reg::LoadDist::DIST_NORM>(input1Value, input1Addr + VL_T * j);162+ Reg::LoadAlign<T, Reg::LoadDist::DIST_NORM>(input1Value, input1Addr + VL_T * j);
163 Reg::Compare<T, CMPMODE::NE>(cmpValue, input2Value, zeroValue, preg);163 Reg::Compare<T, CMPMODE::NE>(cmpValue, input2Value, zeroValue, preg);
164 Reg::Select(resValue, divValue, defaultValue, cmpValue);164 Reg::Select(resValue, divValue, defaultValue, cmpValue);
165- Reg::DataCopy<T, Reg::StoreDist::DIST_NORM>(dstAddr + VL_T * j, resValue, preg);165+ Reg::StoreAlign<T, Reg::StoreDist::DIST_NORM>(dstAddr + VL_T * j, resValue, preg);
166 }166 }
167 }167 }
168#endif168#endif