| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
arch/risc-v: Add clkdev drivers for esp32 timers. This commit added clkdev drivers for esp32 timers. Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com> | 2 个月前 | |
arch/smp: update g_running_tasks to percpu/g_running_task If remove whole g_running_tasks, or replace it self as a macrro, will cause the gdb plugin not working. Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
arch/risc-v: support decouple signal related function from arch code Signed-off-by: guoshichao <guoshichao@xiaomi.com> | 2 个月前 | |
arch/risc-v: support decouple signal related function from arch code Signed-off-by: guoshichao <guoshichao@xiaomi.com> | 2 个月前 | |
arch: delete -fno-optimize-sibling-calls Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com> | 2 个月前 | |
arch: move some macros to public code. Signed-off-by: hujun5 <hujun5@xiaomi.com> | 2 个月前 | |
elf:use SUBALIGN(SECTIONS_ALIGN) set elf section sh_aligment Some architectures of the MPU have alignment requirements for the starting position, so use SUBALGIN to set the alignment. Signed-off-by: anjiahao <anjiahao@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
riscv-v/pgalloc.h: Return kernel vaddr for kernel RAM paddr All kernel memory is mapped paddr=vaddr, so it is trivial to give mapping for kernel memory. Only interesting region should be kernel RAM, so omit kernel ROM and don't allow re-mapping it. | 2 个月前 | |
arch/riscv: use UP_DSB, UP_DMB, UP_ISB as barrier standard API Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com> | 2 个月前 | |
arch/risc-v: Fix the compilation error. common/riscv_addrenv_kstack.c: In function 'up_addrenv_kstackalloc': common/riscv_addrenv_kstack.c:68:34: error: 'TLS_STACK_ALIGN' undeclared (first use in this function) 68 | tcb->xcp.kstack = kmm_memalign(STACK_ALIGNMENT, ARCH_KERNEL_STACKSIZE); | ^~~~~~~~~~~~~~~ common/riscv_addrenv_kstack.c:68:34: note: each undeclared identifier is reported only once for each function it appears in make[1]: *** [Makefile:142: riscv_addrenv_kstack.o] Error 1 make[1]: Target 'libkarch.a' not remade because of errors. make: *** [tools/LibTargets.mk:59: arch/risc-v/src/libkarch.a] Error 2 make: Target 'all' not remade because of errors. Signed-off-by: v-tangmeng <v-tangmeng@xiaomi.com> | 2 个月前 | |
arch/riscv: use UP_DSB, UP_DMB, UP_ISB as barrier standard API Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com> | 2 个月前 | |
fix the compilation error caused by 'DEBUGASSERT' error: implicit declaration of function 'DEBUGASSERT' [-Werror=implicit-function-declaration] Signed-off-by: v-tangmeng <v-tangmeng@xiaomi.com> | 2 个月前 | |
group:move addrenv to group struct addrenv is for task group so move it to group Signed-off-by: anjiahao <anjiahao@xiaomi.com> | 2 个月前 | |
arch/riscv: use UP_DSB, UP_DMB, UP_ISB as barrier standard API Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
arm: skip backtrace asan check Signed-off-by: yinshengkai <yinshengkai@xiaomi.com> | 2 个月前 | |
arch/init: call up_color_intstack before up_irq_enable Make sure interrupt stack is colored before IRQ is enabled. Currently, after calling irq_initialize in nx_start to enable interrupts, there is still a period of execution path before the interrupt stack is colored. Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com> | 2 个月前 | |
risc-v: Add support for RISC-V shadow stack (Zicfiss) extension Add comprehensive support for RISC-V Zicfiss (Control Flow Integrity Shadow Stack) extension to protect against return-oriented programming (ROP) attacks and other control flow hijacking attempts. * Added Kconfig options for Zicfiss ISA extension and shadow stack support * Defined shadow stack pointer CSR (CSR_SSP) in csr.h header * Extended IRQ context to include shadow stack pointer register * Added shadow stack allocation and management in stack creation/release * Implemented shadow stack context save/restore in exception handling * Updated toolchain configuration to enable Zicfiss extension * Modified memory layout to accommodate shadow stacks alongside regular stacks * Added shadow stack initialization for idle tasks and SMP support Signed-off-by: Huang Qi <huangqi3@xiaomi.com> | 2 个月前 | |
risc-v: Add support for RISC-V shadow stack (Zicfiss) extension Add comprehensive support for RISC-V Zicfiss (Control Flow Integrity Shadow Stack) extension to protect against return-oriented programming (ROP) attacks and other control flow hijacking attempts. * Added Kconfig options for Zicfiss ISA extension and shadow stack support * Defined shadow stack pointer CSR (CSR_SSP) in csr.h header * Extended IRQ context to include shadow stack pointer register * Added shadow stack allocation and management in stack creation/release * Implemented shadow stack context save/restore in exception handling * Updated toolchain configuration to enable Zicfiss extension * Modified memory layout to accommodate shadow stacks alongside regular stacks * Added shadow stack initialization for idle tasks and SMP support Signed-off-by: Huang Qi <huangqi3@xiaomi.com> | 2 个月前 | |
arch/risc-v: Decouple ARCH_RV_CPUID_MAP and up_cpu_index() Summary: - Separated CPU index functionality from CPU ID mapping configuration - Moved CPU ID mapping functions to new riscv_cpuidmap.c file - Made up_cpu_index() implementation dependent on ARCH_USE_S_MODE - Updated build system to handle new file organization Impact: - Improves code organization by separating concerns between basic CPU index functionality and advanced CPU ID mapping features - Makes CPU index functionality available independently of CPU ID mapping - Reduces conditional compilation complexity in header files - Better aligns with RISC-V architecture modes (M-mode vs S-mode) Testing: GitHub CI and local testing Signed-off-by: Huang Qi <huangqi3@xiaomi.com> | 2 个月前 | |
arch/risc-v: Decouple ARCH_RV_CPUID_MAP and up_cpu_index() Summary: - Separated CPU index functionality from CPU ID mapping configuration - Moved CPU ID mapping functions to new riscv_cpuidmap.c file - Made up_cpu_index() implementation dependent on ARCH_USE_S_MODE - Updated build system to handle new file organization Impact: - Improves code organization by separating concerns between basic CPU index functionality and advanced CPU ID mapping features - Makes CPU index functionality available independently of CPU ID mapping - Reduces conditional compilation complexity in header files - Better aligns with RISC-V architecture modes (M-mode vs S-mode) Testing: GitHub CI and local testing Signed-off-by: Huang Qi <huangqi3@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
riscv_cpustart.c: Fix reading of interrupt status Let's read the interrupt status correctly, by checking for the interrupt source bit instead of assuming no other status bit is set. | 2 个月前 | |
nuttx/atomic: replace atomic_fetch_xxx with atomic_xxx just like zephyr Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com> | 2 个月前 | |
fix compile error Signed-off-by: hujun5 <hujun5@xiaomi.com> | 2 个月前 | |
sched/arch: move suspend/resume scheduler to arch irq handler Move nxsched_suspend_scheduler/nxsched_resume_scheduler from nxsched_switch to arch-specific IRQ handlers. This change: 1. Fixes missing suspend/resume in SMP sched IPI handler (arm_smp_sched_handler calls nxsched_switch_running directly without going through nxsched_switch) 2. Avoids spurious suspend/resume when ISR triggers multiple context switches (e.g., sem_post to tasks A->B->C only records suspend(old)->resume(C), not intermediate transitions) Signed-off-by: ligd <liguiding1@xiaomi.com> | 2 个月前 | |
nuttx/atomic: replace atomic_fetch_xxx with atomic_xxx just like zephyr Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com> | 2 个月前 | |
arch: add signal disabled support in interrupt handling impl When the signal functionality is turned off, there is no need to allocate additional stack space for the signal handling process. Signed-off-by: guoshichao <guoshichao@xiaomi.com> | 2 个月前 | |
sched: unify the thread exit running task behavior. We already split switch_context into nxsched_suspend_scheduler and nxsched_resume_scheduler, when task_exit, set running = NULL for more compatible. The switch context is much more frequency than task_exit, we should prefer decrease the switch_context record time cost. Also the x_doirq xcp.regs save will be more unified. Signed-off-by: wangzhi16 <wangzhi16@xiaomi.com> Signed-off-by: ligd <liguiding1@xiaomi.com> | 2 个月前 | |
sched:use tcb_s inside of task_tcb_s , remove all cast Signed-off-by: anjiahao <anjiahao@xiaomi.com> | 2 个月前 | |
arch: Make STACK_ALIGNMENT consistent with TLS_STACK_ALIGNMENT when CONFIG_TLS_ALIGNED=y Signed-off-by: hujun5 <hujun5@xiaomi.com> | 2 个月前 | |
dns: fix dns failed when ipv4/6 dual stack enable The ipv6 address filled the cache, and the ipv4 address did not have a place to store it, causing the resolution to fail. so if IPV6 has already filled the buffer, rewrite ipv4 DNS results from half of the buffer. Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
arch/risc-v: support backtrace dump during IRQ Adds support for backtrace when the system crashes during IRQ for RISC-V. Tested with SMP, no SMP and no interrupt stack. | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
fs/hostfs: add link, symlink, readlink and lstat support Implemented link(), symlink(), readlink() and lstat() in hostfs. Signed-off-by: zhengyu16 <zhengyu16@xiaomi.com> | 2 个月前 | |
xtensa/esp32s3: Add support for RT-Timer based on Systimer peripheral Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
arch: change all g_interrupt_context to percpu Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
risc-v: Add support for RISC-V shadow stack (Zicfiss) extension Add comprehensive support for RISC-V Zicfiss (Control Flow Integrity Shadow Stack) extension to protect against return-oriented programming (ROP) attacks and other control flow hijacking attempts. * Added Kconfig options for Zicfiss ISA extension and shadow stack support * Defined shadow stack pointer CSR (CSR_SSP) in csr.h header * Extended IRQ context to include shadow stack pointer register * Added shadow stack allocation and management in stack creation/release * Implemented shadow stack context save/restore in exception handling * Updated toolchain configuration to enable Zicfiss extension * Modified memory layout to accommodate shadow stacks alongside regular stacks * Added shadow stack initialization for idle tasks and SMP support Signed-off-by: Huang Qi <huangqi3@xiaomi.com> | 2 个月前 | |
arch/init: call up_color_intstack before up_irq_enable Make sure interrupt stack is colored before IRQ is enabled. Currently, after calling irq_initialize in nx_start to enable interrupts, there is still a period of execution path before the interrupt stack is colored. Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
arch: Make STACK_ALIGNMENT consistent with TLS_STACK_ALIGNMENT when CONFIG_TLS_ALIGNED=y Signed-off-by: hujun5 <hujun5@xiaomi.com> | 2 个月前 | |
Merge remote-tracking branch 'mirtos/master' into dev-upmerge-nuttx-10.1-0507 Signed-off-by: liuhaitao <liuhaitao@xiaomi.com> | 2 个月前 | |
arch/riscv: Remove CONFIG_ARCH_RV_HARTID_BASE offset from riscv_mhartid The function is supposed to return the physical hart ID. It is needed for e.g. external interrupt acknowledgment (see mpfs_plic.c). This offset is moved initially to up_cpu_index (which is also wrong, but less wrong than the current implementation). Finally, a translation between physical <-> logical shall be provided. | 2 个月前 | |
dns: fix dns failed when ipv4/6 dual stack enable The ipv6 address filled the cache, and the ipv4 address did not have a place to store it, causing the resolution to fail. so if IPV6 has already filled the buffer, rewrite ipv4 DNS results from half of the buffer. Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
modifyreg[8|32]: use small lock in modifyreg[8|32] reason: We would like to replace the big lock with a small lock. Signed-off-by: hujun5 <hujun5@xiaomi.com> | 2 个月前 | |
arch/riscv: Remove kmalloc.h for mtime driver. This commit removed kmalloc.h for mtime driver. Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com> | 2 个月前 | |
arch/risc-v: Ensure the timer setting atomicity on 32-bit platforms. This commit guaranteed the timer setting atomicity on 32-bit platforms. Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com> | 2 个月前 | |
up_nputs: fix AddressSanitizer: global-buffer-overflow problem ==2117790==ERROR: AddressSanitizer: global-buffer-overflow on address 0x64d9e3c0 at pc 0x59ac4e16 bp 0xcefe8058 sp 0xcefe8048 READ of size 1 at 0x64d9e3c0 thread T0 #0 0x59ac4e15 in up_nputs sim/up_nputs.c:54 #1 0x59a67e4c in syslog_default_write syslog/syslog_channel.c:220 #2 0x59a67823 in syslog_default_write syslog/syslog_write.c:101 #3 0x59a67f10 in syslog_write syslog/syslog_write.c:153 #4 0x59a651c3 in syslogstream_flush syslog/syslog_stream.c:60 #5 0x59a6564e in syslogstream_addchar syslog/syslog_stream.c:104 #6 0x59a6576f in syslogstream_putc syslog/syslog_stream.c:140 #7 0x5989fc4d in vsprintf_internal stdio/lib_libvsprintf.c:952 #8 0x598a1298 in lib_vsprintf stdio/lib_libvsprintf.c:1379 #9 0x59a64ea4 in nx_vsyslog syslog/vsyslog.c:223 #10 0x598a601a in vsyslog syslog/lib_syslog.c:68 #11 0x59b0e3dc in AIOTJS::logPrintf(int, char const*, ...) src/ajs_log.cpp:45 #12 0x59b03d56 in jse_dump_obj src/jse/quickjs/jse_quickjs.cpp:569 #13 0x59b03ea1 in jse_dump_error1(JSContext*, unsigned long long) src/jse/quickjs/jse_quickjs.cpp:602 #14 0x59b03dd9 in jse_dump_error(JSContext*) src/jse/quickjs/jse_quickjs.cpp:591 #15 0x59bed615 in ferry::DomComponent::callHook(char const*) src/framework/dom/component.cpp:65 #16 0x59bfe0ff in ferry::DomComponent::initialize() src/framework/dom/component.cpp:645 #17 0x59bb141d in dom_create_component(JSContext*, unsigned long long, unsigned long long, unsigned long long) (/home/wangbowen/project/central/vela_miot_bes_m0/bin/audio+0x365c41d) #18 0x59b4c0d3 in AIOTJS::__createComponent(JSContext*, unsigned long long, int, unsigned long long*) (/home/wangbowen/project/central/vela_miot_bes_m0/bin/audio+0x35f70d3) #19 0x5a56ec17 in js_call_c_function quickjs/quickjs.c:16108 Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com> | 2 个月前 | |
riscv_percpu: Replace critical section with irqsave/irqrestore Since the SCRATCH register is used to store the percpu pointer, which should not be accessed by other CPUs, we can replace the critical section with irqsave/irqrestore. Signed-off-by: Huang Qi <huangqi3@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
perf: add noinstrument_function to up_perf_gettime and related functions Add noinstrument_function attribute to up_perf_gettime and its helper functions (like cp15_pmu_rdccr) across all architectures. These functions are called by perf_gettime which is used in the instrument callback path, and must not be instrumented to avoid infinite recursion when CONFIG_ARCH_INSTRUMENT_ALL is enabled. Signed-off-by: yezhonghui <yezhonghui@xiaomi.com> | 2 个月前 | |
perf: add noinstrument_function to up_perf_gettime and related functions Add noinstrument_function attribute to up_perf_gettime and its helper functions (like cp15_pmu_rdccr) across all architectures. These functions are called by perf_gettime which is used in the instrument callback path, and must not be instrumented to avoid infinite recursion when CONFIG_ARCH_INSTRUMENT_ALL is enabled. Signed-off-by: yezhonghui <yezhonghui@xiaomi.com> | 2 个月前 | |
group:move addrenv to group struct addrenv is for task group so move it to group Signed-off-by: anjiahao <anjiahao@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
arch: up_getusrsp change to inline and implement in irq.h Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
nuttx/atomic: replace atomic_fetch_xxx with atomic_xxx just like zephyr Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com> | 2 个月前 | |
driver/usbdev: support userspace to access ep0 Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
Revert "Reduce the size of tcb by four bytes." This reverts commit 893c5e92c28aca338b38a3d85bd232f9a25a5b56. Signed-off-by: wangzhi16 <wangzhi16@xiaomi.com> | 2 个月前 | |
arch: risc-v: Add support for semihosting and hostfs Summary: - This commit adds support for semihosting and hostfs Impact: - None Testing: - Tested with nsh and nsh64 (defconfig will be updated later) Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com> | 2 个月前 | |
arch: set g_running_task to NULL before context restore in sigdeliver For architectures using syscall-based fullcontextrestore (arm_a_r, arm64, risc-v, tricore), the restore goes through irq_dispatch which reads g_running_task->xcp.regs on entry. If g_running_task is not NULL, irq_dispatch overwrites tcb->xcp.regs with the syscall exception frame, causing the syscall to return to the wrong context instead of restoring saved_regs. Set g_running_task = NULL before setting xcp.regs and calling fullcontextrestore, so irq_dispatch allocates a fresh temp stack frame and correctly restores the saved context. Signed-off-by: ligd <liguiding1@xiaomi.com> | 2 个月前 | |
arch/risc-v: support decouple signal related function from arch code Signed-off-by: guoshichao <guoshichao@xiaomi.com> | 2 个月前 | |
arch/risc-v: get wider visibility for arch instruction macros Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
arch: Make STACK_ALIGNMENT consistent with TLS_STACK_ALIGNMENT when CONFIG_TLS_ALIGNED=y Signed-off-by: hujun5 <hujun5@xiaomi.com> | 2 个月前 | |
nuttx/atomic: replace atomic_fetch_xxx with atomic_xxx just like zephyr Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com> | 2 个月前 | |
arch: use nxsched_supend and nxsched_resume directly After unifying suspend and resume, it was found that it was no longer possible to guarantee that both from and to at the call point were valid. This actually changed the semantics of the nxsched_switch_context, so we need to separate them again. We've completely integrated the nxsched_supend and nxsched_resume calls into sched, so arch will no longer call them. Signed-off-by: guoshengyuan1 <guoshengyuan1@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 | |
reginfo: add coredump register offset The reginfo struct is used for both coredump and gdbstub. GDB stub needs information of the register value offset in g/G packet. Coredump needs information of register offset in register field. They are not in same order for some of the architecture, thus we add goffset and coffset in reginfo to describe it. Signed-off-by: xuxingliang <xuxingliang@xiaomi.com> | 2 个月前 | |
assert: unify stack and register dump across platforms Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com> Signed-off-by: chao.an <anchao@xiaomi.com> | 2 个月前 | |
Merge remote-tracking branch 'mirtos/master' into dev-upmerge-nuttx-10.1-0507 Signed-off-by: liuhaitao <liuhaitao@xiaomi.com> | 2 个月前 | |
arch/stack_align: decrease the stack align requirements. Add ttype in up_use_stack API. We can always get tls by tcb if Flat, and through syscall if no aligned, so don't need to make kstack aligned with TLS_STACK_ALIGN. If always stack aligned will very easy to cause memory fragment when long time used. For BMP case, _percpu_size don't have to align with TLS_STACK_ALIGN after this patch, as .percpu.bss stack don't have to TLS_STACK_ALIGN. TLS_ALIGNED depends on BUILD_KERNEL || BUILD_PROTECTED. We can suppose TLS_ALIGNED will never defined in BUILD_FLAT. Signed-off-by: buxiasen <buxiasen@xiaomi.com> | 2 个月前 | |
risc-v: Add RISC-V Zicfilp Control Flow Integrity extension support Add support for the RISC-V Zicfilp (Control Flow Integrity for Indirect Branches) extension to provide hardware-assisted protection against ROP/JOP attacks. * Add ARCH_RV_ISA_ZICFILP Kconfig option for enabling Zicfilp extension * Update toolchain files to add _zicfilp to -march flags * Add conditional lpad instruction in trap vector for CFI landing pad * Include comprehensive documentation covering configuration, limitations, and usage * Support both Makefile and CMake build systems * Note M-mode compatibility limitations and vendor Signed-off-by: Huang Qi <huangqi3@xiaomi.com> | 2 个月前 | |
Merge branch 'master' into vela apache/nuttx commit id: eb27ebba8adfe29644a7b890f86e6f16941921dc Signed-off-by: ligd <liguiding1@xiaomi.com> Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com> | 2 个月前 |
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