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Merged
ub: udma: Intercept unsupported operations. #24177
ChenYutaoAdd on Jun 24
ub: udma: Intercept unsupported operations. #24177
Merged
ChenYutaoAdd on Jun 24
Merged fromeingesch/kernelbr_624_order_typeintoopeneuler/kernelOLK-6.6
Total: 6 files changed+77-18
Mdrivers/ub/urma/hw/udma/udma_ctl.c+1-1
@@ -1365,6 +1365,7 @@ udma_get_kernel_jetty_sq_id_and_buf(struct udma_dev *udma_dev, struct udma_jetty
1365{1365{
1366 int ret;1366 int ret;
1367 1367 
1368+ udma_jetty->sq.jetty_type = UDMA_LOCK_BUFFER_JETTY_TYPE;
1368 ret = alloc_jetty_id(udma_dev, &udma_jetty->sq, base_cfg->id, NULL);1369 ret = alloc_jetty_id(udma_dev, &udma_jetty->sq, base_cfg->id, NULL);
1369 if (ret) {1370 if (ret) {
1370 dev_err(udma_dev->dev, "alloc WQE lock buffer jetty id failed, ret = %d.\n", ret);1371 dev_err(udma_dev->dev, "alloc WQE lock buffer jetty id failed, ret = %d.\n", ret);
@@ -1374,7 +1375,6 @@ udma_get_kernel_jetty_sq_id_and_buf(struct udma_dev *udma_dev, struct udma_jetty
1374 udma_jetty->ubcore_jetty.jetty_id.id = udma_jetty->sq.id;1375 udma_jetty->ubcore_jetty.jetty_id.id = udma_jetty->sq.id;
1375 udma_jetty->ubcore_jetty.jetty_cfg = *base_cfg;1376 udma_jetty->ubcore_jetty.jetty_cfg = *base_cfg;
1376 udma_jetty->jfr = to_udma_jfr(base_cfg->jfr);1377 udma_jetty->jfr = to_udma_jfr(base_cfg->jfr);
1377- udma_jetty->sq.jetty_type = UDMA_LOCK_BUFFER_JETTY_TYPE;
1378 udma_jetty->jetty_addr = (uintptr_t)&udma_jetty->sq;1378 udma_jetty->jetty_addr = (uintptr_t)&udma_jetty->sq;
1379 ret = udma_get_from_kernel_sq_lock_buf(udma_dev, &udma_jetty->sq, base_cfg, buf_idx);1379 ret = udma_get_from_kernel_sq_lock_buf(udma_dev, &udma_jetty->sq, base_cfg, buf_idx);
1380 if (ret) {1380 if (ret) {
Mdrivers/ub/urma/hw/udma/udma_jetty.c+54-1
@@ -140,7 +140,7 @@ static void udma_init_jettyc(struct udma_dev *dev, struct ubcore_jetty_cfg *cfg,
140 140 
141 ctx->state = JETTY_READY;141 ctx->state = JETTY_READY;
142 ctx->jfs_mode = JETTY;142 ctx->jfs_mode = JETTY;
143- ctx->type = to_udma_type(cfg->trans_mode, cfg->flag.bs.order_type);143+ ctx->type = udma_get_type(cfg->trans_mode, cfg->flag.bs.order_type);
144 ctx->sl = dev->udma_sl[UDMA_DEFAULT_SL_NUM];144 ctx->sl = dev->udma_sl[UDMA_DEFAULT_SL_NUM];
145 if (ctx->type == JETTY_RM || ctx->type == JETTY_RC) {145 if (ctx->type == JETTY_RM || ctx->type == JETTY_RC) {
146 ctx->sl = dev->priority_info[cfg->priority].SL;146 ctx->sl = dev->priority_info[cfg->priority].SL;
@@ -1595,6 +1595,10 @@ struct ubcore_tjetty *udma_import_jetty_ex(struct ubcore_device *ub_dev,
1595 return ERR_PTR(-EINVAL);1595 return ERR_PTR(-EINVAL);
1596 }1596 }
1597 1597 
1598+ ret = udma_get_tp_type_available(udma_dev, cfg);
1599+ if (ret)
1600+ return ERR_PTR(ret);
1601+ 
1598 ret = udma_check_jetty_grp_info(cfg, udma_dev);1602 ret = udma_check_jetty_grp_info(cfg, udma_dev);
1599 if (ret)1603 if (ret)
1600 return ERR_PTR(ret);1604 return ERR_PTR(ret);
@@ -2029,3 +2033,52 @@ uint32_t udma_get_ta_timeout(uint8_t gear)
2029 2033 
2030 return (gear < ARRAY_SIZE(timeout_table)) ? timeout_table[gear] : UDMA_TA_TIMEOUT_64000MS;2034 return (gear < ARRAY_SIZE(timeout_table)) ? timeout_table[gear] : UDMA_TA_TIMEOUT_64000MS;
2031}2035}
2036+ 
2037+uint32_t udma_get_type(uint32_t trans_mode, uint32_t order_type)
2038+{
2039+ switch (trans_mode) {
2040+ case UBCORE_TP_RM:
2041+ return JETTY_RM;
2042+ case UBCORE_TP_RC:
2043+ return JETTY_RC;
2044+ case UBCORE_TP_UM:
2045+ if (order_type == UBCORE_OL)
2046+ return JETTY_RC;
2047+ return JETTY_UM;
2048+ default:
2049+ return JETTY_TYPE_RESERVED;
2050+ }
2051+}
2052+ 
2053+int udma_get_tp_type_available(struct udma_dev *dev, struct ubcore_tjetty_cfg *cfg)
2054+ 
2055+{
2056+ uint32_t tp_ability_bit = 0;
2057+ 
2058+ if (cfg->flag.bs.order_type == UBCORE_OI && cfg->tp_type == UBCORE_RTP) {
2059+ tp_ability_bit = !!(ubase_get_ub_feature() & UBASE_URMA_RTP_ROI);
2060+ } else if (cfg->flag.bs.order_type == UBCORE_OI && cfg->tp_type == UBCORE_CTP) {
2061+ tp_ability_bit = !!(ubase_get_ub_feature() & UBASE_URMA_CTP_ROI);
2062+ } else if (cfg->flag.bs.order_type == UBCORE_OL && cfg->tp_type == UBCORE_CTP) {
2063+ tp_ability_bit = !!(ubase_get_ub_feature() & UBASE_URMA_CTP_ROL);
2064+ } else if (cfg->flag.bs.order_type == UBCORE_OL && cfg->tp_type == UBCORE_RTP) {
2065+ tp_ability_bit = !!(ubase_get_ub_feature() & UBASE_URMA_RTP_ROL);
2066+ } else if (cfg->flag.bs.order_type == UBCORE_NO && cfg->tp_type == UBCORE_CTP) {
2067+ tp_ability_bit = !!(ubase_get_ub_feature() & UBASE_URMA_CTP_UNO);
2068+ } else if (cfg->flag.bs.order_type == UBCORE_NO && cfg->tp_type == UBCORE_UTP) {
2069+ tp_ability_bit = !!(ubase_get_ub_feature() & UBASE_URMA_UTP_UNO);
2070+ } else if (cfg->flag.bs.order_type == UBCORE_OT && cfg->tp_type == UBCORE_CTP) {
2071+ tp_ability_bit = !!(ubase_get_ub_feature() & UBASE_URMA_CTP_ROT);
2072+ } else if (cfg->flag.bs.order_type == UBCORE_OT && cfg->tp_type == UBCORE_RTP) {
2073+ tp_ability_bit = !!(ubase_get_ub_feature() & UBASE_URMA_RTP_ROT);
2074+ } else {
2075+ dev_err(dev->dev, "tp mode is not recognized.\n");
2076+ return -EINVAL;
2077+ }
2078+ 
2079+ if (!tp_ability_bit) {
2080+ dev_err(dev->dev, "tp mode is not supported, tp type: %u .\n", cfg->tp_type);
2081+ return -EINVAL;
2082+ }
2083+ return 0;
2084+}
Mdrivers/ub/urma/hw/udma/udma_jetty.h+2-14
@@ -233,20 +233,6 @@ struct udma_jetty_grp_ctx {
233 uint32_t valid;233 uint32_t valid;
234};234};
235 235 
236-static inline uint32_t to_udma_type(uint32_t trans_mode, uint32_t order_type)
237-{
238- switch (trans_mode) {
239- case UBCORE_TP_RM:
240- return JETTY_RM;
241- case UBCORE_TP_RC:
242- return JETTY_RC;
243- case UBCORE_TP_UM:
244- return order_type == UBCORE_OL ? JETTY_RC : JETTY_UM;
245- default:
246- return JETTY_TYPE_RESERVED;
247- }
248-}
249- 
250static inline struct udma_jetty *to_udma_jetty(struct ubcore_jetty *jetty)236static inline struct udma_jetty *to_udma_jetty(struct ubcore_jetty *jetty)
251{237{
252 return container_of(jetty, struct udma_jetty, ubcore_jetty);238 return container_of(jetty, struct udma_jetty, ubcore_jetty);
@@ -351,4 +337,6 @@ int udma_get_jetty_opt(struct ubcore_jetty *jetty, uint64_t opt, void *buf,
351int udma_set_jetty_opt(struct ubcore_jetty *jetty, uint64_t opt,337int udma_set_jetty_opt(struct ubcore_jetty *jetty, uint64_t opt,
352 void *buf, uint32_t len, struct ubcore_udata *udata);338 void *buf, uint32_t len, struct ubcore_udata *udata);
353void udma_get_jfs_cfg_field(struct ubcore_jfs_cfg *jfs_cfg, uint64_t opt, void *buf);339void udma_get_jfs_cfg_field(struct ubcore_jfs_cfg *jfs_cfg, uint64_t opt, void *buf);
340+uint32_t udma_get_type(uint32_t trans_mode, uint32_t order_type);
341+int udma_get_tp_type_available(struct udma_dev *dev, struct ubcore_tjetty_cfg *cfg);
354#endif /* __UDMA_JETTY_H__ */342#endif /* __UDMA_JETTY_H__ */
Mdrivers/ub/urma/hw/udma/udma_jfr.c+7-1
@@ -324,7 +324,7 @@ static void udma_init_jfrc(struct udma_dev *dev, struct ubcore_jfr_cfg *cfg,
324 }324 }
325 if (cfg->flag.bs.token_policy != UBCORE_TOKEN_NONE)325 if (cfg->flag.bs.token_policy != UBCORE_TOKEN_NONE)
326 ctx->token_en = 1;326 ctx->token_en = 1;
327- ctx->type = to_udma_type(cfg->trans_mode, cfg->flag.bs.order_type);327+ ctx->type = udma_get_type(cfg->trans_mode, cfg->flag.bs.order_type);
328 ctx->token_value = cfg->token_value.token;328 ctx->token_value = cfg->token_value.token;
329 ctx->user_data_l = jfr->jetty_addr;329 ctx->user_data_l = jfr->jetty_addr;
330 ctx->user_data_h = jfr->jetty_addr >> UDMA_USER_DATA_H_OFFSET;330 ctx->user_data_h = jfr->jetty_addr >> UDMA_USER_DATA_H_OFFSET;
@@ -990,7 +990,13 @@ struct ubcore_tjetty *udma_import_jfr_ex(struct ubcore_device *dev,
990 struct ubcore_active_tp_cfg *active_tp_cfg,990 struct ubcore_active_tp_cfg *active_tp_cfg,
991 struct ubcore_udata *udata)991 struct ubcore_udata *udata)
992{992{
993+ struct udma_dev *udma_dev = to_udma_dev(dev);
993 struct udma_target_jetty *udma_tjfr;994 struct udma_target_jetty *udma_tjfr;
995+ int ret;
996+ 
997+ ret = udma_get_tp_type_available(udma_dev, cfg);
998+ if (ret)
999+ return NULL;
994 1000 
995 udma_tjfr = kzalloc(sizeof(*udma_tjfr), GFP_KERNEL);1001 udma_tjfr = kzalloc(sizeof(*udma_tjfr), GFP_KERNEL);
996 if (!udma_tjfr)1002 if (!udma_tjfr)
Mdrivers/ub/urma/hw/udma/udma_jfs.c+1-1
@@ -313,7 +313,7 @@ void udma_init_jfsc(struct udma_dev *dev, struct ubcore_jfs_cfg *cfg,
313 313 
314 ctx->state = JETTY_READY;314 ctx->state = JETTY_READY;
315 ctx->jfs_mode = JFS;315 ctx->jfs_mode = JFS;
316- ctx->type = to_udma_type(cfg->trans_mode, cfg->flag.bs.order_type);316+ ctx->type = udma_get_type(cfg->trans_mode, cfg->flag.bs.order_type);
317 ctx->sl = dev->udma_sl[UDMA_DEFAULT_SL_NUM];317 ctx->sl = dev->udma_sl[UDMA_DEFAULT_SL_NUM];
318 if (ctx->type == JETTY_RM) {318 if (ctx->type == JETTY_RM) {
319 ctx->sl = dev->priority_info[cfg->priority].SL;319 ctx->sl = dev->priority_info[cfg->priority].SL;
Mdrivers/ub/urma/hw/udma/udma_main.c+12-0
@@ -164,6 +164,18 @@ static void udma_set_dev_caps(struct ubcore_device_attr *attr, struct udma_dev *
164 attr->dev_cap.feature.bs.ipourma_en = udma_dev->caps.ipourma_en;164 attr->dev_cap.feature.bs.ipourma_en = udma_dev->caps.ipourma_en;
165 attr->dev_cap.feature.bs.ctp_en = udma_dev->caps.ctp_en;165 attr->dev_cap.feature.bs.ctp_en = udma_dev->caps.ctp_en;
166 attr->dev_cap.feature.bs.uboe = !ubase_adev_ubl_supported(udma_dev->comdev.adev);166 attr->dev_cap.feature.bs.uboe = !ubase_adev_ubl_supported(udma_dev->comdev.adev);
167+ attr->dev_cap.rm_tp_cap.bs.rtp = (ubase_get_ub_feature() &
168+ UBASE_URMA_RTP_ROI) ? 1 : 0;
169+ attr->dev_cap.rm_tp_cap.bs.ctp = (ubase_get_ub_feature() &
170+ UBASE_URMA_CTP_ROI) ? 1 : 0;
171+ attr->dev_cap.rc_tp_cap.bs.ctp = (ubase_get_ub_feature() &
172+ UBASE_URMA_CTP_ROL) ? 1 : 0;
173+ attr->dev_cap.rc_tp_cap.bs.rtp = (ubase_get_ub_feature() &
174+ UBASE_URMA_RTP_ROL) ? 1 : 0;
175+ attr->dev_cap.um_tp_cap.bs.ctp = (ubase_get_ub_feature() &
176+ UBASE_URMA_CTP_UNO) ? 1 : 0;
177+ attr->dev_cap.um_tp_cap.bs.utp = (ubase_get_ub_feature() &
178+ UBASE_URMA_UTP_UNO) ? 1 : 0;
167}179}
168 180 
169static int udma_query_device_attr(struct ubcore_device *dev,181static int udma_query_device_attr(struct ubcore_device *dev,