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dt-bindings: cleanup DTS example whitespaces The DTS code coding style expects spaces around '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #display/msm Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230702182308.7583-1-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org> | 3 年前 | |
Documentation: Add documentation for APM X-Gene SoC PMU DTS binding Driver providing perf backend for the SoC-wide PMU hardware found in APM X-Gene SoCs. Signed-off-by: Tai Nguyen <ttnguyen@apm.com> Acked-by: Rob Herring <robh@kernel.org> | 9 年前 | |
dt-bindings: perf: Convert Arm CCN to DT schema Convert the Arm CCN performance monitors binding to DT schema format. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/20220613145554.3727354-1-robh@kernel.org | 4 年前 | |
dt-bindings: perf: arm-cmn: Add CMN-650 and CMN-700 If you were to guess from the product names that CMN-650 and CMN-700 are the next two evolutionary steps of Arm's enterprise-level interconnect following on from CMN-600, you'd be pleasantly correct. Add them to the DT binding. CC: devicetree@vger.kernel.org Signed-off-by: Robin Murphy <robin.murphy@arm.com> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Link: https://lore.kernel.org/r/9b4dc0c82c91adff62b6f92eec5f61fb25b9db87.1650320598.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org> | 4 年前 | |
dt-bindings: Drop type from 'cpus' property 'cpus' is a common property, and it is now defined in dtschema schemas, so drop the type references in the tree. Acked-by: Suzuki K Poulose <suzuki.poulse@arm.com> Acked-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20221111212857.4104308-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> | 3 年前 | |
dt-bindings: Add Arm SMMUv3 PMCG binding Add binding for the Arm SMMUv3 PMU. Each node represents a PMCG, and is placed as a sibling node of the SMMU. Although the PMCGs registers may be within the SMMU MMIO region, they are separate devices, and there can be multiple PMCG devices for each SMMU (for example one for the TCU and one for each TBU). Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/20211117144844.241072-2-jean-philippe@linaro.org Signed-off-by: Will Deacon <will@kernel.org> | 4 年前 | |
dt-bindings: perf: fsl-imx-ddr: Add i.MX93 compatible i.MX93 ddr pmu shares the same device node format as i.MX8. This will add a compatible for i.MX93 and modify the title. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Link: https://lore.kernel.org/r/20230418102910.2065651-2-xu.yang_2@nxp.com Signed-off-by: Will Deacon <will@kernel.org> | 3 年前 | |
iommu/ummu: Add UMMU-PMU devicetree file ubmmu driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ID40QK ----------------------------------------------------------- This patch add ummu-pmu devicetree file Signed-off-by: Lizhi He Wu <helizhi1@huawei.com> Signed-off-by: Liming An <anliming1@h-partners.com> | 8 个月前 | |
dt-bindings: perf: marvell: cn10k ddr performance monitor Add binding documentation for the Marvell CN10k DDR performance monitor unit. Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220211045346.17894-2-bbhushan2@marvell.com Signed-off-by: Will Deacon <will@kernel.org> | 4 年前 | |
dt-bindings: perf: Add YAML schemas for Marvell CN10K LLC-TAD pmu bindings Add device tree bindings for Last-level-cache Tag-and-data (LLC-TAD) unit PMU for Marvell CN10K SoCs. Signed-off-by: Bhaskara Budiredla <bbudiredla@marvell.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211115043506.6679-3-bbudiredla@marvell.com Signed-off-by: Will Deacon <will@kernel.org> | 4 年前 | |
dt-bindings: perf: riscv,pmu: fix property dependencies Seemingly I mis-implemented the dependencies here. The OpenSBI docs only point out that the "riscv,event-to-mhpmcounters property is mandatory if riscv,event-to-mhpmevent is present". It never claims that riscv,event-to-mhpmcounters requires riscv,event-to-mhpmevent. Drop the dependency of riscv,event-to-mhpmcounters on riscv,event-to-mhpmevent. Fixes: 7e38085d9c59 ("dt-bindings: riscv: add SBI PMU event mappings") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20230404-tractor-confusing-8852e552539a@spud Signed-off-by: Rob Herring <robh@kernel.org> | 3 年前 | |
dt-bindings: arm: spe-pmu: convert to DT schema Convert the Arm Statisical Profiling Extension (SPE) binding to DT schema. Not much to see here, basically just the announcement that SPE is integrated on the system level and where the IRQ is routed to. Move it into the more suitable perf/ directory on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220506140533.3566431-3-andre.przywara@arm.com | 4 年前 |
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