| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
[Backport][BOLT][AArch64] Fix ADR relaxation (#71835) Currently we have an optimization that if the ADR points to the same function we might skip it's relaxation. But it doesn't take into account that BF might be split, in such situation we still need to relax it. And just in case also relax if the initial BF size is >= 1MB. Fixes #71822 | 10 个月前 | |
[Backport][BOLT] Return proper minimal alignment from BF (#67707) Currently minimal alignment of function is hardcoded to 2 bytes. Add 2 more cases: 1. In case BF is data in code return the alignment of CI as minimal alignment 2. For aarch64 and riscv platforms return the minimal value of 4 (added test for aarch64) Otherwise fallback to returning the 2 as it previously was. | 10 个月前 | |
[BOLT][NFC] Replace anonymous namespace functions with static Follow LLVM Coding Standards guideline on using anonymous namespaces (https://llvm.org/docs/CodingStandards.html#anonymous-namespaces) and use static modifier for function definitions. Reviewed By: #bolt, maksfb Differential Revision: https://reviews.llvm.org/D143124 | 3 年前 | |
[BOLT] Remove redundant dumps in AsmDump Dumping jump table and tail call fdata is covered by subsequent iteration over successors. Reviewed By: #bolt, maksfb Differential Revision: https://reviews.llvm.org/D149799 | 3 年前 | |
[BOLT] Add -dump-cg option to dump call graph Reviewed By: #bolt, rafauler Differential Revision: https://reviews.llvm.org/D153994 | 2 年前 | |
Add Om for Kunpeng Opts | 6 个月前 | |
[BOLT] CMOVConversion pass Convert simple hammocks into cmov based on misprediction rate. Test Plan: - Assembly test: cmov-conversion.s - Testing on a binary: # Bootstrap clang with -x86-cmov-converter-force-all and -Wl,--emit-relocs (Release build) # Collect perf.data: - clang++ <opts> bolt/lib/Core/BinaryFunction.cpp -E > bf.cpp - perf record -e cycles:u -j any,u -- clang-15 bf.cpp -O2 -std=c++14 -c -o bf.o # Optimize clang-15 with and w/o -cmov-conversion: - llvm-bolt clang-15 -p perf.data -o clang-15.bolt - llvm-bolt clang-15 -p perf.data -cmov-conversion -o clang-15.bolt.cmovconv # Run perf experiment: - test: clang-15.bolt.cmovconv, - control: clang-15.bolt, - workload (clang options): bf.cpp -O2 -std=c++14 -c -o bf.o Results: task-clock [delta: -360.21 ± 356.75, delta(%): -1.7760 ± 1.7589, p-value: 0.047951, balance: -6] instructions [delta: 44061118 ± 13246382, delta(%): 0.0690 ± 0.0207, p-value: 0.000001, balance: 50] icache-misses [delta: -5534468 ± 2779620, delta(%): -0.4331 ± 0.2175, p-value: 0.028014, balance: -28] branch-misses [delta: -1624270 ± 1113244, delta(%): -0.3456 ± 0.2368, p-value: 0.030300, balance: -22] Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D120177 | 4 年前 | |
[BOLT] Port from llvm-bolt repo [Part 4] Co-authored-by: rfwang07<wangrufeng5@huawei.com> Co-authored-by: eastb233<xiezhiheng@huawei.com> | 5 个月前 | |
[BOLT] Unifying implementations of ext-tsp After BOLT's merge to LLVM, there are two (almost identical) versions of the code layout algorithm. The diff unifies the implementations by keeping the one in LLVM. There are mild changes in the resulting block orders. I tested the changes extensively both on the clang binary and on prod services. Didn't see stat sig differences on average. Reviewed By: Amir Differential Revision: https://reviews.llvm.org/D129895 | 3 年前 | |
[BOLT][NFC] Replace anonymous namespace functions with static Follow LLVM Coding Standards guideline on using anonymous namespaces (https://llvm.org/docs/CodingStandards.html#anonymous-namespaces) and use static modifier for function definitions. Reviewed By: #bolt, maksfb Differential Revision: https://reviews.llvm.org/D143124 | 3 年前 | |
[BOLT][NFC] Fix file-description comments Summary: Fix comments at the start of source files. (cherry picked from FBD33274597) | 4 年前 | |
[BOLT][NFC] Use std::optional in MCPlusBuilder Reviewed By: maksfb, #bolt Differential Revision: https://reviews.llvm.org/D139260 | 3 年前 | |
[BOLT] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716 | 3 年前 | |
[BOLT] Port from llvm-bolt repo [Part 4] Co-authored-by: rfwang07<wangrufeng5@huawei.com> Co-authored-by: eastb233<xiezhiheng@huawei.com> | 5 个月前 | |
[BOLT] Add minimal RISC-V 64-bit support Just enough features are implemented to process a simple "hello world" executable and produce something that still runs (including libc calls). This was mainly a matter of implementing support for various relocations. Currently, the following are handled: - R_RISCV_JAL - R_RISCV_CALL - R_RISCV_CALL_PLT - R_RISCV_BRANCH - R_RISCV_RVC_BRANCH - R_RISCV_RVC_JUMP - R_RISCV_GOT_HI20 - R_RISCV_PCREL_HI20 - R_RISCV_PCREL_LO12_I - R_RISCV_RELAX - R_RISCV_NONE Executables linked with linker relaxation will probably fail to be processed. BOLT relocates .text to a high address while leaving .plt at its original (low) address. This causes PC-relative PLT calls that were relaxed to a JAL to not fit their offset in an I-immediate anymore. This is something that will be addressed in a later patch. Changes to the BOLT core are relatively minor. Two things were tricky to implement and needed slightly larger changes. I'll explain those below. The R_RISCV_CALL(_PLT) relocation is put on the first instruction of a AUIPC/JALR pair, the second does not get any relocation (unlike other PCREL pairs). This causes issues with the combinations of the way BOLT processes binaries and the RISC-V MC-layer handles relocations: - BOLT reassembles instructions one by one and since the JALR doesn't have a relocation, it simply gets copied without modification; - Even though the MC-layer handles R_RISCV_CALL properly (adjusts both the AUIPC and the JALR), it assumes the immediates of both instructions are 0 (to be able to or-in a new value). This will most likely not be the case for the JALR that got copied over. To handle this difficulty without resorting to RISC-V-specific hacks in the BOLT core, a new binary pass was added that searches for AUIPC/JALR pairs and zeroes-out the immediate of the JALR. A second difficulty was supporting ABS symbols. As far as I can tell, ABS symbols were not handled at all, causing __global_pointer$ to break. RewriteInstance::analyzeRelocation was updated to handle these generically. Tests are provided for all supported relocations. Note that in order to test the correct handling of PLT entries, an ELF file produced by GCC had to be used. While I tried to strip the YAML representation, it's still quite large. Any suggestions on how to improve this would be appreciated. Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D145687 | 3 年前 | |
[BOLT][AArch64] add lock to FixRelaxations pass Since the pass is multithreaded, BC.Ctx must be protected. Otherwise we get crashes when processing. Reviewed by: yota9 Differential Revision: https://reviews.llvm.org/D141465 | 3 年前 | |
[BOLT][NFC] Use llvm::is_contained Apply the replacement throughout BOLT. Reviewed By: #bolt, rafauler Differential Revision: https://reviews.llvm.org/D145464 | 3 年前 | |
[BOLT][NFC] Use llvm::reverse Use llvm::reverse instead of for (auto I = rbegin(), E = rend(); I != E; ++I) Reviewed By: #bolt, rafauler Differential Revision: https://reviews.llvm.org/D140516 | 3 年前 | |
[BOLT][NFC] Use range-based STL wrappers Replace std:: algorithms taking begin/end iterators with llvm:: counterparts accepting ranges. Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D128154 | 3 年前 | |
[BOLT][NFC] Use range-based STL wrappers Replace std:: algorithms taking begin/end iterators with llvm:: counterparts accepting ranges. Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D128154 | 3 年前 | |
Ensure newlines at the end of files (NFC) | 3 年前 | |
[BOLT][NFC] Rename icf-dfs option variable to ICFUseDFS Rename to avoid collision with profile-use-dfs. Differential Revision: https://reviews.llvm.org/D155513 | 2 年前 | |
Add Om for Kunpeng Opts | 6 个月前 | |
Add Om for Kunpeng Opts | 6 个月前 | |
[BOLT] Add option instrumentation-max-size for bump allocator (#174716) While the current max memory size is sufficient for most binaries, a few binaries may encouter insufficient allocated memory space. Allow specify the max memory size of the instrumentation bump allocator. | 6 个月前 | |
[BOLT][NFC] Fix braces usage in Passes Summary: Refactor bolt/*/Passes to follow the braces rule for if/else/loop from [LLVM Coding Standards](https://llvm.org/docs/CodingStandards.html). (cherry picked from FBD33344642) | 4 年前 | |
[BOLT][NFC] Fix file-description comments Summary: Fix comments at the start of source files. (cherry picked from FBD33274597) | 4 年前 | |
[Backport][BOLT] Return proper minimal alignment from BF (#67707) Currently minimal alignment of function is hardcoded to 2 bytes. Add 2 more cases: 1. In case BF is data in code return the alignment of CI as minimal alignment 2. For aarch64 and riscv platforms return the minimal value of 4 (added test for aarch64) Otherwise fallback to returning the 2 as it previously was. | 10 个月前 | |
[BOLT] Add randomN split strategy This adds a strategy to split functions into a random number of fragments at randomly chosen split points. Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D130647 | 3 年前 | |
Add Om for Kunpeng Opts | 6 个月前 | |
[BOLT] Replace uses of layout with basic block list As we are moving towards support for multiple fragments, loops that iterate over all basic blocks of a function, but do not depend on the order of basic blocks in the final layout, should iterate over binary functions directly, rather than the layout. Eventually, all loops using the layout list should either iterate over the function, or be aware of multiple layouts. This patch replaces references to binary function's block layout with the binary function itself where only little code changes are necessary. Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D129585 | 3 年前 | |
[BOLT][AArch64] Don't change layout in PatchEntries (#71278) Due to LongJmp pass that is executed before PatchEntries we can't ignore the function here since it would change pre-calculated output layout. The test reloc-26 relied on the wrong behavior, rewritten to unittest. This is also attemp to fix #70771 | 6 个月前 | |
[BOLT][NFC] Use range-based STL wrappers Replace std:: algorithms taking begin/end iterators with llvm:: counterparts accepting ranges. Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D128154 | 3 年前 | |
[bolt] Remove unneeded cl::ZeroOrMore for cl::opt options | 4 年前 | |
[Backport][BOLT] BL/BH are considered aliases in regreassign The relationship of X86 registers is shown in the diagram. BL and BH do not have a direct alias relationship. However, if the BH register cannot be swapped, then the BX/EBX/RBX registers cannot be swapped as well, which means that BL register also cannot be swapped. Therefore, in the presence of BX/EBX/RBX registers, BL and BH have an alias relationship. ┌────────────────┐ │ RBX │ ├────┬───────────┤ │ │ EBX │ ├────┴──┬────────┤ │ │ BX │ ├───────┼───┬────┤ │ │BH │BL │ └───────┴───┴────┘ Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D155098 | 10 个月前 | |
[Backport][CodeLayout] Refactor std::vector uses, namespace, and EdgeCountT. NFC * Place types and functions in the llvm::codelayout namespace * Change EdgeCountT from pair<pair<uint64_t, uint64_t>, uint64_t> to a struct and utilize structured bindings. It is not conventional to use the "T" suffix for structure types. * Remove a redundant copy in ChainT::merge. * Change {ExtTSPImpl,CDSortImpl}::run to use return value instead of an output parameter * Rename applyCDSLayout to computeCacheDirectedLayout: (a) avoid rare abbreviation "CDS" (cache-directed sort) (b) "compute" is more conventional for the specific use case * Change the parameter types from std::vector to ArrayRef so that SmallVector arguments can be used. * Similarly, rename applyExtTspLayout to computeExtTspLayout. Reviewed By: Amir Differential Revision: https://reviews.llvm.org/D159526 | 10 个月前 | |
[Backport][BOLT] Fix a bug related to iterators in ReorderData pass If Itr is the last element and then std::next(Itr) will be Range.end(), so that the statement std::next(Itr)->second is a UB. Reviewed By: yota9, maksfb Differential Revision: https://reviews.llvm.org/D159177 | 10 个月前 | |
Add Om for Kunpeng Opts | 6 个月前 | |
[BOLT] Use MCInstPrinter in createRetpolineFunctionTag Make retpoline functions invariant of X86 register numbers. retpoline-synthetic.test is known to fail NFC testing due to shifting register numbers. Use canonical register names instead of tablegen numbers. Before: __retpoline_r51_ __retpoline_mem_r58+DATAat0x200fe8 __retpoline_mem_r51+0 __retpoline_mem_r132+0+8*53 After: __retpoline_%rax_ __retpoline_mem_%rip+DATAat0x200fe8 __retpoline_mem_%rax+0 __retpoline_mem_%r12+0+8*%rbx Test Plan: - Revert 67bd3c58c0c7389e39c5a2f4d3b1a30459ccf5b7 that touches X86RegisterInfo.td. - retpoline-synthetic.test passes in NFC mode with this diff, fails without it. Reviewed By: #bolt, rafauler Differential Revision: https://reviews.llvm.org/D150138 | 3 年前 | |
[Backport][BOLT] Rename isLoad/isStore to mayLoad/mayStore As discussed in D159266, for some instructions it's impossible to know statically if they will load/store (e.g., predicated instructions). Therefore, mayLoad/mayStore are more appropriate names. | 10 个月前 | |
Add Om for Kunpeng Opts | 6 个月前 | |
[BOLT] Fix AND evaluation bug in shrink wrapping Fix a bug where shrink-wrapping would use wrong stack offsets because the stack was being aligned with an AND instruction, hence, making its true offsets only available during runtime (we can't statically determine where are the stack elements and we must give up on this case). Reviewed By: Amir Differential Revision: https://reviews.llvm.org/D126110 | 4 年前 | |
Add missing MC includes in bolt/ Changes needed after ef736a1c39f27ef4 that removes some implicit dependencies from MrCV headers. | 4 年前 | |
[BOLT][NFC] Fix file-description comments Summary: Fix comments at the start of source files. (cherry picked from FBD33274597) | 4 年前 | |
[BOLT][NFC] Fix braces usage in Passes Summary: Refactor bolt/*/Passes to follow the braces rule for if/else/loop from [LLVM Coding Standards](https://llvm.org/docs/CodingStandards.html). (cherry picked from FBD33344642) | 4 年前 | |
[BOLT] Port from llvm-bolt repo [Part 4] Co-authored-by: rfwang07<wangrufeng5@huawei.com> Co-authored-by: eastb233<xiezhiheng@huawei.com> | 5 个月前 | |
[Backport][BOLT] Rename isLoad/isStore to mayLoad/mayStore As discussed in D159266, for some instructions it's impossible to know statically if they will load/store (e.g., predicated instructions). Therefore, mayLoad/mayStore are more appropriate names. | 10 个月前 | |
[Backport][BOLT] Fix deadloop bug in taildup The intent is clearly to push the tail rather than current BB. Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D159289 | 10 个月前 | |
[BOLT] Add function layout class This patch adds a dedicated class to keep track of each function's layout. It also lays the groundwork for splitting functions into multiple fragments (as opposed to a strict hot/cold split). Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D129518 | 3 年前 | |
[Backport][BOLT][NFC] Extract a function for dump MCInst (#67225) In GDB debugging, obtaining the assembly representation of MCInst is more intuitive. | 10 个月前 | |
[BOLT] Add pass to fix ambiguous memory references This adds a round of checks to memory references, looking for incorrect references to jump table objects. Fix them by replacing the jump table reference with another object reference + offset. This solves bugs related to regular data references in code accidentally being bound to a jump table, and this reference being updated to a new (incorrect) location because we moved this jump table. Fixes #55004 Reviewed By: #bolt, maksfb Differential Revision: https://reviews.llvm.org/D134098 | 3 年前 | |
Add Om for Kunpeng Opts | 6 个月前 |
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