PPhilippe Mathieu-Daudétarget/hexagon: Use generic cpu_list()
| 文件 | 最后提交记录 | 最后更新时间 |
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target/hexagon/idef-parser/prepare: use env to invoke bash This file is the only one involved in the compilation process which still uses the /bin/bash path. Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-ID: <20231123211506.636533-1-sam@rfc1149.net> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 2 年前 | |
target/hexagon: fix some occurrences of -Wshadow=local Of the changes in this commit, the changes in HELPER(commit_hvx_stores)() are less obvious. They are required because of some macro invocations like SCATTER_OP_WRITE_TO_MEM(). e.g.: In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows a previous local [-Werror=shadow=compatible-local] 205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ | ^ ../target/hexagon/op_helper.c:157:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 157 | SCATTER_OP_WRITE_TO_MEM(uint16_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here 135 | int i; | ^ In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows a previous local [-Werror=shadow=compatible-local] 204 | uintptr_t ra = GETPC(); \ | ^~ ../target/hexagon/op_helper.c:160:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 160 | SCATTER_OP_WRITE_TO_MEM(uint32_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here 134 | uintptr_t ra = GETPC(); | ^~ Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231008220945.983643-3-bcain@quicinc.com> | 2 年前 | |
target/hexagon: fix some occurrences of -Wshadow=local Of the changes in this commit, the changes in HELPER(commit_hvx_stores)() are less obvious. They are required because of some macro invocations like SCATTER_OP_WRITE_TO_MEM(). e.g.: In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows a previous local [-Werror=shadow=compatible-local] 205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ | ^ ../target/hexagon/op_helper.c:157:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 157 | SCATTER_OP_WRITE_TO_MEM(uint16_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here 135 | int i; | ^ In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows a previous local [-Werror=shadow=compatible-local] 204 | uintptr_t ra = GETPC(); \ | ^~ ../target/hexagon/op_helper.c:160:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 160 | SCATTER_OP_WRITE_TO_MEM(uint32_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here 134 | uintptr_t ra = GETPC(); | ^~ Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231008220945.983643-3-bcain@quicinc.com> | 2 年前 | |
tcg: Rename cpu_env to tcg_env Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 2 年前 | |
Hexagon (target/hexagon) Short-circuit packet register writes In certain cases, we can avoid the overhead of writing to hex_new_value and write directly to hex_gpr. We add need_commit field to DisasContext indicating if the end-of-packet commit is needed. If it is not needed, get_result_gpr() and get_result_gpr_pair() can return hex_gpr. We pass the ctx->need_commit to helpers when needed. Finally, we can early-exit from gen_reg_writes during packet commit. There are a few instructions whose semantics write to the result before reading all the inputs. Therefore, the idef-parser generated code is incompatible with short-circuit. We tell idef-parser to skip them. For debugging purposes, we add a cpu property to turn off short-circuit. When the short-circuit property is false, we skip the analysis and force the end-of-packet commit. Here's a simple example of the TCG generated for 0x004000b4: 0x7800c020 { R0 = #0x1 } BEFORE: ---- 004000b4 movi_i32 new_r0,$0x1 mov_i32 r0,new_r0 AFTER: ---- 004000b4 movi_i32 r0,$0x1 This patch reintroduces a use of check_for_attrib, so we remove the G_GNUC_UNUSED added earlier in this series. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com> | 3 年前 | |
Hexagon (target/hexagon) CABAC decode bin The following instruction is added S2_cabacdecbin Rdd32=decbin(Rss32,Rtt32) Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-27-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
Clean up decorations and whitespace around header guards Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-5-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 年前 | |
Hexagon (target/hexagon) Mark registers as read during packet analysis Have gen_analyze_funcs mark the registers that are read by the instruction. We also mark the implicit reads using instruction attributes. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-11-tsimpson@quicinc.com> | 3 年前 | |
target/hexagon: Remove NB_MMU_MODES define Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230306175230.7110-7-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 年前 | |
target: Move ArchCPUClass definition to 'cpu.h' The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each ArchCPUClass type. These forward declarations are sufficient for code in hw/ to use the QOM definitions. No need to expose these structure definitions. Keep each local to their target/ by moving them to the corresponding "cpu.h" header. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-13-philmd@linaro.org> | 2 年前 | |
target/hexagon: Use generic cpu_list() No changes in the output from the following command. [gshan@gshan q]$ ./build/qemu-hexagon -cpu ? Available CPUs: v67 v68 v69 v71 v73 Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231114235628.534334-12-gshan@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 2 年前 | |
target/hexagon: Use generic cpu_list() No changes in the output from the following command. [gshan@gshan q]$ ./build/qemu-hexagon -cpu ? Available CPUs: v67 v68 v69 v71 v73 Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231114235628.534334-12-gshan@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 2 年前 | |
Hexagon (target/hexagon) change variables from int to bool when appropriate Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-8-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
Hexagon (decode): look for pkts with multiple insns at the same slot Each slot in a packet can be assigned to at most one instruction. Although the assembler generally ought to enforce this rule, we better be safe than sorry and also do some check to properly throw an "invalid packet" exception on wrong slot assignments. This should also make it easier to debug possible future errors caused by missing updates to find_iclass_slots() rules in target/hexagon/iclass.c. Co-authored-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <f8b829443523568823d062adf8bf6659bc6d4a3f.1683552984.git.quic_mathbern@quicinc.com> | 3 年前 | |
Hexagon (target/hexagon) instruction/packet decode Take the words from instruction memory and build a packet_t for TCG code generation The following operations are performed Convert the .new encoded offset to the register number of the producer Reorder the packet so .new producer is before consumer Apply constant extenders Separate subinsn's into two instructions Break compare-jumps into two instructions Create instructions for :endloop Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-14-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
Use black code style for python scripts Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230320092533.2859433-3-quic_mliebel@quicinc.com> | 3 年前 | |
hexagon: spelling fixes Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Brian Cain <bcain@quicinc.com> | 2 年前 | |
Hexagon (target/hexagon) properly handle denorm in arch_sf_recip_common The arch_sf_recip_common function was calling float32_getexp which adjusts for denorm, but the we actually need the raw exponent bits. This function is called from 3 instructions sfrecipa sffixupn sffixupd Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-6-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 年前 | |
Hexagon (gdbstub): add HVX support Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Co-authored-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathbern@quicinc.com> | 3 年前 | |
target/hexagon/*.py: clean up used 'toss' and 'numregs' vars Many Hexagon python scripts call hex_common.get_tagregs(), but only one call site use the full reg structure given by this function. To make the code cleaner, let's make get_tagregs() filter out the unused fields (i.e. 'toss' and 'numregs'), properly removed the unused variables at the call sites. The hex_common.bad_register() function is also adjusted to work exclusively with 'regtype' and 'regid' args. For the single call site that does use toss/numregs, we provide an optional parameter to get_tagregs() which will restore the old full behavior. Suggested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <3ffd4ccb972879f57f499705c624e8eaba7f8b52.1684939078.git.quic_mathbern@quicinc.com> | 3 年前 | |
Hexagon HVX (target/hexagon) C preprocessor for decode tree Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> | 4 年前 | |
target/hexagon/*.py: clean up used 'toss' and 'numregs' vars Many Hexagon python scripts call hex_common.get_tagregs(), but only one call site use the full reg structure given by this function. To make the code cleaner, let's make get_tagregs() filter out the unused fields (i.e. 'toss' and 'numregs'), properly removed the unused variables at the call sites. The hex_common.bad_register() function is also adjusted to work exclusively with 'regtype' and 'regid' args. For the single call site that does use toss/numregs, we provide an optional parameter to get_tagregs() which will restore the old full behavior. Suggested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <3ffd4ccb972879f57f499705c624e8eaba7f8b52.1684939078.git.quic_mathbern@quicinc.com> | 3 年前 | |
target/hexagon/*.py: clean up used 'toss' and 'numregs' vars Many Hexagon python scripts call hex_common.get_tagregs(), but only one call site use the full reg structure given by this function. To make the code cleaner, let's make get_tagregs() filter out the unused fields (i.e. 'toss' and 'numregs'), properly removed the unused variables at the call sites. The hex_common.bad_register() function is also adjusted to work exclusively with 'regtype' and 'regid' args. For the single call site that does use toss/numregs, we provide an optional parameter to get_tagregs() which will restore the old full behavior. Suggested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <3ffd4ccb972879f57f499705c624e8eaba7f8b52.1684939078.git.quic_mathbern@quicinc.com> | 3 年前 | |
target/hexagon/*.py: clean up used 'toss' and 'numregs' vars Many Hexagon python scripts call hex_common.get_tagregs(), but only one call site use the full reg structure given by this function. To make the code cleaner, let's make get_tagregs() filter out the unused fields (i.e. 'toss' and 'numregs'), properly removed the unused variables at the call sites. The hex_common.bad_register() function is also adjusted to work exclusively with 'regtype' and 'regid' args. For the single call site that does use toss/numregs, we provide an optional parameter to get_tagregs() which will restore the old full behavior. Suggested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <3ffd4ccb972879f57f499705c624e8eaba7f8b52.1684939078.git.quic_mathbern@quicinc.com> | 3 年前 | |
Use black code style for python scripts Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230320092533.2859433-3-quic_mliebel@quicinc.com> | 3 年前 | |
target/hexagon/*.py: clean up used 'toss' and 'numregs' vars Many Hexagon python scripts call hex_common.get_tagregs(), but only one call site use the full reg structure given by this function. To make the code cleaner, let's make get_tagregs() filter out the unused fields (i.e. 'toss' and 'numregs'), properly removed the unused variables at the call sites. The hex_common.bad_register() function is also adjusted to work exclusively with 'regtype' and 'regid' args. For the single call site that does use toss/numregs, we provide an optional parameter to get_tagregs() which will restore the old full behavior. Suggested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <3ffd4ccb972879f57f499705c624e8eaba7f8b52.1684939078.git.quic_mathbern@quicinc.com> | 3 年前 | |
Use black code style for python scripts Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230320092533.2859433-3-quic_mliebel@quicinc.com> | 3 年前 | |
Use black code style for python scripts Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230320092533.2859433-3-quic_mliebel@quicinc.com> | 3 年前 | |
Hexagon HVX (target/hexagon) semantics generator Add HVX support to the semantics generator Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> | 4 年前 | |
Use black code style for python scripts Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230320092533.2859433-3-quic_mliebel@quicinc.com> | 3 年前 | |
tcg: Rename cpu_env to tcg_env Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 2 年前 | |
Use black code style for python scripts Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230320092533.2859433-3-quic_mliebel@quicinc.com> | 3 年前 | |
tcg: Rename cpu_env to tcg_env Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 2 年前 | |
tcg: Rename cpu_env to tcg_env Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 2 年前 | |
tcg: Rename cpu_env to tcg_env Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 2 年前 | |
Hexagon (target/hexagon) Make special new_value for USR Precursor to moving new_value from the global state to DisasContext USR will need to stay in the global state because some helpers will set it's value Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-17-tsimpson@quicinc.com> | 3 年前 | |
Hexagon (target/hexagon) Move items to DisasContext The following items in the CPUHexagonState are only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. The following items are moved dczero_addr branch_taken this_PC Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-22-tsimpson@quicinc.com> | 3 年前 | |
target/hexagon: Clean up includes This commit was created with scripts/clean-includes. All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Changes to standalone programs dropped, because these intentionally don't use qemu/osdep.h: target/hexagon/gen_dectree_import.c target/hexagon/gen_semantics.c target/hexagon/idef-parser/idef-parser.h target/hexagon/idef-parser/parser-helpers.c target/hexagon/idef-parser/parser-helpers.h Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20230202133830.2152150-14-armbru@redhat.com> | 3 年前 | |
target/hexagon: avoid invalid escape in Python string This is an error in Python 3.12; fix it by using a raw string literal. Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> | 2 年前 | |
target/hexagon: rename aliased register HEX_REG_P3_0 The patch renames the identifier of the 32bit register HEX_REG_P3_0 to HEX_REG_P3_0_ALIASED. This change is to intended to provide some warning that HEX_REG_P3_0 is an aliased register which has multiple representations in CPU state and therefore might require special handling in some contexts. The hope is to prevent accidental misuse of this register e.g the issue reported for the signals tests failure [here][1]. [1]: https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg01102.html Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221229092006.10709-3-quic_mthiyaga@quicinc.com> | 3 年前 | |
Hexagon (iclass): update J4_hintjumpr slot constraints The Hexagon PRM says that "The assembler automatically encodes instructions in the packet in the proper order. In the binary encoding of a packet, the instructions must be ordered from Slot 3 down to Slot 0." Prior to the architecture version v73, the slot constraints from instruction "hintjr" only allowed it to be executed at slot 2. With that in mind, consider the packet: { hintjr(r0) nop nop if (!p0) memd(r1+#0) = r1:0 } To satisfy the ordering rule quoted from the PRM, the assembler would, thus, move one of the nops to the first position, so that it can be assigned to slot 3 and the subsequent hintjr to slot 2. However, since v73, hintjr can be executed at either slot 2 or 3. So there is no need to reorder that packet and the assembler will encode it as is. When QEMU tries to execute it, however, we end up hitting a "misaliged store" exception because both the store and the hintjr will be assigned to store 0, and some functions like slot_is_predicated() expect the decode machinery to assign only one instruction per slot. In particular, the mentioned function will traverse the packet until it finds the first instruction at the desired slot which, for slot 0, will be hintjr. Since hintjr is not predicated, the result is that we try to execute the store regardless of the predicate. And because the predicate is false, we had not previously loaded hex_store_addr[0] or hex_store_width[0]. As a result, the store will decide de width based on trash memory, causing it to be misaligned. Update the slot constraints for hintjr so that QEMU can properly handle such encodings. Note: to avoid similar-but-not-identical issues in the future, we should look for multiple instructions at the same slot during decoding time and throw an invalid packet exception. That will be done in the subsequent commit. Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <0fcd8293642c6324119fbbab44741164bcbd04fb.1673616964.git.quic_mathbern@quicinc.com> | 3 年前 | |
Hexagon (target/hexagon) instruction classes Determine legal VLIW slots for each instruction Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-26-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
Hexagon (target/hexagon) Remove PC from the runtime state Add pc field to Packet structure For helpers that need PC, pass an extra argument Remove slot arg from conditional jump helpers On a trap0, copy pkt->pc into hex_gpr[HEX_REG_PC] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221108162906.3166-6-tsimpson@quicinc.com> | 3 年前 | |
Hexagon (gdbstub): add HVX support Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Co-authored-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathbern@quicinc.com> | 3 年前 | |
target/hexagon: move GETPC() calls to top level helpers As docs/devel/loads-stores.rst states: GETPC() should be used with great care: calling it in other functions that are *not* the top level HELPER(foo) will cause unexpected behavior. Instead, the value of GETPC() should be read from the helper and passed if needed to the functions that the helper calls. Let's fix the GETPC() usage in Hexagon, making sure it's always called from top level helpers and passed down to the places where it's needed. There are a few snippets where that is not currently the case: - probe_store(), which is only called from two helpers, so it's easy to move GETPC() up. - mem_load*() functions, which are also called directly from helpers, but through the MEM_LOAD*() set of macros. Note that this are only used when compiling with --disable-hexagon-idef-parser. In this case, we also take this opportunity to simplify the code, unifying the mem_load*() functions. - HELPER(probe_hvx_stores), when called from another helper, ends up using its own GETPC() expansion instead of the top level caller. Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Message-Id: <2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathbern@quicinc.com>-ne Reviewed-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Message-Id: <20231008220945.983643-2-bcain@quicinc.com> | 2 年前 | |
Merge tag 'pull-hex-20230306' of https://github.com/quic/qemu into staging Hexagon (target/hexagon) update # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmQGzGYACgkQewJE+xLe # RCJfxggAgAY9fqUxKk5FxziMX6sVxx2SiYGU1biABtHyduQvJ43U7In4cnbC65FL # Pn+ZSixPRh51Ij2s9FTzDQ8IUNt/k1W7gCoEC3I0wDbQHdICEIlx30ry68QlUgOa # T6ZDquJkanwFjb7kMnyM4LRBBxLG+OuYvKe1e+nzun0LDlfTS/sHitRlf4AJEBOK # 9h/Bdy81RcWlLzlc5tmD0f9rhtmkkFCTu/TGLt4G6sfn1xZbRdh5N1cFfUShPlQM # qAgj+JgBOQoPKaBhQZnA3Ps9ZEM4+/8KPsr5oGweAcjqD8+kMGCmi2jv+60ES5Uq # EDpn25COw7BVAo6vP/JfBEiZTg+YpA== # =FDSG # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Mar 2023 05:32:22 GMT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20230306' of https://github.com/quic/qemu: Hexagon (target/hexagon) Improve code gen for predicated HVX instructions Hexagon (target/hexagon) Reduce manipulation of slot_cancelled Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair] Hexagon (target/hexagon) Change subtract from zero to change sign Hexagon (tests/tcg/hexagon) Enable HVX tests Hexagon (tests/tcg/hexagon) Remove __builtin from scatter_gather Hexagon (tests/tcg/hexagon) Update preg_alias.c Hexagon (target/hexagon) Analyze packet for HVX Hexagon (target/hexagon) Don't set pkt_has_store_s1 when not needed Hexagon (target/hexagon) Analyze packet before generating TCG Hexagon (target/hexagon) Add overrides for dealloc-return instructions Hexagon (target/hexagon) Add overrides for endloop1/endloop01 Hexagon (target/hexagon) Add overrides for callr Hexagon (target/hexagon) Add overrides for jumpr31 instructions target/hexagon/idef-parser: Remove unused code paths target/hexagon/idef-parser: Elide mov in gen_pred_assign Hexagon (target/hexagon) Restore --disable-hexagon-idef-parser build Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 年前 | |
target/hexagon: fix some occurrences of -Wshadow=local Of the changes in this commit, the changes in HELPER(commit_hvx_stores)() are less obvious. They are required because of some macro invocations like SCATTER_OP_WRITE_TO_MEM(). e.g.: In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows a previous local [-Werror=shadow=compatible-local] 205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ | ^ ../target/hexagon/op_helper.c:157:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 157 | SCATTER_OP_WRITE_TO_MEM(uint16_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here 135 | int i; | ^ In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows a previous local [-Werror=shadow=compatible-local] 204 | uintptr_t ra = GETPC(); \ | ^~ ../target/hexagon/op_helper.c:160:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 160 | SCATTER_OP_WRITE_TO_MEM(uint32_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here 134 | uintptr_t ra = GETPC(); | ^~ Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231008220945.983643-3-bcain@quicinc.com> | 2 年前 | |
target/hexagon: move GETPC() calls to top level helpers As docs/devel/loads-stores.rst states: GETPC() should be used with great care: calling it in other functions that are *not* the top level HELPER(foo) will cause unexpected behavior. Instead, the value of GETPC() should be read from the helper and passed if needed to the functions that the helper calls. Let's fix the GETPC() usage in Hexagon, making sure it's always called from top level helpers and passed down to the places where it's needed. There are a few snippets where that is not currently the case: - probe_store(), which is only called from two helpers, so it's easy to move GETPC() up. - mem_load*() functions, which are also called directly from helpers, but through the MEM_LOAD*() set of macros. Note that this are only used when compiling with --disable-hexagon-idef-parser. In this case, we also take this opportunity to simplify the code, unifying the mem_load*() functions. - HELPER(probe_hvx_stores), when called from another helper, ends up using its own GETPC() expansion instead of the top level caller. Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Message-Id: <2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathbern@quicinc.com>-ne Reviewed-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Message-Id: <20231008220945.983643-2-bcain@quicinc.com> | 2 年前 | |
target/hexagon/opcodes: Add missing varargs cleanup Fix a trivial incorrect usage of variable argument macros detected by Coverity (missing_va_end: va_end was not called for ap). Fixes: Coverity CID 1446720 (VARARGS) Fixes: e3c00c2ed75 ("Hexagon (target/hexagon) opcode data structures") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20210223111253.2831285-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
Hexagon (target/hexagon) opcode data structures Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-24-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
Hexagon (target/hexagon) instruction printing Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-15-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
Hexagon (target/hexagon) instruction printing Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-15-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
Hexagon (target/hexagon) cleanup reg_field_info definition Include size in declaration Remove {0, 0} entry Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-15-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
Hexagon (target/hexagon) cleanup reg_field_info definition Include size in declaration Remove {0, 0} entry Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-15-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
Hexagon (target/hexagon) register fields Declare bitfields within registers such as user status register (USR) Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-12-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 年前 | |
target/hexagon: fix some occurrences of -Wshadow=local Of the changes in this commit, the changes in HELPER(commit_hvx_stores)() are less obvious. They are required because of some macro invocations like SCATTER_OP_WRITE_TO_MEM(). e.g.: In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows a previous local [-Werror=shadow=compatible-local] 205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ | ^ ../target/hexagon/op_helper.c:157:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 157 | SCATTER_OP_WRITE_TO_MEM(uint16_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here 135 | int i; | ^ In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows a previous local [-Werror=shadow=compatible-local] 204 | uintptr_t ra = GETPC(); \ | ^~ ../target/hexagon/op_helper.c:160:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 160 | SCATTER_OP_WRITE_TO_MEM(uint32_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here 134 | uintptr_t ra = GETPC(); | ^~ Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231008220945.983643-3-bcain@quicinc.com> | 2 年前 | |
Hexagon (target/hexagon) Move items to DisasContext The following items in the CPUHexagonState are only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. The following items are moved dczero_addr branch_taken this_PC Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-22-tsimpson@quicinc.com> | 3 年前 |