master

文件	最后提交记录	最后更新时间
tcg-target-con-set.h	tcg/arm: Adjust constraints on qemu_ld/st Always reserve r3 for tlb softmmu lookup. Fix a bug in user-only ALL_QLDST_REGS, in that r14 is clobbered by the BLNE that leads to the misaligned trap. Remove r0+r1 from user-only ALL_QLDST_REGS; I believe these had been reserved for bswap, which we no longer perform during qemu_st. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	3 年前
tcg-target-con-str.h	tcg/arm: Adjust constraints on qemu_ld/st Always reserve r3 for tlb softmmu lookup. Fix a bug in user-only ALL_QLDST_REGS, in that r14 is clobbered by the BLNE that leads to the misaligned trap. Remove r0+r1 from user-only ALL_QLDST_REGS; I believe these had been reserved for bswap, which we no longer perform during qemu_st. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	3 年前
tcg-target-reg-bits.h	tcg: Split out tcg-target-reg-bits.h Often, the only thing we need to know about the TCG host is the register size. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	3 年前
tcg-target.c.inc	tcg/arm: Use tcg_use_softmmu Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	2 年前
tcg-target.h	tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>	2 年前
tcg-target.opc.h	tcg/arm: Implement TCG_TARGET_HAS_roti_vec Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec. For NEON, this is shift-right followed by shift-left-and-insert. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>	5 年前