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Improve UseAVX setting and add cpu descriptions for zhaoxin processors #741
vicwang创建于 5月27日
Improve UseAVX setting and add cpu descriptions for zhaoxin processors #741
已开启
vicwang创建于 5月27日
从vic-vw/openjdk-1.8.0openEuler-24.03-LTS-SP3-add-zx-feature合入到src-openeuler/openjdk-1.8.0openEuler-24.03-LTS-SP3
共 2 个文件变更+334-1
AImprove-UseAVX-setting-and-add-cpu-descriptions-for-zhaoxin-processors.patch+328-0
@@ -0,0 +1,328 @@
1+diff --git a/hotspot/src/cpu/x86/vm/assembler_x86.cpp b/hotspot/src/cpu/x86/vm/assembler_x86.cpp
2+index 1759ecdf..79e3d611 100644
3+--- a/hotspot/src/cpu/x86/vm/assembler_x86.cpp
4++++ b/hotspot/src/cpu/x86/vm/assembler_x86.cpp
5+@@ -2231,6 +2231,89 @@ void Assembler::nop(int i) {
6+ return;
7+ }
8+
9++ if (UseAddressNop && VM_Version::is_zx()) {
10++ //
11++ // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
12++ // 1: 0x90
13++ // 2: 0x66 0x90
14++ // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
15++ // 4: 0x0F 0x1F 0x40 0x00
16++ // 5: 0x0F 0x1F 0x44 0x00 0x00
17++ // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
18++ // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
19++ // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
20++ // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
21++ // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
22++ // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
23++
24++ // The rest coding is ZX specific - don't use consecutive address nops
25++
26++ // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
27++ // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
28++ // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
29++ // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
30++
31++ while (i >= 15) {
32++ // For ZX don't generate consecutive addess nops (mix with regular nops)
33++ i -= 15;
34++ emit_int8(0x66); // size prefix
35++ emit_int8(0x66); // size prefix
36++ emit_int8(0x66); // size prefix
37++ addr_nop_8();
38++ emit_int8(0x66); // size prefix
39++ emit_int8(0x66); // size prefix
40++ emit_int8(0x66); // size prefix
41++ emit_int8((unsigned char)0x90);
42++ // nop
43++ }
44++ switch (i) {
45++ case 14:
46++ emit_int8(0x66); // size prefix
47++ case 13:
48++ emit_int8(0x66); // size prefix
49++ case 12:
50++ addr_nop_8();
51++ emit_int8(0x66); // size prefix
52++ emit_int8(0x66); // size prefix
53++ emit_int8(0x66); // size prefix
54++ emit_int8((unsigned char)0x90);
55++ // nop
56++ break;
57++ case 11:
58++ emit_int8(0x66); // size prefix
59++ case 10:
60++ emit_int8(0x66); // size prefix
61++ case 9:
62++ emit_int8(0x66); // size prefix
63++ case 8:
64++ addr_nop_8();
65++ break;
66++ case 7:
67++ addr_nop_7();
68++ break;
69++ case 6:
70++ emit_int8(0x66); // size prefix
71++ case 5:
72++ addr_nop_5();
73++ break;
74++ case 4:
75++ addr_nop_4();
76++ break;
77++ case 3:
78++ // Don't use "0x0F 0x1F 0x00" - need patching safe padding
79++ emit_int8(0x66); // size prefix
80++ case 2:
81++ emit_int8(0x66); // size prefix
82++ case 1:
83++ emit_int8((unsigned char)0x90);
84++ // nop
85++ break;
86++ default:
87++ assert(i == 0, " ");
88++ }
89++ return;
90++ }
91++
92+ // Using nops with size prefixes "0x66 0x90".
93+ // From AMD Optimization Guide:
94+ // 1: 0x90
95+diff --git a/hotspot/src/cpu/x86/vm/vm_version_ext_x86.cpp b/hotspot/src/cpu/x86/vm/vm_version_ext_x86.cpp
96+index cea3d890..b3b21ae3 100644
97+--- a/hotspot/src/cpu/x86/vm/vm_version_ext_x86.cpp
98++++ b/hotspot/src/cpu/x86/vm/vm_version_ext_x86.cpp
99+@@ -407,6 +407,23 @@ const char* VM_Version_Ext::cpu_family_description(void) {
100+ }
101+ return _family_id_intel[cpu_family_id];
102+ }
103++ if (is_zx()) {
104++ int cpu_model_id = extended_cpu_model();
105++ if (cpu_family_id == 7) {
106++ switch (cpu_model_id) {
107++ case 0x1B:
108++ return "wudaokou";
109++ case 0x3B:
110++ return "lujiazui";
111++ case 0x5B:
112++ return "yongfeng";
113++ case 0x6B:
114++ return "shijidadao";
115++ }
116++ } else if (cpu_family_id == 6) {
117++ return "zhangjiang";
118++ }
119++ }
120+ return "Unknown x86";
121+ }
122+
123+@@ -423,6 +440,9 @@ int VM_Version_Ext::cpu_type_description(char* const buf, size_t buf_len) {
124+ } else if (is_amd()) {
125+ cpu_type = "AMD";
126+ x64 = cpu_is_em64t() ? " AMD64" : "";
127++ } else if (is_zx()) {
128++ cpu_type = "Zhaoxin";
129++ x64 = cpu_is_em64t() ? "x86_64" : "";
130+ } else {
131+ cpu_type = "Unknown x86";
132+ x64 = cpu_is_em64t() ? " x86_64" : "";
133+diff --git a/hotspot/src/cpu/x86/vm/vm_version_x86.cpp b/hotspot/src/cpu/x86/vm/vm_version_x86.cpp
134+index 42586c4e..4a5e02ee 100644
135+--- a/hotspot/src/cpu/x86/vm/vm_version_x86.cpp
136++++ b/hotspot/src/cpu/x86/vm/vm_version_x86.cpp
137+@@ -470,6 +470,19 @@ void VM_Version::get_processor_features() {
138+ if (UseSSE < 1)
139+ _cpuFeatures &= ~CPU_SSE;
140+
141++ //ZX cpus specific settings
142++ if (is_zx() && FLAG_IS_DEFAULT(UseAVX)) {
143++ if (cpu_family() == 7) {
144++ if (extended_cpu_model() == 0x5B || extended_cpu_model() == 0x6B) {
145++ UseAVX = 1;
146++ } else if (extended_cpu_model() == 0x1B || extended_cpu_model() == 0x3B) {
147++ UseAVX = 0;
148++ }
149++ } else if (cpu_family() == 6) {
150++ UseAVX = 0;
151++ }
152++ }
153++
154+ if (UseAVX < 2)
155+ _cpuFeatures &= ~CPU_AVX2;
156+
157+@@ -772,6 +785,65 @@ void VM_Version::get_processor_features() {
158+ // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
159+ // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
160+
161++ if (is_zx()) { // ZX cpus specific settings
162++ if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
163++ UseStoreImmI16 = false; // don't use it on ZX cpus
164++ }
165++ if ((cpu_family() == 6) || (cpu_family() == 7)) {
166++ if (FLAG_IS_DEFAULT(UseAddressNop)) {
167++ // Use it on all ZX cpus
168++ UseAddressNop = true;
169++ }
170++ }
171++ if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
172++ UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus
173++ }
174++ if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
175++ if (supports_sse3()) {
176++ UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus
177++ } else {
178++ UseXmmRegToRegMoveAll = false;
179++ }
180++ }
181++ if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus
182++#ifdef COMPILER2
183++ if (FLAG_IS_DEFAULT(MaxLoopPad)) {
184++ // For new ZX cpus do the next optimization:
185++ // don't align the beginning of a loop if there are enough instructions
186++ // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
187++ // in current fetch line (OptoLoopAlignment) or the padding
188++ // is big (> MaxLoopPad).
189++ // Set MaxLoopPad to 11 for new ZX cpus to reduce number of
190++ // generated NOP instructions. 11 is the largest size of one
191++ // address NOP instruction '0F 1F' (see Assembler::nop(i)).
192++ MaxLoopPad = 11;
193++ }
194++#endif // COMPILER2
195++ if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
196++ UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus
197++ }
198++ if (supports_sse4_2()) { // new ZX cpus
199++ if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
200++ UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
201++ }
202++ }
203++ if (supports_sse4_2()) {
204++ if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
205++ FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
206++ }
207++ } else {
208++ if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
209++ warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
210++ }
211++ FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
212++ }
213++ }
214++
215++ if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
216++ FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
217++ }
218++ }
219++
220+ if( is_amd() ) { // AMD cpus specific settings
221+ if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
222+ // Use it on new AMD cpus starting from Opteron.
223+@@ -1032,6 +1104,15 @@ void VM_Version::get_processor_features() {
224+ }
225+ #endif
226+ }
227++
228++ if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) {
229++#ifdef COMPILER2
230++ if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
231++ FLAG_SET_DEFAULT(UseFPUForSpilling, true);
232++ }
233++#endif
234++ }
235++
236+ assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
237+
238+ #ifdef _LP64
239+diff --git a/hotspot/src/cpu/x86/vm/vm_version_x86.hpp b/hotspot/src/cpu/x86/vm/vm_version_x86.hpp
240+index 5bb872b7..67fb2d7d 100644
241+--- a/hotspot/src/cpu/x86/vm/vm_version_x86.hpp
242++++ b/hotspot/src/cpu/x86/vm/vm_version_x86.hpp
243+@@ -269,6 +269,9 @@ protected:
244+ enum {
245+ // AMD
246+ CPU_FAMILY_AMD_11H = 0x11,
247++ // ZX
248++ CPU_FAMILY_ZX_CORE_F6 = 6,
249++ CPU_FAMILY_ZX_CORE_F7 = 7,
250+ // Intel
251+ CPU_FAMILY_INTEL_CORE = 6,
252+ CPU_MODEL_NEHALEM = 0x1e,
253+@@ -480,6 +483,20 @@ protected:
254+ }
255+ }
256+
257++ // ZX features.
258++ if (is_zx()) {
259++ if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
260++ result |= CPU_ADX;
261++ if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
262++ result |= CPU_BMI2;
263++ if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
264++ result |= CPU_LZCNT;
265++ // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
266++ if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
267++ result |= CPU_3DNOW_PREFETCH;
268++ }
269++ }
270++
271+ return result;
272+ }
273+
274+@@ -559,6 +576,7 @@ public:
275+ static bool is_P6() { return cpu_family() >= 6; }
276+ static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
277+ static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
278++ static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS '
279+
280+ static bool supports_processor_topology() {
281+ return (_cpuid_info.std_max_function >= 0xB) &&
282+@@ -580,6 +598,15 @@ public:
283+ }
284+ } else if (is_amd()) {
285+ result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
286++ } else if (is_zx()) {
287++ bool supports_topology = supports_processor_topology();
288++ if (supports_topology) {
289++ result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
290++ _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
291++ }
292++ if (!supports_topology || result == 0) {
293++ result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
294++ }
295+ }
296+ return result;
297+ }
298+@@ -588,6 +615,8 @@ public:
299+ uint result = 1;
300+ if (is_intel() && supports_processor_topology()) {
301+ result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
302++ } else if (is_zx() && supports_processor_topology()) {
303++ result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
304+ } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
305+ result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
306+ cores_per_cpu();
307+@@ -601,6 +630,8 @@ public:
308+ result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
309+ } else if (is_amd()) {
310+ result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
311++ } else if (is_zx()) {
312++ result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
313+ }
314+ if (result < 32) // not defined ?
315+ result = 32; // 32 bytes by default on x86 and other x64
316+@@ -711,6 +742,12 @@ public:
317+ count = 256; // Opteron
318+ else
319+ count = 128; // Athlon
320++ } else if (is_zx()) { // ZX
321++ if (supports_sse2()) {
322++ return 256;
323++ } else {
324++ return 128;
325++ }
326+ } else { // Intel
327+ if (supports_sse2())
328+ if (cpu_family() == 6) {
Mopenjdk-1.8.0.spec+6-1
@@ -953,7 +953,7 @@ Provides: java-%{javaver}-%{origin}-accessibility%{?1} = %{epoch}:%{version}-%{r
953 953 
954Name: java-%{javaver}-%{origin}954Name: java-%{javaver}-%{origin}
955Version: %{javaver}.%{updatever}.%{buildver}955Version: %{javaver}.%{updatever}.%{buildver}
956-Release: 8956+Release: 9
957# java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons957# java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons
958# and this change was brought into RHEL-4. java-1.5.0-ibm packages958# and this change was brought into RHEL-4. java-1.5.0-ibm packages
959# also included the epoch in their virtual provides. This created a959# also included the epoch in their virtual provides. This created a
@@ -1399,6 +1399,7 @@ Patch485: fix-libpng-CVE-2026-25646.patch
1399Patch486: fix-zlib-CVE-2026-27171.patch1399Patch486: fix-zlib-CVE-2026-27171.patch
1400Patch487: update-JProfileCache-feature.patch1400Patch487: update-JProfileCache-feature.patch
1401Patch488: JProfileCache-preload-resolved-classes-during-resolution.patch1401Patch488: JProfileCache-preload-resolved-classes-during-resolution.patch
1402+Patch489: Improve-UseAVX-setting-and-add-cpu-descriptions-for-zhaoxin-processors.patch
1402 1403 
1403#############################################1404#############################################
1404#1405#
@@ -2101,6 +2102,7 @@ pushd %{top_level_dir_name}
2101%patch486 -p12102%patch486 -p1
2102%patch487 -p12103%patch487 -p1
2103%patch488 -p12104%patch488 -p1
2105+%patch489 -p1
2104%endif2106%endif
2105 2107 
2106%ifarch loongarch642108%ifarch loongarch64
@@ -3084,6 +3086,9 @@ cjc.mainProgram(args) -- the returns from copy_jdk_configs.lua should not affect
3084%endif3086%endif
3085 3087 
3086%changelog3088%changelog
3089+* Tue May 26 2026 vicwang <vicwang-oc@zhaoxin.com> -1:1.8.0.482.b08-9
3090+- add Improve-UseAVX-setting-and-add-cpu-descriptions-for-zhaoxin-processors.patch
3091+ 
3087* Mon Mar 23 2026 lc-compiler <lc@wxiat.com> -1:1.8.0.482.b08-83092* Mon Mar 23 2026 lc-compiler <lc@wxiat.com> -1:1.8.0.482.b08-8
3088- swjdk8u4823093- swjdk8u482
3089 3094