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算子类型 Conv2D, 数据类型float16 fmap(NCHW):[8, 912, 14, 14] weight(NCHW):[912, 24, 3, 3] group属性:38 stride属性:2 dilation属性:全为1 pad属性:全为0 带bias
SOC:Ascend950PR 版本:基于当前最新版本
1)按算子规格输入构造input、weight、属性等输入 2)在对应950PR环境(32核)执行相关用例(通路可以使用pytorch)
精度正确
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.207 [conv2d_v2_base_tiling_fast_tiling.cpp:59][OPS_NN][GetTilingFromFastTiling][1006276] OpName:[] Conv2DV2 AscendC: get tiling from Mmode basic block algorithm, belongs to fast_tiling. [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.214 [conv2d_v2_base_tiling_fast_tiling.cpp:62][OPS_NN][GetTilingFromFastTiling][1006276] OpName:[] Conv2DV2 AscendC: batchDim / mDim / nDim / groupDim: 4, 1, 2, 4. [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.234 [conv2d_v2_base_tiling_print.cpp:46][OPS_NN][PrintOpTilingData][1006276] OpName:[] Conv2DV2 AscendC: ops tilingdata: hin: 14, win: 14, hout: 7, wout: 7, batch: 8, cin: 912, cout: 912, kh: 3, kw: 3, batchDim: 4, hoDim: 1, woDim: 1, nDim: 2, strideH: 2, strideW: 2, dilationH: 1, dilationW: 1, padTop: 0, padLeft: 0, groups: 38, cinOpt: 48, coutOpt: 48, groupOpt: 19, enlarge: 2, groupDim: 4, hasBias: 1 [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.247 [conv2d_v2_base_tiling_fast_tiling.cpp:246][OPS_NN][Conv2dApiTilingSetShape][1006276] OpName:[] Conv2DV2 AscendC: api got: orgCo: 912, orgkH: 3, orgkW: 3, orgHi: 14, orgWi: 14, singleCo: 32, singleHo: 0, singleWo: 7, singleM: 64, singleGroups: 2, singleGroupOpt: 5, enlarge: 2 [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.258 [conv2d_v2_api_tiling.cpp:1195][OPS_NN][PrintConv2DBasicBlockInfoPhase2][1006276] OpName:[Conv2DV2] [Phase2]: batchDim[4], mDim[1], nDim[2], groupDim[4], mCut[1], nCut[2], mTile[64], nTile[32], mIn[196], [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.269 [conv_api_tiling_algorithm_BBmode.cpp:509][OPS_NN][GetL1Tiling][1006276] OpName:[Conv2DV2] l1LoadStrategyType is: 0 [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.276 [conv_api_tiling_algorithm_BBmode.cpp:672][OPS_NN][GetL1LoadTilingParams][1006276] OpName:[Conv2DV2] singleBBFmapSize: 18816, singleBBWeightSize: 27648, fmapSizeMultix1: 18816, weightBBSizeMultix1: 27648 [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.292 [conv2d_v2_base_tiling_tilingkey.cpp:336][OPS_NN][SetTilingKey][1006276] OpName:[] Conv2DV2 AscendC: c04 mode status is: 0 [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.304 [conv2d_v2_base_tiling_tilingkey.cpp:356][OPS_NN][SetTilingKey][1006276] OpName:[] Conv2DV2 AscendC: tiling key: 2544. fmpTiling[0], weightTiling[0], l1PingPong[3], l0PingPong[3], outputOrder[1], iterOrder[0], groupType[2], enableSmallChannel[0], weightUbTrans[0], fmapCppyMode[0], innerBatch[0], disContinuous[0], batchOne[0], noPad[0], smallWeight[0], smallKernel[0]. [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.329 [conv2d_v2_base_tiling_print.cpp:164][OPS_NN][PrintLibApiTilingData][1006276] OpName:[] Conv2DV2 AscendC: api tilingdata: singleCoreHo: 64, singleCoreWo: 0, singleCoreBatch: 2, orgHi: 14, orgWi: 14, orgHo: 7, orgWo: 7, groups: 38, orgCi: 912, orgCo: 912, kernelH: 3, kernelW: 3, singleCoreCi: 48, singleCoreCo: 32, hoL1: 64, woL1: 0, kAL1: 432, kBL1: 432, nBL1: 32, hoL0: 64, woL0: 0, kL0: 144, nL0: 32, pBufferFlag: 31, multiNBL1: 1, strideH: 2, strideW: 2, dilationH: 1, dilationW: 1, padTop: 0, padBottom: 1, padLeft: 0, padRight: 1, aL1SpaceSize: 18816, singleCoreGroups: 2, singleCoreGroupOpt: 5, enlarge: 2, bUbNStep: 0, iterateMNOrder: 0, biasFullLoadFlag: 1, fixpParamsFullLoadFlag: 1, hf32Enable: 0, hf32TransMode: 0, hasBias: 1, hasScale: 0, offsetx: 0, roundMode: 0, innerBatch: 1 [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.341 [conv2d_v2_base_tiling_print.cpp:165][OPS_NN][PrintLibApiTilingData][1006276] OpName:[] bUbKStep: 0, orgHixWi: 196, kernelHxkernelW: 9, kernelHxkernelWxkernelD: 9, cinAInCore: 48, cinATailInCore: 48, cinBInCore: 48, cinBTailInCore: 48, mStep: 64, kStep: 9, nStep: 2, fmapKStride: 4, weightKStride: 2, cinOffsetBlockInGM: 9408, coutOffsetBlock: 216, nL1DivBlockSize: 2, dualOutput: 0, quantMode0: 0, reluMode0: 0, clipMode0: 0, quantMode1: 0, reluMode1: 0, clipMode1: 0, khL1: 0, kwL1: 0, khUb: 0, kwUb: 0, unionDataXt: 271593602 [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.352 [conv2d_v2_base_tiling.cpp:467][OPS_NN][DoLibApiTiling][1006276] OpName:[] Conv2DV2 AscendC: success to add fast tiling to cache [DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.382 [batch_mat_mul_v3_base_tiling.cpp:148][OPS_NN][DefaultTilingInfoDump][1006276] OpName:[Conv2DV2:] Start to dump tiling info. tilingkey:2544, tiling data size:376, content:14,0,14,0,7,0,7,0,196,0,2,0,64,0,0,0,271593602,16,14,0,14,0,7,0,7,0,912,912,48,32,64,0,432,432,0,0,32,64,0,144,32,31,38,2,2,5,0,0,0,0,9,9,18816,1,48,48,48,48,64,9,2,4,2,9408,216,2,3,3,2,2,1,1,0,1,0,1,1,8,912,912,3,3,4,4,2,1,1,48,48,19,65792,256,0,0,
Thanks for sending an issue! Please fill in the following template to help quickly solve your problem.
Describe the current behavior / 问题描述 (Mandatory / 必填)
算子类型 Conv2D, 数据类型float16
fmap(NCHW):[8, 912, 14, 14]
weight(NCHW):[912, 24, 3, 3]
group属性:38
stride属性:2
dilation属性:全为1
pad属性:全为0
带bias
Environment / 环境信息 (Mandatory / 必填)
SOC:Ascend950PR
版本:基于当前最新版本
Steps to reproduce the issue / 重现步骤 (Mandatory / 必填)
1)按算子规格输入构造input、weight、属性等输入
2)在对应950PR环境(32核)执行相关用例(通路可以使用pytorch)
Describe the expected behavior / 预期结果 (Mandatory / 必填)
精度正确
Related log / screenshot / 日志 / 截图 (Mandatory / 必填)
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.207 [conv2d_v2_base_tiling_fast_tiling.cpp:59][OPS_NN][GetTilingFromFastTiling][1006276] OpName:[] Conv2DV2 AscendC: get tiling from Mmode basic block algorithm, belongs to fast_tiling.
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.214 [conv2d_v2_base_tiling_fast_tiling.cpp:62][OPS_NN][GetTilingFromFastTiling][1006276] OpName:[] Conv2DV2 AscendC: batchDim / mDim / nDim / groupDim: 4, 1, 2, 4.
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.234 [conv2d_v2_base_tiling_print.cpp:46][OPS_NN][PrintOpTilingData][1006276] OpName:[] Conv2DV2 AscendC: ops tilingdata: hin: 14, win: 14, hout: 7, wout: 7, batch: 8, cin: 912, cout: 912, kh: 3, kw: 3, batchDim: 4, hoDim: 1, woDim: 1, nDim: 2, strideH: 2, strideW: 2, dilationH: 1, dilationW: 1, padTop: 0, padLeft: 0, groups: 38, cinOpt: 48, coutOpt: 48, groupOpt: 19, enlarge: 2, groupDim: 4, hasBias: 1
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.247 [conv2d_v2_base_tiling_fast_tiling.cpp:246][OPS_NN][Conv2dApiTilingSetShape][1006276] OpName:[] Conv2DV2 AscendC: api got: orgCo: 912, orgkH: 3, orgkW: 3, orgHi: 14, orgWi: 14, singleCo: 32, singleHo: 0, singleWo: 7, singleM: 64, singleGroups: 2, singleGroupOpt: 5, enlarge: 2
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.258 [conv2d_v2_api_tiling.cpp:1195][OPS_NN][PrintConv2DBasicBlockInfoPhase2][1006276] OpName:[Conv2DV2] [Phase2]: batchDim[4], mDim[1], nDim[2], groupDim[4], mCut[1], nCut[2], mTile[64], nTile[32], mIn[196],
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.269 [conv_api_tiling_algorithm_BBmode.cpp:509][OPS_NN][GetL1Tiling][1006276] OpName:[Conv2DV2] l1LoadStrategyType is: 0
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.276 [conv_api_tiling_algorithm_BBmode.cpp:672][OPS_NN][GetL1LoadTilingParams][1006276] OpName:[Conv2DV2] singleBBFmapSize: 18816, singleBBWeightSize: 27648, fmapSizeMultix1: 18816, weightBBSizeMultix1: 27648
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.292 [conv2d_v2_base_tiling_tilingkey.cpp:336][OPS_NN][SetTilingKey][1006276] OpName:[] Conv2DV2 AscendC: c04 mode status is: 0
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.304 [conv2d_v2_base_tiling_tilingkey.cpp:356][OPS_NN][SetTilingKey][1006276] OpName:[] Conv2DV2 AscendC: tiling key: 2544. fmpTiling[0], weightTiling[0], l1PingPong[3], l0PingPong[3], outputOrder[1], iterOrder[0], groupType[2], enableSmallChannel[0], weightUbTrans[0], fmapCppyMode[0], innerBatch[0], disContinuous[0], batchOne[0], noPad[0], smallWeight[0], smallKernel[0].
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.329 [conv2d_v2_base_tiling_print.cpp:164][OPS_NN][PrintLibApiTilingData][1006276] OpName:[] Conv2DV2 AscendC: api tilingdata: singleCoreHo: 64, singleCoreWo: 0, singleCoreBatch: 2, orgHi: 14, orgWi: 14, orgHo: 7, orgWo: 7, groups: 38, orgCi: 912, orgCo: 912, kernelH: 3, kernelW: 3, singleCoreCi: 48, singleCoreCo: 32, hoL1: 64, woL1: 0, kAL1: 432, kBL1: 432, nBL1: 32, hoL0: 64, woL0: 0, kL0: 144, nL0: 32, pBufferFlag: 31, multiNBL1: 1, strideH: 2, strideW: 2, dilationH: 1, dilationW: 1, padTop: 0, padBottom: 1, padLeft: 0, padRight: 1, aL1SpaceSize: 18816, singleCoreGroups: 2, singleCoreGroupOpt: 5, enlarge: 2, bUbNStep: 0, iterateMNOrder: 0, biasFullLoadFlag: 1, fixpParamsFullLoadFlag: 1, hf32Enable: 0, hf32TransMode: 0, hasBias: 1, hasScale: 0, offsetx: 0, roundMode: 0, innerBatch: 1
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.341 [conv2d_v2_base_tiling_print.cpp:165][OPS_NN][PrintLibApiTilingData][1006276] OpName:[] bUbKStep: 0, orgHixWi: 196, kernelHxkernelW: 9, kernelHxkernelWxkernelD: 9, cinAInCore: 48, cinATailInCore: 48, cinBInCore: 48, cinBTailInCore: 48, mStep: 64, kStep: 9, nStep: 2, fmapKStride: 4, weightKStride: 2, cinOffsetBlockInGM: 9408, coutOffsetBlock: 216, nL1DivBlockSize: 2, dualOutput: 0, quantMode0: 0, reluMode0: 0, clipMode0: 0, quantMode1: 0, reluMode1: 0, clipMode1: 0, khL1: 0, kwL1: 0, khUb: 0, kwUb: 0, unionDataXt: 271593602
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.352 [conv2d_v2_base_tiling.cpp:467][OPS_NN][DoLibApiTiling][1006276] OpName:[] Conv2DV2 AscendC: success to add fast tiling to cache
[DEBUG] OP(1006276,python3):2026-06-25-11:51:58.823.382 [batch_mat_mul_v3_base_tiling.cpp:148][OPS_NN][DefaultTilingInfoDump][1006276] OpName:[Conv2DV2:] Start to dump tiling info. tilingkey:2544, tiling data size:376, content:14,0,14,0,7,0,7,0,196,0,2,0,64,0,0,0,271593602,16,14,0,14,0,7,0,7,0,912,912,48,32,64,0,432,432,0,0,32,64,0,144,32,31,38,2,2,5,0,0,0,0,9,9,18816,1,48,48,48,48,64,9,2,4,2,9408,216,2,3,3,2,2,1,1,0,1,0,1,1,8,912,912,3,3,4,4,2,1,1,48,48,19,65792,256,0,0,
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