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npu coredump #1570
yring_8创建于 4月14日
npu coredump #1570
已合并
yring_8创建于 4月14日
从已删除 :master合入到cann/runtimemaster
共 25 个文件变更+478-610
Minclude/external/acl/acl_dump.h+2-2
@@ -62,13 +62,13 @@ ACL_FUNC_VISIBILITY aclError aclopStartDumpArgs(uint32_t dumpType, const char *p
62 */62 */
63ACL_FUNC_VISIBILITY aclError aclopStopDumpArgs(uint32_t dumpType);63ACL_FUNC_VISIBILITY aclError aclopStopDumpArgs(uint32_t dumpType);
64 64 
65-enum acldumpType {65+typedef enum acldumpType {
66 AIC_ERR_BRIEF_DUMP = 1, // lite exception dump66 AIC_ERR_BRIEF_DUMP = 1, // lite exception dump
67 AIC_ERR_NORM_DUMP = 2, // normal exception dump67 AIC_ERR_NORM_DUMP = 2, // normal exception dump
68 AIC_ERR_DETAIL_DUMP = 3, // coredump mode68 AIC_ERR_DETAIL_DUMP = 3, // coredump mode
69 DATA_DUMP = 4, // tensor data dump69 DATA_DUMP = 4, // tensor data dump
70 OVERFLOW_DUMP = 5 // overflow dump70 OVERFLOW_DUMP = 5 // overflow dump
71-};71+} acldumpType;
72 72 
73/**73/**
74 * @ingroup AscendCL74 * @ingroup AscendCL
Dpkg_inc/dump/acl_dump.h+0-76
@@ -1,76 +0,0 @@
1-/**
2-  * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3-  * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4-  * CANN Open Software License Agreement Version 2.0 (the "License").
5-  * Please refer to the License for details. You may not use this file except in compliance with the License.
6-  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7-  * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8-  * See LICENSE in the root of the software repository for the full text of the License.
9-  */
10- 
11-/*!
12- * \file acl_dump.h
13- * \brief
14-*/
15- 
16-#ifndef INC_EXTERNAL_ACL_DUMP_H_
17-#define INC_EXTERNAL_ACL_DUMP_H_
18- 
19-#include <stdint.h>
20- 
21-#if (defined(_WIN32) || defined(_WIN64) || defined(_MSC_VER))
22-#define ACL_DUMP_API __declspec(dllexport)
23-#else
24-#define ACL_DUMP_API __attribute__((visibility("default")))
25-#endif
26- 
27-#include "acl_base.h"
28- 
29-#ifdef __cplusplus
30-extern "C" {
31-#endif
32- 
33-#define ACL_DUMP_MAX_FILE_PATH_LENGTH 4096
34-typedef struct acldumpChunk {
35- char fileName[ACL_DUMP_MAX_FILE_PATH_LENGTH]; // file name, absolute path
36- uint32_t bufLen; // dataBuf length
37- uint32_t isLastChunk; // is last chunk. 0: not 1: yes
38- int64_t offset; // Offset in file. -1: append write
39- int32_t flag; // flag
40- uint8_t dataBuf[0]; // data buffer
41-} acldumpChunk;
42- 
43-ACL_DUMP_API aclError acldumpRegCallback(int32_t (* const messageCallback)(const acldumpChunk *, int32_t),
44- int32_t flag);
45-ACL_DUMP_API void acldumpUnregCallback();
46- 
47-#define ACL_OP_DUMP_OP_AICORE_ARGS 0x00000001U
48- 
49-/**
50- * @ingroup AscendCL
51- * @brief Enable the dump function of the corresponding dump type.
52- *
53- * @param dumpType [IN] type of dump
54- * @param path [IN] dump path
55- *
56- * @retval ACL_SUCCESS The function is successfully executed.
57- * @retval OtherValues Failure
58- */
59-ACL_FUNC_VISIBILITY aclError aclopStartDumpArgs(uint32_t dumpType, const char *path);
60- 
61-/**
62- * @ingroup AscendCL
63- * @brief Disable the dump function of the corresponding dump type.
64- *
65- * @param dumpType [IN] type of dump
66- *
67- * @retval ACL_SUCCESS The function is successfully executed.
68- * @retval OtherValues Failure
69- */
70-ACL_FUNC_VISIBILITY aclError aclopStopDumpArgs(uint32_t dumpType);
71- 
72-#ifdef __cplusplus
73-}
74-#endif
75- 
76-#endif
Dpkg_inc/dump/adx_exception_callback.h+0-87
@@ -1,87 +0,0 @@
1-/**
2-  * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3-  * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4-  * CANN Open Software License Agreement Version 2.0 (the "License").
5-  * Please refer to the License for details. You may not use this file except in compliance with the License.
6-  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7-  * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8-  * See LICENSE in the root of the software repository for the full text of the License.
9-  */
10- 
11-/*!
12- * \file adx_exception_callback.h
13- * \brief
14-*/
15- 
16-#ifndef ADX_EXCEPTION_CALLBACK_H
17-#define ADX_EXCEPTION_CALLBACK_H
18-#include <cstdint>
19-#if (defined(_WIN32) || defined(_WIN64) || defined(_MSC_VER))
20-#define ADX_API __declspec(dllexport)
21-#else
22-#define ADX_API __attribute__((visibility("default")))
23-#endif
24-namespace Adx {
25- 
26-/**
27- * @name HeadProcess
28- * @brief Callback for increasing target size
29- * @param addr [IN] Pointer to the header addr
30- * @param headerSize [IN] Header size
31- * @param newHeaderSize [OUT] New header size after target size is added
32- * @return success: 0, fail: -1
33- */
34-using HeadProcess = int32_t (*)(uint32_t deviceId, const void *addr, uint64_t headerSize, uint64_t &newHeaderSize);
35- 
36-/**
37- * @name TensorProcess
38- * @brief Callback for increasing target size content
39- * @param addr [IN] Pointer to the header addr
40- * @param size [IN] Header size
41- * @param fd [IN] File descriptor
42- * @return success: 0, fail: -1
43- */
44-using TensorProcess = int32_t (*)(uint32_t deviceId, const void *addr, uint64_t size, int32_t fd);
45- 
46-enum class DfxTensorType : uint16_t {
47- INVALID_TENSOR = 0,
48- GENERAL_TENSOR = 1,
49- INPUT_TENSOR,
50- OUTPUT_TENSOR,
51- WORKSPACE_TENSOR,
52- ASCENDC_LOG = 5,
53- MC2_CTX,
54- TILING_DATA,
55- L1,
56- L2,
57- OVERFLOW_ADDRESS = 10,
58- FFTS_ADDRESS,
59- SHAPE_TENSOR,
60- ARGS = 101, // args以下为 coredump 新增的，中间预留，从101开始定义
61- STACK = 102,
62- DEVICE_KERNEL_OBJECT = 103, //device侧GM中算子.o数据
63-};
64- 
65-#ifndef ADUMP_TINY_CHIP
66-/**
67- * @name AdumpRegHeadProcess
68- * @brief Callback register for header size increase
69- * @param tensorType [IN] tensor type
70- * @param headProcess [IN] Callback function for header size increase
71- * @return success: 0, fail: -1
72- */
73-ADX_API int32_t AdumpRegHeadProcess(DfxTensorType tensorType, HeadProcess headProcess);
74- 
75-/**
76- * @name AdumpRegTensorProcess
77- * @brief Callback register for tensor data writing
78- * @param tensorType [IN] tensor type
79- * @param tensorProcess [IN] Callback function for tensor data writing
80- * @return success: 0, fail: -1
81- */
82-ADX_API int32_t AdumpRegTensorProcess(DfxTensorType tensorType, TensorProcess tensorProcess);
83-#endif
84- 
85-} // namespace Adx
86- 
87-#endif
Msrc/dfx/adump/adump/adump_couple/ascend_dump.cmake+0-2
@@ -27,7 +27,6 @@ set(ascendDumpSrcList
27 ${ADUMP_ADUMP_DIR}/exception/dump_args.cpp27 ${ADUMP_ADUMP_DIR}/exception/dump_args.cpp
28 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core.cpp28 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core.cpp
29 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core_register.cpp29 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core_register.cpp
30- ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core_platform.cpp
31 ${ADUMP_ADUMP_DIR}/exception/dump_ELF.cpp30 ${ADUMP_ADUMP_DIR}/exception/dump_ELF.cpp
32 ${ADUMP_ADUMP_DIR}/exception/dump_file.cpp31 ${ADUMP_ADUMP_DIR}/exception/dump_file.cpp
33 ${ADUMP_ADUMP_DIR}/exception/dump_operator.cpp32 ${ADUMP_ADUMP_DIR}/exception/dump_operator.cpp
@@ -37,7 +36,6 @@ set(ascendDumpSrcList
37 ${ADUMP_ADUMP_DIR}/exception/exception_info_common.cpp36 ${ADUMP_ADUMP_DIR}/exception/exception_info_common.cpp
38 ${ADUMP_ADUMP_DIR}/exception/kernel_info_collector.cpp37 ${ADUMP_ADUMP_DIR}/exception/kernel_info_collector.cpp
39 ${ADUMP_ADUMP_DIR}/exception/register_config/register_config.cpp38 ${ADUMP_ADUMP_DIR}/exception/register_config/register_config.cpp
40- ${ADUMP_ADUMP_DIR}/exception/register_config/register_config_platform.cpp
41 ${ADUMP_ADUMP_DIR}/exception/thread_manager.cpp39 ${ADUMP_ADUMP_DIR}/exception/thread_manager.cpp
42 ${ADUMP_ADUMP_DIR}/impl/dump_datatype.cpp40 ${ADUMP_ADUMP_DIR}/impl/dump_datatype.cpp
43 ${ADUMP_ADUMP_DIR}/impl/dump_memory.cpp41 ${ADUMP_ADUMP_DIR}/impl/dump_memory.cpp
Msrc/dfx/adump/adump/adump_couple/ascend_dump_close.cmake+0-2
@@ -27,7 +27,6 @@ set(ascendDumpSrcList
27 ${ADUMP_ADUMP_DIR}/exception/dump_args.cpp27 ${ADUMP_ADUMP_DIR}/exception/dump_args.cpp
28 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core.cpp28 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core.cpp
29 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core_register.cpp29 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core_register.cpp
30- ${ADUMP_ADUMP_DIR}/exception/dump_core/close/dump_core_platform.cpp
31 ${ADUMP_ADUMP_DIR}/exception/dump_ELF.cpp30 ${ADUMP_ADUMP_DIR}/exception/dump_ELF.cpp
32 ${ADUMP_ADUMP_DIR}/exception/dump_file.cpp31 ${ADUMP_ADUMP_DIR}/exception/dump_file.cpp
33 ${ADUMP_ADUMP_DIR}/exception/dump_operator.cpp32 ${ADUMP_ADUMP_DIR}/exception/dump_operator.cpp
@@ -37,7 +36,6 @@ set(ascendDumpSrcList
37 ${ADUMP_ADUMP_DIR}/exception/exception_info_common.cpp36 ${ADUMP_ADUMP_DIR}/exception/exception_info_common.cpp
38 ${ADUMP_ADUMP_DIR}/exception/kernel_info_collector.cpp37 ${ADUMP_ADUMP_DIR}/exception/kernel_info_collector.cpp
39 ${ADUMP_ADUMP_DIR}/exception/register_config/register_config.cpp38 ${ADUMP_ADUMP_DIR}/exception/register_config/register_config.cpp
40- ${ADUMP_ADUMP_DIR}/exception/register_config/close/register_config_platform.cpp
41 ${ADUMP_ADUMP_DIR}/exception/thread_manager.cpp39 ${ADUMP_ADUMP_DIR}/exception/thread_manager.cpp
42 ${ADUMP_ADUMP_DIR}/impl/dump_datatype.cpp40 ${ADUMP_ADUMP_DIR}/impl/dump_datatype.cpp
43 ${ADUMP_ADUMP_DIR}/impl/dump_memory.cpp41 ${ADUMP_ADUMP_DIR}/impl/dump_memory.cpp
Msrc/dfx/adump/adump/adump_decouple/ascend_dump.cmake+0-2
@@ -27,7 +27,6 @@ set(ascendDumpSrcList
27 ${ADUMP_ADUMP_DIR}/exception/dump_args.cpp27 ${ADUMP_ADUMP_DIR}/exception/dump_args.cpp
28 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core.cpp28 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core.cpp
29 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core_register.cpp29 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core_register.cpp
30- ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core_platform.cpp
31 ${ADUMP_ADUMP_DIR}/exception/dump_ELF.cpp30 ${ADUMP_ADUMP_DIR}/exception/dump_ELF.cpp
32 ${ADUMP_ADUMP_DIR}/exception/dump_file.cpp31 ${ADUMP_ADUMP_DIR}/exception/dump_file.cpp
33 ${ADUMP_ADUMP_DIR}/exception/dump_operator.cpp32 ${ADUMP_ADUMP_DIR}/exception/dump_operator.cpp
@@ -37,7 +36,6 @@ set(ascendDumpSrcList
37 ${ADUMP_ADUMP_DIR}/exception/exception_info_common.cpp36 ${ADUMP_ADUMP_DIR}/exception/exception_info_common.cpp
38 ${ADUMP_ADUMP_DIR}/exception/kernel_info_collector.cpp37 ${ADUMP_ADUMP_DIR}/exception/kernel_info_collector.cpp
39 ${ADUMP_ADUMP_DIR}/exception/register_config/register_config.cpp38 ${ADUMP_ADUMP_DIR}/exception/register_config/register_config.cpp
40- ${ADUMP_ADUMP_DIR}/exception/register_config/register_config_platform.cpp
41 ${ADUMP_ADUMP_DIR}/exception/thread_manager.cpp39 ${ADUMP_ADUMP_DIR}/exception/thread_manager.cpp
42 ${ADUMP_ADUMP_DIR}/impl/dump_datatype.cpp40 ${ADUMP_ADUMP_DIR}/impl/dump_datatype.cpp
43 ${ADUMP_ADUMP_DIR}/impl/dump_memory.cpp41 ${ADUMP_ADUMP_DIR}/impl/dump_memory.cpp
Msrc/dfx/adump/adump/adump_decouple/ascend_dump_close.cmake+0-2
@@ -27,7 +27,6 @@ set(ascendDumpSrcList
27 ${ADUMP_ADUMP_DIR}/exception/dump_args.cpp27 ${ADUMP_ADUMP_DIR}/exception/dump_args.cpp
28 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core.cpp28 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core.cpp
29 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core_register.cpp29 ${ADUMP_ADUMP_DIR}/exception/dump_core/dump_core_register.cpp
30- ${ADUMP_ADUMP_DIR}/exception/dump_core/close/dump_core_platform.cpp
31 ${ADUMP_ADUMP_DIR}/exception/dump_ELF.cpp30 ${ADUMP_ADUMP_DIR}/exception/dump_ELF.cpp
32 ${ADUMP_ADUMP_DIR}/exception/dump_file.cpp31 ${ADUMP_ADUMP_DIR}/exception/dump_file.cpp
33 ${ADUMP_ADUMP_DIR}/exception/dump_operator.cpp32 ${ADUMP_ADUMP_DIR}/exception/dump_operator.cpp
@@ -37,7 +36,6 @@ set(ascendDumpSrcList
37 ${ADUMP_ADUMP_DIR}/exception/exception_info_common.cpp36 ${ADUMP_ADUMP_DIR}/exception/exception_info_common.cpp
38 ${ADUMP_ADUMP_DIR}/exception/kernel_info_collector.cpp37 ${ADUMP_ADUMP_DIR}/exception/kernel_info_collector.cpp
39 ${ADUMP_ADUMP_DIR}/exception/register_config/register_config.cpp38 ${ADUMP_ADUMP_DIR}/exception/register_config/register_config.cpp
40- ${ADUMP_ADUMP_DIR}/exception/register_config/close/register_config_platform.cpp
41 ${ADUMP_ADUMP_DIR}/exception/thread_manager.cpp39 ${ADUMP_ADUMP_DIR}/exception/thread_manager.cpp
42 ${ADUMP_ADUMP_DIR}/impl/dump_datatype.cpp40 ${ADUMP_ADUMP_DIR}/impl/dump_datatype.cpp
43 ${ADUMP_ADUMP_DIR}/impl/dump_memory.cpp41 ${ADUMP_ADUMP_DIR}/impl/dump_memory.cpp
Dsrc/dfx/adump/adump/exception/dump_core/close/dump_core_platform.cpp+0-98
@@ -1,98 +0,0 @@
1-/**
2- 
3- * Copyright (c) 2025 Huawei Technologies Co., Ltd.
4- * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
5- * CANN Open Software License Agreement Version 2.0 (the "License").
6- * Please refer to the License for details. You may not use this file except in compliance with the License.
7- * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
8- * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
9- * See LICENSE in the root of the software repository for the full text of the License.
10- */
11-#include "dump_core.h"
12-#include "log/adx_log.h"
13-#include "adump_dsmi.h"
14- 
15-namespace Adx {
16-void DumpCore::DumpRegister(uint8_t coreType, uint16_t coreId)
17-{
18- uint32_t platform = 0;
19- IDE_CTRL_VALUE_FAILED(AdumpDsmi::DrvGetPlatformType(platform), return, "Get platform type failed");
20- switch (static_cast<PlatformType>(platform)) {
21- case PlatformType::CHIP_CLOUD_V2:
22- DumpV2Register(coreType, coreId);
23- break;
24- case PlatformType::CHIP_CLOUD_V4:
25- DumpV4Register(coreType, coreId);
26- break;
27- default:
28- break;
29- }
30-}
31- 
32-void DumpCore::DumpV4Register(uint8_t coreType, uint16_t coreId)
33-{
34- std::vector<RegInfoWide> regData;
35- std::string sectionName = ASCEND_SHNAME_REGS + "." + std::to_string(ConvertCoreId(coreType, coreId));
36- std::shared_ptr<RegisterInterface> reg = RegisterManager::GetInstance().GetRegister();
37- IDE_CTRL_VALUE_FAILED(reg != nullptr, return, "Get register failed, null register.");
38- for (const auto &regType: reg->GetRegisterTypes(coreType)) {
39- DumpV4DebugRegister(coreType, coreId, reg->GetRegisterTable(regType), regData);
40- }
41- 
42- size_t totalSize = regData.size() * sizeof(RegInfoWide);
43- std::string data(reinterpret_cast<const char *>(regData.data()), totalSize);
44- ELF::SectionPtr registerSection = coreFile_.AddSection(ASCEND_SHTYPE_REGS, sectionName);
45- IDE_CTRL_VALUE_FAILED(registerSection != nullptr, return, "Create %s section failed.", sectionName.c_str());
46- registerSection->SetData(data);
47- registerSection->SetEntSize(sizeof(RegInfoWide));
48-}
49- 
50-void DumpCore::DumpV4DebugRegister(uint8_t coreType, uint16_t coreId, const std::vector<RegisterTable> &tables,
51- std::vector<RegInfoWide> &regData) const
52-{
53- std::string data;
54- std::stringstream ss;
55- ss << "v4 Debug register data. coreType:" << static_cast<int32_t>(coreType) << ", coreId:" << coreId << ".";
56- bool dataValid = true;
57- for (const RegisterTable &table : tables) {
58- dataValid = DumpReadDebugAICoreRegister(coreType, coreId, table, data);
59- errno_t err = EOK;
60- const char *dataPtr = data.data();
61- for (uint32_t i = 0; i < table.num; ++i) {
62- RegInfoWide regInfo{table.startAddr + i, REG_DATA_VALID, {0}, table.byteWith, {0}};
63- if (dataValid) {
64- err = memcpy_s(&regInfo.value, sizeof(regInfo.value), dataPtr, table.byteWith);
65- if (err != EOK) {
66- IDE_LOGE("Failed to copy v4 debug register data from cache buffer. "
67- "coreType: %hhu, coreId: %hu, addr: 0x%llx, ret: %d",
68- coreType, coreId, regInfo.addr, err);
69- regInfo.validFlag = REG_DATA_INVALID;
70- } else {
71- std::string value = FormatRegisterData(regInfo.value, regInfo.regSize);
72- ss << " 0x" << std::hex << regInfo.addr << ": " << value << ",";
73- }
74- } else {
75- regInfo.validFlag = REG_DATA_INVALID;
76- }
77- dataPtr += table.byteWith;
78- regData.emplace_back(regInfo);
79- }
80- }
81- IDE_LOGI("%s", ss.str().c_str());
82-}
83- 
84-uint16_t DumpCore::ConvertCoreId(uint8_t coreType, uint16_t coreId) const
85-{
86- uint32_t platform = 0;
87- (void)AdumpDsmi::DrvGetPlatformType(platform);
88- switch (static_cast<PlatformType>(platform)) {
89- case PlatformType::CHIP_CLOUD_V2:
90- return (coreType == CORE_TYPE_AIC) ? coreId : static_cast<uint16_t>(CORE_SIZE_AIC + coreId);
91- case PlatformType::CHIP_CLOUD_V4:
92- return (coreType == CORE_TYPE_AIC) ? coreId : static_cast<uint16_t>(CORE_SIZE_AIC_DAVID + coreId);
93- default:
94- break;
95- }
96- return coreId;
97-}
98-} // namespace Adx
Msrc/dfx/adump/adump/exception/dump_core/dump_core.cpp+21-7
@@ -295,6 +295,7 @@ int32_t DumpCore::D2HMemcpyWithCheck(const GlobalMemInfo &memInfo, std::string &
295 295 
296int32_t DumpCore::ProcessGlobalMemory(GlobalMemInfo &memInfo, std::vector<GlobalMemInfo> &memInfoList, bool checkAddr)296int32_t DumpCore::ProcessGlobalMemory(GlobalMemInfo &memInfo, std::vector<GlobalMemInfo> &memInfoList, bool checkAddr)
297{297{
298+ IDE_LOGI("Dump device data. data type: %hu, addr: 0x%llx, size: %llu", memInfo.type, memInfo.devAddr, memInfo.size);
298 std::string curData(memInfo.size, 0);299 std::string curData(memInfo.size, 0);
299 if (memInfo.size != 0) {300 if (memInfo.size != 0) {
300 if (checkAddr) {301 if (checkAddr) {
@@ -416,21 +417,34 @@ void DumpCore::DumpWorkSpace(const DumpArgs &args, std::vector<GlobalMemInfo> &m
416void DumpCore::DumpStack(const rtBinHandle &binHandle, std::vector<GlobalMemInfo> &memInfoList)417void DumpCore::DumpStack(const rtBinHandle &binHandle, std::vector<GlobalMemInfo> &memInfoList)
417{418{
418 for (uint16_t aicId : aiCoreIds_) {419 for (uint16_t aicId : aiCoreIds_) {
419- DumpCoreStack(binHandle, CORE_TYPE_AIC, aicId, memInfoList);420+ IDE_LOGI("Dump core stack data. coreType: aic, coreId: %hu", aicId);
421+ DumpCoreStack(
422+ binHandle, CORE_TYPE_AIC, aicId, false, RT_STACK_TYPE_SCALAR, DfxTensorType::STACK, memInfoList);
423+ DumpCoreStack(
424+ binHandle, CORE_TYPE_AIC, aicId, true, RT_STACK_TYPE_SIMT, DfxTensorType::SIMT_STACK, memInfoList);
420 }425 }
421 for (uint16_t aivId : aiVectorCoreIds_) {426 for (uint16_t aivId : aiVectorCoreIds_) {
422- DumpCoreStack(binHandle, CORE_TYPE_AIV, aivId, memInfoList);427+ IDE_LOGI("Dump core stack data. coreType: aiv, coreId: %hu", aivId);
428+ DumpCoreStack(
429+ binHandle, CORE_TYPE_AIV, aivId, false, RT_STACK_TYPE_SCALAR, DfxTensorType::STACK, memInfoList);
430+ DumpCoreStack(
431+ binHandle, CORE_TYPE_AIV, aivId, true, RT_STACK_TYPE_SIMT, DfxTensorType::SIMT_STACK, memInfoList);
423 }432 }
424}433}
425 434 
426-void DumpCore::DumpCoreStack(const rtBinHandle &binHandle, uint8_t coreType, uint16_t coreId,435+void DumpCore::DumpCoreStack(const rtBinHandle& binHandle, const uint8_t coreType, const uint16_t coreId,
436+ bool checkAddr, const rtStackType_t rtStackType, DfxTensorType dumpStackType,
427 std::vector<GlobalMemInfo> &memInfoList)437 std::vector<GlobalMemInfo> &memInfoList)
428{438{
429 const void *stackAddr = nullptr;439 const void *stackAddr = nullptr;
430 uint32_t stackSize = 0;440 uint32_t stackSize = 0;
431- rtError_t rtRet = rtGetStackBuffer(binHandle, 0U, RT_STACK_TYPE_SCALAR, coreType, coreId, &stackAddr, &stackSize);441+ rtError_t rtRet = rtGetStackBuffer(binHandle, 0U, rtStackType, coreType, coreId, &stackAddr, &stackSize);
442+ if (rtRet == ACL_ERROR_RT_FEATURE_NOT_SUPPORT) {
443+ IDE_LOGW("RTS does not support rtGetStackBuffer feature. stackType: %d, ret: %d", rtStackType, rtRet);
444+ return;
445+ }
432 if ((rtRet != RT_ERROR_NONE) || (stackAddr == nullptr)) {446 if ((rtRet != RT_ERROR_NONE) || (stackAddr == nullptr)) {
433- IDE_LOGE("Call rtGetStackBuffer to get stack data failed, coreType: %hhu coreId: %hu, ret: %d",447+ IDE_LOGE("Call rtGetStackBuffer to get stack data failed, coreType: %hhu, coreId: %hu, ret: %d",
434 coreType, coreId, static_cast<int32_t>(rtRet));448 coreType, coreId, static_cast<int32_t>(rtRet));
435 return;449 return;
436 }450 }
@@ -438,12 +452,12 @@ void DumpCore::DumpCoreStack(const rtBinHandle &binHandle, uint8_t coreType, uin
438 .devAddr = reinterpret_cast<uint64_t>(stackAddr),452 .devAddr = reinterpret_cast<uint64_t>(stackAddr),
439 .size = stackSize,453 .size = stackSize,
440 .sectionIndex = 0,454 .sectionIndex = 0,
441- .type = DfxTensorType::STACK,455+ .type = dumpStackType,
442 .reserve = 0,456 .reserve = 0,
443 .extraInfo = {.coreInfo = {ConvertCoreId(coreType, coreId)}}457 .extraInfo = {.coreInfo = {ConvertCoreId(coreType, coreId)}}
444 };458 };
445 459 
446- int32_t ret = ProcessGlobalMemory(memInfo, memInfoList, false);460+ int32_t ret = ProcessGlobalMemory(memInfo, memInfoList, checkAddr);
447 IDE_CTRL_VALUE_FAILED(ret == ADUMP_SUCCESS, return,461 IDE_CTRL_VALUE_FAILED(ret == ADUMP_SUCCESS, return,
448 "Save stack section failed, core type: %hhu, core id: %hu", coreType, coreId);462 "Save stack section failed, core type: %hhu, core id: %hu", coreType, coreId);
449 463 
Msrc/dfx/adump/adump/exception/dump_core/dump_core.h+54-41
@@ -30,9 +30,9 @@ const std::string DEFAULT_KERNEL_NAME("unknow_kernel");
30 30 
31class DumpCore {31class DumpCore {
32public:32public:
33- explicit DumpCore(const std::string &path, uint32_t devId) : path_(path), devId_(devId) {};33+ explicit DumpCore(const std::string& path, uint32_t devId) : path_(path), devId_(devId) {};
34 ~DumpCore() = default;34 ~DumpCore() = default;
35- int32_t DumpCoreFile(const rtExceptionInfo &exception);35+ int32_t DumpCoreFile(const rtExceptionInfo& exception);
36 36 
37private:37private:
38 struct CacheParam {38 struct CacheParam {
@@ -43,54 +43,67 @@ private:
43 uint32_t sectionIndex;43 uint32_t sectionIndex;
44 rtDebugMemoryType_t cacheType;44 rtDebugMemoryType_t cacheType;
45 CacheParam() : coreType(0), coreId(0), memSize(0), memAddr(0), sectionIndex(0), cacheType(RT_MEM_TYPE_MAX) {}45 CacheParam() : coreType(0), coreId(0), memSize(0), memAddr(0), sectionIndex(0), cacheType(RT_MEM_TYPE_MAX) {}
46- CacheParam(uint8_t type, uint16_t id, uint64_t size, uint64_t addr, uint32_t index,46+ CacheParam(uint8_t type, uint16_t id, uint64_t size, uint64_t addr, uint32_t index, rtDebugMemoryType_t memType)
47- rtDebugMemoryType_t memType) : coreType(type), coreId(id), memSize(size), memAddr(addr),47+ : coreType(type), coreId(id), memSize(size), memAddr(addr), sectionIndex(index), cacheType(memType)
48- sectionIndex(index), cacheType(memType) {}48+ {}
49 };49 };
50 50 
51 void DumpCoreInfo(uint32_t devId);51 void DumpCoreInfo(uint32_t devId);
52 52 
53- void DumpGlobalMemory(const rtExceptionInfo &exception);53+ void DumpGlobalMemory(const rtExceptionInfo& exception);
54- int32_t ProcessGlobalMemory(GlobalMemInfo &memInfo, std::vector<GlobalMemInfo> &memInfoList, bool checkAddr = true);54+ int32_t ProcessGlobalMemory(GlobalMemInfo& memInfo, std::vector<GlobalMemInfo>& memInfoList, bool checkAddr = true);
55- void DumpArgsInfo(const rtExceptionArgsInfo_t &exceptionArgsInfo, std::vector<GlobalMemInfo> &memInfoList);55+ void DumpArgsInfo(const rtExceptionArgsInfo_t& exceptionArgsInfo, std::vector<GlobalMemInfo>& memInfoList);
56- void DumpInput(const DumpArgs &args, std::vector<GlobalMemInfo> &memInfoList);56+ void DumpInput(const DumpArgs& args, std::vector<GlobalMemInfo>& memInfoList);
57- void DumpTensorBuffer(const DumpArgs &args, std::vector<GlobalMemInfo> &memInfoList);57+ void DumpTensorBuffer(const DumpArgs& args, std::vector<GlobalMemInfo>& memInfoList);
58- void DumpWorkSpace(const DumpArgs &args, std::vector<GlobalMemInfo> &memInfoList);58+ void DumpWorkSpace(const DumpArgs& args, std::vector<GlobalMemInfo>& memInfoList);
59- void DumpStack(const rtBinHandle &binHandle, std::vector<GlobalMemInfo> &memInfoList);59+ void DumpStack(const rtBinHandle& binHandle, std::vector<GlobalMemInfo>& memInfoList);
60- void DumpCoreStack(const rtBinHandle &binHandle, uint8_t coreType, uint16_t coreId,60+ void DumpCoreStack(const rtBinHandle& binHandle, const uint8_t coreType, const uint16_t coreId, bool checkAddr,
61- std::vector<GlobalMemInfo> &memInfoList);61+ const rtStackType_t rtStackType, DfxTensorType dumpStackType, std::vector<GlobalMemInfo> &memInfoList);
62- void DumpHostKernelBin(const rtExceptionKernelInfo_t &kernelInfo);62+ void DumpHostKernelBin(const rtExceptionKernelInfo_t& kernelInfo);
63- void DumpDeviceKernelBin(const rtExceptionKernelInfo_t &kernelInfo, std::vector<GlobalMemInfo> &memInfoList);63+ void DumpDeviceKernelBin(const rtExceptionKernelInfo_t& kernelInfo, std::vector<GlobalMemInfo>& memInfoList);
64- void DumpHostFile(const rtExceptionArgsInfo_t &argsInfo);64+ void DumpHostFile(const rtExceptionArgsInfo_t& argsInfo);
65- void DumpHostFile(const std::string &filePath, uint32_t sectionType, const std::string &sectionName);65+ void DumpHostFile(const std::string& filePath, uint32_t sectionType, const std::string& sectionName);
66- void DumpKernelInfo(const std::string &kernelName);66+ void DumpKernelInfo(const std::string& kernelName);
67- void DumpGlobalAuxInfo(const std::vector<GlobalMemInfo> &memInfoList);67+ void DumpGlobalAuxInfo(const std::vector<GlobalMemInfo>& memInfoList);
68- int32_t D2HMemcpyWithCheck(const GlobalMemInfo &memInfo, std::string &data) const;68+ int32_t D2HMemcpyWithCheck(const GlobalMemInfo& memInfo, std::string& data) const;
69- int32_t D2HMemcpyWithNoCheck(const GlobalMemInfo &memInfo, std::string &data) const;69+ int32_t D2HMemcpyWithNoCheck(const GlobalMemInfo& memInfo, std::string& data) const;
70 void DumpResourceInit();70 void DumpResourceInit();
71 void DumpLocalMemory(uint8_t coreType, uint16_t coreId);71 void DumpLocalMemory(uint8_t coreType, uint16_t coreId);
72- void DumpCache(uint8_t coreType, uint16_t coreId, const std::string &sectionName,72+ void DumpCache(
73- std::vector<LocalMemInfo> &localMemInfoList);73+ uint8_t coreType, uint16_t coreId, const std::string& sectionName, std::vector<LocalMemInfo>& localMemInfoList);
74- void DumpCache(uint8_t coreType, uint16_t coreId, const CacheParam &cacheParam, const std::string &sectionName,74+ void DumpCache(
75- std::vector<LocalMemInfo> &localMemInfoList);75+ uint8_t coreType, uint16_t coreId, const CacheParam& cacheParam, const std::string& sectionName,
76- void DumpBuffer(uint8_t coreType, uint16_t coreId, const std::string &sectionName,76+ std::vector<LocalMemInfo>& localMemInfoList);
77- std::vector<LocalMemInfo> &localMemInfoList);77+ void DumpBuffer(
78- void DumpLocalAuxInfo(const std::string &coreIdStr, std::vector<LocalMemInfo> &localMemInfoList);78+ uint8_t coreType, uint16_t coreId, const std::string& sectionName, std::vector<LocalMemInfo>& localMemInfoList);
79+ void DumpLocalAuxInfo(const std::string& coreIdStr, std::vector<LocalMemInfo>& localMemInfoList);
79 void DumpRegister(uint8_t coreType, uint16_t coreId);80 void DumpRegister(uint8_t coreType, uint16_t coreId);
80 void DumpV2Register(uint8_t coreType, uint16_t coreId);81 void DumpV2Register(uint8_t coreType, uint16_t coreId);
81- void DumpV2DebugRegister(uint8_t coreType, uint16_t coreId, const std::vector<RegisterTable> &tables,82+ void DumpV2DebugRegister(
82- std::vector<RegInfo> &regData) const;83+ uint8_t coreType, uint16_t coreId, const std::vector<RegisterTable>& tables,
83- void DumpV2ErrorRegister(uint8_t coreType, uint16_t coreId, const std::vector<ErrorRegisterTable> &tables,84+ std::vector<RegInfo>& regData) const;
84- std::vector<RegInfo> &regData) const;85+ void DumpV2ErrorRegister(
86+ uint8_t coreType, uint16_t coreId, const std::vector<ErrorRegisterTable>& tables,
87+ std::vector<RegInfo>& regData) const;
85 void DumpV4Register(uint8_t coreType, uint16_t coreId);88 void DumpV4Register(uint8_t coreType, uint16_t coreId);
86- void DumpV4DebugRegister(uint8_t coreType, uint16_t coreId, const std::vector<RegisterTable> &tables,89+ void DumpV4DebugRegister(
87- std::vector<RegInfoWide> &regData) const;90+ uint8_t coreType, uint16_t coreId, const std::vector<RegisterTable>& tables,
88- bool DumpReadDebugAICoreRegister(uint8_t coreType, uint16_t coreId, const RegisterTable &table,91+ std::vector<RegInfoWide>& regData) const;
89- std::string &data) const;92+ void DumpV4ErrorRegister(
90- std::string FormatRegisterData(const uint8_t *valAddr, uint8_t valSize) const;93+ uint8_t coreType, uint16_t coreId, const std::vector<ErrorRegisterTable>& tables,
94+ std::vector<RegInfoWide>& regData) const;
95+ bool DumpReadDebugAICoreRegister(
96+ uint8_t coreType, uint16_t coreId, const RegisterTable& table, std::vector<uint8_t>& data) const;
97+ std::string FormatRegisterData(const uint8_t* valAddr, uint8_t valSize) const;
98+ template <typename T>
99+ void DumpDebugRegisterImpl(
100+ uint8_t coreType, uint16_t coreId, const std::vector<RegisterTable>& tables, std::vector<T>& regData) const;
101+ template <typename T>
102+ void DumpErrorRegisterImpl(
103+ uint8_t coreType, uint16_t coreId, const std::vector<ErrorRegisterTable>& tables,
104+ std::vector<T>& regData) const;
91 uint16_t ConvertCoreId(uint8_t coreType, uint16_t coreId) const;105 uint16_t ConvertCoreId(uint8_t coreType, uint16_t coreId) const;
92- void SaveCoreFile(const rtExceptionInfo &exception);106+ void SaveCoreFile(const rtExceptionInfo& exception);
93- 
94 std::string path_;107 std::string path_;
95 uint32_t devId_;108 uint32_t devId_;
96 ELF::DumpELF coreFile_;109 ELF::DumpELF coreFile_;
@@ -104,5 +117,5 @@ private:
104 std::vector<CacheParam> stackParamList_;117 std::vector<CacheParam> stackParamList_;
105 ExceptionRegInfo exceptionRegInfo_{0, nullptr};118 ExceptionRegInfo exceptionRegInfo_{0, nullptr};
106};119};
107-} // namespace Adx120+} // namespace Adx
108#endif121#endif
Dsrc/dfx/adump/adump/exception/dump_core/dump_core_platform.cpp+0-41
@@ -1,41 +0,0 @@
1-/**
2-  * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3-  * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4-  * CANN Open Software License Agreement Version 2.0 (the "License").
5-  * Please refer to the License for details. You may not use this file except in compliance with the License.
6-  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7-  * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8-  * See LICENSE in the root of the software repository for the full text of the License.
9-  */
10-#include "dump_core.h"
11-#include "log/adx_log.h"
12-#include "adump_dsmi.h"
13- 
14-namespace Adx {
15- 
16-void DumpCore::DumpRegister(uint8_t coreType, uint16_t coreId)
17-{
18- uint32_t platform = 0;
19- IDE_CTRL_VALUE_FAILED(AdumpDsmi::DrvGetPlatformType(platform), return, "Get platform type failed.");
20- switch (static_cast<PlatformType>(platform)) {
21- case PlatformType::CHIP_CLOUD_V2:
22- DumpV2Register(coreType, coreId);
23- break;
24- default:
25- break;
26- }
27-}
28- 
29-uint16_t DumpCore::ConvertCoreId(uint8_t coreType, uint16_t coreId) const
30-{
31- uint32_t platform = 0;
32- (void)AdumpDsmi::DrvGetPlatformType(platform);
33- switch (static_cast<PlatformType>(platform)) {
34- case PlatformType::CHIP_CLOUD_V2:
35- return (coreType == CORE_TYPE_AIC) ? coreId : static_cast<uint16_t>(CORE_SIZE_AIC + coreId);
36- default:
37- break;
38- }
39- return coreId;
40-}
41-} // namespace Adx
Msrc/dfx/adump/adump/exception/dump_core/dump_core_register.cpp+156-73
@@ -17,118 +17,201 @@
17#include "dump_core.h"17#include "dump_core.h"
18 18 
19namespace Adx {19namespace Adx {
20-constexpr int32_t REG_FIELD_WIDTH = 2;20+constexpr int32_t REG_FIELD_WIDTH = 2;
21 21 
22-std::string DumpCore::FormatRegisterData(const uint8_t *valAddr, uint8_t valSize) const22+void DumpCore::DumpRegister(uint8_t coreType, uint16_t coreId)
23+{
24+ uint32_t platform = 0;
25+ IDE_CTRL_VALUE_FAILED(AdumpDsmi::DrvGetPlatformType(platform), return, "Get platform type failed.");
26+ switch (static_cast<PlatformType>(platform)) {
27+ case PlatformType::CHIP_CLOUD_V2:
28+ DumpV2Register(coreType, coreId);
29+ break;
30+ case PlatformType::CHIP_CLOUD_V4:
31+ DumpV4Register(coreType, coreId);
32+ break;
33+ default:
34+ break;
35+ }
36+}
37+ 
38+std::string DumpCore::FormatRegisterData(const uint8_t* valAddr, uint8_t valSize) const
23{39{
24 std::stringstream ss;40 std::stringstream ss;
25 ss << std::hex << std::setfill('0');41 ss << std::hex << std::setfill('0');
26 for (uint8_t i = 0; i < valSize; ++i) {42 for (uint8_t i = 0; i < valSize; ++i) {
27- ss << " " << std::setw(REG_FIELD_WIDTH) << static_cast<uint32_t>(valAddr[i]);43+ ss << std::setw(REG_FIELD_WIDTH) << static_cast<uint32_t>(valAddr[i]);
28 }44 }
29 return ss.str();45 return ss.str();
30}46}
31 47 
32-bool DumpCore::DumpReadDebugAICoreRegister(uint8_t coreType, uint16_t coreId, const RegisterTable &table,48+bool DumpCore::DumpReadDebugAICoreRegister(
33- std::string &data) const49+ uint8_t coreType, uint16_t coreId, const RegisterTable& table, std::vector<uint8_t>& data) const
34{50{
35- data.clear();51+ data.resize(table.num * table.byteWidth);
36- data.reserve(table.num * table.byteWith);
37 rtDebugMemoryParam_t param = {coreType, 0, coreId, RT_MEM_TYPE_REGISTER, 0, 0, 0, 0, 0};52 rtDebugMemoryParam_t param = {coreType, 0, coreId, RT_MEM_TYPE_REGISTER, 0, 0, 0, 0, 0};
38 param.srcAddr = table.startAddr;53 param.srcAddr = table.startAddr;
39 param.dstAddr = reinterpret_cast<uint64_t>(data.data());54 param.dstAddr = reinterpret_cast<uint64_t>(data.data());
40- param.memLen = table.num * table.byteWith;55+ param.memLen = table.num * table.byteWidth;
41- param.elementSize = table.byteWith;56+ param.elementSize = table.byteWidth;
42 rtError_t ret = rtDebugReadAICore(&param);57 rtError_t ret = rtDebugReadAICore(&param);
43 if (ret != RT_ERROR_NONE) {58 if (ret != RT_ERROR_NONE) {
44- IDE_LOGE("Failed to read debug register data. coreType: %hhu, coreId: %hu, start addr: 0x%llx, "59+ IDE_LOGE(
45- "num: %u, byteWith: %hhu, ret: %d",60+ "Failed to read debug register data. coreType: %hhu, coreId: %hu, start addr: 0x%llx, "
46- coreType, coreId, param.srcAddr, table.num, table.byteWith, static_cast<int32_t>(ret));61+ "num: %u, byteWidth: %hhu, ret: %d",
62+ coreType, coreId, param.srcAddr, table.num, table.byteWidth, static_cast<int32_t>(ret));
47 return false;63 return false;
48 }64 }
49 return true;65 return true;
50}66}
51 67 
68+template <typename T>
69+void DumpCore::DumpDebugRegisterImpl(
70+ uint8_t coreType, uint16_t coreId, const std::vector<RegisterTable>& tables, std::vector<T>& regData) const
71+{
72+ std::stringstream ss;
73+ for (const RegisterTable& table : tables) {
74+ std::vector<uint8_t> data;
75+ bool dataValid = DumpReadDebugAICoreRegister(coreType, coreId, table, data);
76+ errno_t err = EOK;
77+ const uint8_t* dataPtr = data.data();
78+ for (uint32_t i = 0; i < table.num; ++i) {
79+ T regInfo{table.startAddr + i, REG_DATA_VALID, {0}, table.byteWidth, {0}};
80+ if (dataValid) {
81+ err = memcpy_s(&regInfo.value, sizeof(regInfo.value), dataPtr, table.byteWidth);
82+ if (err != EOK) {
83+ IDE_LOGE("Failed to copy debug register data from cache buffer. "
84+ "coreType: %hhu, coreId: %hu, addr: 0x%llx, ret: %d",
85+ coreType, coreId, regInfo.addr, err);
86+ regInfo.validFlag = REG_DATA_INVALID;
87+ } else {
88+ std::string value = FormatRegisterData(regInfo.value, regInfo.regSize);
89+ ss << " 0x" << std::hex << regInfo.addr << ": " << value << ",";
90+ }
91+ } else {
92+ regInfo.validFlag = REG_DATA_INVALID;
93+ }
94+ dataPtr += table.byteWidth;
95+ regData.emplace_back(regInfo);
96+ }
97+ }
98+ std::string dataStr = ss.str();
99+ if (!dataStr.empty()) {
100+ IDE_LOGW("Debug register data. coreType=%d, coreId=%d.%s",
101+ static_cast<int32_t>(coreType), coreId, dataStr.c_str());
102+ }
103+}
104+ 
105+template <typename T>
106+void DumpCore::DumpErrorRegisterImpl(
107+ uint8_t coreType, uint16_t coreId, const std::vector<ErrorRegisterTable>& tables, std::vector<T>& regData) const
108+{
109+ std::stringstream ss;
110+ std::vector<std::string> regLogs;
111+ for (uint32_t i = 0; i < exceptionRegInfo_.coreNum; i++) {
112+ rtExceptionErrRegInfo_t core = exceptionRegInfo_.errRegInfo[i];
113+ if (coreId != core.coreId || coreType != core.coreType) {
114+ continue;
115+ }
116+ for (const auto& table : tables) {
117+ T regInfo{table.offsetAddr, REG_DATA_VALID, {0}, table.byteWidth, {0}};
118+ errno_t err = memcpy_s(&regInfo.value, sizeof(regInfo.value), core.errReg + table.errIndex, table.byteWidth);
119+ if (err != EOK) {
120+ IDE_LOGE("Failed to copy error register data from exception args. "
121+ "coreType: %hhu, coreId: %hu, addr: 0x%llx, ret: %d",
122+ coreType, coreId, regInfo.addr, err);
123+ regInfo.validFlag = REG_DATA_INVALID;
124+ } else {
125+ std::string value = FormatRegisterData(regInfo.value, regInfo.regSize);
126+ ss << table.name << "[0x" << std::hex << regInfo.addr << "]: " << value << ",";
127+ }
128+ regData.emplace_back(regInfo);
129+ }
130+ }
131+ std::string dataStr = ss.str();
132+ if (!dataStr.empty()) {
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Yyring_84月16日

字符串过长，可能打印不全，建议分片打印

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133+ IDE_LOGW("Error register data. coreType=%d, coreId=%d. %s",
134+ static_cast<int32_t>(coreType), coreId, dataStr.c_str());
135+ }
136+}
137+ 
52void DumpCore::DumpV2Register(uint8_t coreType, uint16_t coreId)138void DumpCore::DumpV2Register(uint8_t coreType, uint16_t coreId)
53{139{
54 std::vector<RegInfo> regData;140 std::vector<RegInfo> regData;
55 std::string sectionName = ASCEND_SHNAME_REGS + "." + std::to_string(ConvertCoreId(coreType, coreId));141 std::string sectionName = ASCEND_SHNAME_REGS + "." + std::to_string(ConvertCoreId(coreType, coreId));
56 std::shared_ptr<RegisterInterface> reg = RegisterManager::GetInstance().GetRegister();142 std::shared_ptr<RegisterInterface> reg = RegisterManager::GetInstance().GetRegister();
57 IDE_CTRL_VALUE_FAILED(reg != nullptr, return, "Get register failed, null register.");143 IDE_CTRL_VALUE_FAILED(reg != nullptr, return, "Get register failed, null register.");
58- for (const auto &regType : reg->GetRegisterTypes(coreType)) {144+ for (const auto& regType : reg->GetRegisterTypes(coreType)) {
59 DumpV2DebugRegister(coreType, coreId, reg->GetRegisterTable(regType), regData);145 DumpV2DebugRegister(coreType, coreId, reg->GetRegisterTable(regType), regData);
60 }146 }
61 DumpV2ErrorRegister(coreType, coreId, reg->GetErrorRegisterTable(), regData);147 DumpV2ErrorRegister(coreType, coreId, reg->GetErrorRegisterTable(), regData);
62 148 
63 size_t totalSize = regData.size() * sizeof(RegInfo);149 size_t totalSize = regData.size() * sizeof(RegInfo);
64- std::string data(reinterpret_cast<const char *>(regData.data()), totalSize);150+ std::string data(reinterpret_cast<const char*>(regData.data()), totalSize);
65 ELF::SectionPtr registerSection = coreFile_.AddSection(ASCEND_SHTYPE_REGS, sectionName);151 ELF::SectionPtr registerSection = coreFile_.AddSection(ASCEND_SHTYPE_REGS, sectionName);
66 IDE_CTRL_VALUE_FAILED(registerSection != nullptr, return, "Create %s section failed.", sectionName.c_str());152 IDE_CTRL_VALUE_FAILED(registerSection != nullptr, return, "Create %s section failed.", sectionName.c_str());
67 registerSection->SetData(data);153 registerSection->SetData(data);
68 registerSection->SetEntSize(sizeof(RegInfo));154 registerSection->SetEntSize(sizeof(RegInfo));
69}155}
70 156 
71-void DumpCore::DumpV2DebugRegister(uint8_t coreType, uint16_t coreId, const std::vector<RegisterTable> &tables,157+void DumpCore::DumpV2DebugRegister(
72- std::vector<RegInfo> &regData) const158+ uint8_t coreType, uint16_t coreId, const std::vector<RegisterTable>& tables, std::vector<RegInfo>& regData) const
73{159{
74- std::string data;160+ DumpDebugRegisterImpl(coreType, coreId, tables, regData);
75- std::stringstream ss;
76- ss << "Debug register data. coreType:" << static_cast<int32_t>(coreType) << ", coreId:" << coreId << ".";
77- bool dataValid = true;
78- for (const RegisterTable &table : tables) {
79- dataValid = DumpReadDebugAICoreRegister(coreType, coreId, table, data);
80- errno_t err = EOK;
81- const char *dataPtr = data.data();
82- for (uint32_t i = 0; i < table.num; ++i) {
83- RegInfo regInfo{table.startAddr + i, REG_DATA_VALID, {0}, table.byteWith, {0}};
84- if (dataValid) {
85- err = memcpy_s(&regInfo.value, sizeof(regInfo.value), dataPtr, table.byteWith);
86- if (err != EOK) {
87- IDE_LOGE("Failed to copy debug register data from cache buffer. "
88- "coreType: %hhu, coreId: %hu, addr: 0x%llx, ret: %d",
89- coreType, coreId, regInfo.addr, err);
90- regInfo.validFlag = REG_DATA_INVALID;
91- } else {
92- std::string value = FormatRegisterData(regInfo.value, regInfo.regSize);
93- ss << " 0x" << std::hex << regInfo.addr << ":" << value << ",";
94- }
95- } else {
96- regInfo.validFlag = REG_DATA_INVALID;
97- }
98- regData.emplace_back(regInfo);
99- dataPtr += table.byteWith;
100- }
101- }
102- IDE_LOGW("%s", ss.str().c_str());
103}161}
104 162 
105-void DumpCore::DumpV2ErrorRegister(uint8_t coreType, uint16_t coreId, const std::vector<ErrorRegisterTable> &tables,163+void DumpCore::DumpV2ErrorRegister(
106- std::vector<RegInfo> &regData) const164+ uint8_t coreType, uint16_t coreId, const std::vector<ErrorRegisterTable>& tables,
165+ std::vector<RegInfo>& regData) const
107{166{
108- errno_t err = EOK;167+ DumpErrorRegisterImpl(coreType, coreId, tables, regData);
109- std::stringstream ss;
110- ss << "Error register data. coreType=" << static_cast<int32_t>(coreType) << ", coreId=" << coreId << ".";
111- for (uint32_t i = 0; i < exceptionRegInfo_.coreNum; i++) {
112- rtExceptionErrRegInfo_t coreErrRegInfo = exceptionRegInfo_.errRegInfo[i];
113- if (coreId != coreErrRegInfo.coreId || coreType != coreErrRegInfo.coreType) {
114- continue;
115- }
116- for (const ErrorRegisterTable &table: tables) {
117- RegInfo regInfo{table.offsetAddr, REG_DATA_VALID, {0}, table.byteWidth, {0}};
118- err = memcpy_s(&regInfo.value, sizeof(regInfo.value), coreErrRegInfo.errReg + table.errIndex,
119- table.byteWidth);
120- if (err != EOK) {
121- IDE_LOGE("Failed to copy error register data from exception args. "
122- "coreType: %hhu, coreId: %hu, addr: 0x%llx, ret: %d",
123- coreType, coreId, regInfo.addr, err);
124- regInfo.validFlag = REG_DATA_INVALID;
125- } else {
126- std::string value = FormatRegisterData(regInfo.value, regInfo.regSize);
127- ss << " " << table.name << "[0x" << std::hex << regInfo.addr << "]: " << value << ",";
128- }
129- regData.emplace_back(regInfo);
130- }
131- }
132- IDE_LOGW("%s", ss.str().c_str());
133}168}
134-} // namespace Adx169+ 
170+void DumpCore::DumpV4Register(uint8_t coreType, uint16_t coreId)
Y
Yyring_84月16日

DumpV4Register与DumpV2Register相似度高，可以提取公共部分

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171+{
172+ std::vector<RegInfoWide> regData;
173+ std::string sectionName = ASCEND_SHNAME_REGS + "." + std::to_string(ConvertCoreId(coreType, coreId));
174+ std::shared_ptr<RegisterInterface> reg = RegisterManager::GetInstance().GetRegister();
175+ IDE_CTRL_VALUE_FAILED(reg != nullptr, return, "Get register failed, null register.");
176+ for (const auto& regType : reg->GetRegisterTypes(coreType)) {
177+ DumpV4DebugRegister(coreType, coreId, reg->GetRegisterTable(regType), regData);
178+ }
179+ DumpV4ErrorRegister(coreType, coreId, reg->GetErrorRegisterTable(), regData);
180+ 
181+ size_t totalSize = regData.size() * sizeof(RegInfoWide);
182+ std::string data(reinterpret_cast<const char*>(regData.data()), totalSize);
183+ ELF::SectionPtr registerSection = coreFile_.AddSection(ASCEND_SHTYPE_REGS, sectionName);
184+ IDE_CTRL_VALUE_FAILED(registerSection != nullptr, return, "Create %s section failed.", sectionName.c_str());
185+ registerSection->SetData(data);
186+ registerSection->SetEntSize(sizeof(RegInfoWide));
187+}
188+ 
189+void DumpCore::DumpV4DebugRegister(
190+ uint8_t coreType, uint16_t coreId, const std::vector<RegisterTable>& tables,
191+ std::vector<RegInfoWide>& regData) const
192+{
193+ DumpDebugRegisterImpl(coreType, coreId, tables, regData);
194+}
195+ 
196+void DumpCore::DumpV4ErrorRegister(
197+ uint8_t coreType, uint16_t coreId, const std::vector<ErrorRegisterTable>& tables,
198+ std::vector<RegInfoWide>& regData) const
199+{
200+ DumpErrorRegisterImpl(coreType, coreId, tables, regData);
201+}
202+ 
203+uint16_t DumpCore::ConvertCoreId(uint8_t coreType, uint16_t coreId) const
204+{
205+ uint32_t platform = 0;
206+ IDE_CTRL_VALUE_FAILED(AdumpDsmi::DrvGetPlatformType(platform), return coreId, "Get platform type failed.");
207+ switch (static_cast<PlatformType>(platform)) {
208+ case PlatformType::CHIP_CLOUD_V2:
209+ return (coreType == CORE_TYPE_AIC) ? coreId : static_cast<uint16_t>(CORE_SIZE_AIC + coreId);
210+ case PlatformType::CHIP_CLOUD_V4:
211+ return (coreType == CORE_TYPE_AIC) ? coreId : static_cast<uint16_t>(CORE_SIZE_AIC_DAVID + coreId);
212+ default:
213+ break;
214+ }
215+ return coreId;
216+}
217+} // namespace Adx
Msrc/dfx/adump/adump/exception/kernel_info_collector.cpp+0-6
@@ -374,12 +374,6 @@ int32_t KernelInfoCollector::CollectKernelFile(const std::string &kernelName, co
374 374 
375int32_t KernelInfoCollector::GetExceptionRegInfo(const rtExceptionInfo &exception, ExceptionRegInfo &exceptionRegInfo)375int32_t KernelInfoCollector::GetExceptionRegInfo(const rtExceptionInfo &exception, ExceptionRegInfo &exceptionRegInfo)
376{376{
377- uint32_t platform = 0;
378- IDE_CTRL_VALUE_FAILED(AdumpDsmi::DrvGetPlatformType(platform), return ADUMP_FAILED, "Get platform type failed.");
379- if (static_cast<PlatformType>(platform) != PlatformType::CHIP_CLOUD_V2) {
380- IDE_LOGW("Not support to get error register information from RTS.");
381- return ADUMP_FAILED;
382- }
383 rtError_t rtRet = rtGetExceptionRegInfo(&exception, &exceptionRegInfo.errRegInfo, &exceptionRegInfo.coreNum);377 rtError_t rtRet = rtGetExceptionRegInfo(&exception, &exceptionRegInfo.errRegInfo, &exceptionRegInfo.coreNum);
384 IDE_CTRL_VALUE_FAILED(rtRet == RT_ERROR_NONE, return ADUMP_FAILED,378 IDE_CTRL_VALUE_FAILED(rtRet == RT_ERROR_NONE, return ADUMP_FAILED,
385 "Call rtGetExceptionRegInfo for error register information failed. ret: %d", static_cast<int32_t>(rtRet));379 "Call rtGetExceptionRegInfo for error register information failed. ret: %d", static_cast<int32_t>(rtRet));
Dsrc/dfx/adump/adump/exception/register_config/close/register_config_platform.cpp+0-32
@@ -1,32 +0,0 @@
1-/**
2- * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3- * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4- * CANN Open Software License Agreement Version 2.0 (the "License").
5- * Please refer to the License for details. You may not use this file except in compliance with the License.
6- * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7- * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8- * See LICENSE in the root of the software repository for the full text of the License.
9- */
10- 
11-#include "register_config.h"
12-#include "adump_dsmi.h"
13- 
14-namespace Adx {
15-void RegisterManager::CreateRegister()
16-{
17- uint32_t type = 0;
18- if (!AdumpDsmi::DrvGetPlatformType(type)) {
19- return;
20- }
21- switch (static_cast<PlatformType>(type)) {
22- case PlatformType::CHIP_CLOUD_V2:
23- register_ = std::make_shared<CloudV2Register>();
24- break;
25- case PlatformType::CHIP_CLOUD_V4:
26- register_ = std::make_shared<CloudV4Register>();
27- break;
28- default:
29- break;
30- }
31-}
32-}
Msrc/dfx/adump/adump/exception/register_config/register_config.cpp+130-66
@@ -11,19 +11,21 @@
11#include "runtime/base.h"11#include "runtime/base.h"
12#include "dump_common.h"12#include "dump_common.h"
13#include "register_config.h"13#include "register_config.h"
14+#include "acc_error_info.h"
15+#include "adump_dsmi.h"
14 16 
15namespace Adx {17namespace Adx {
16 18 
17const std::vector<RegisterTable>& RegisterInterface::GetRegisterTable(RegisterType type) const19const std::vector<RegisterTable>& RegisterInterface::GetRegisterTable(RegisterType type) const
18{20{
19 static std::vector<RegisterTable> defaultTables = {};21 static std::vector<RegisterTable> defaultTables = {};
20- return registerTableMap_.find(type) != registerTableMap_.end() ? registerTableMap_.at(type): defaultTables;22+ return registerTableMap_.find(type) != registerTableMap_.end() ? registerTableMap_.at(type) : defaultTables;
21}23}
22 24 
23const std::vector<RegisterType>& RegisterInterface::GetRegisterTypes(uint8_t coreType) const25const std::vector<RegisterType>& RegisterInterface::GetRegisterTypes(uint8_t coreType) const
24{26{
25 static std::vector<RegisterType> defaultTypes = {};27 static std::vector<RegisterType> defaultTypes = {};
26- return registerTypeMap_.find(coreType) != registerTypeMap_.end() ? registerTypeMap_.at(coreType): defaultTypes;28+ return registerTypeMap_.find(coreType) != registerTypeMap_.end() ? registerTypeMap_.at(coreType) : defaultTypes;
27}29}
28 30 
29const std::vector<ErrorRegisterTable>& RegisterInterface::GetErrorRegisterTable() const31const std::vector<ErrorRegisterTable>& RegisterInterface::GetErrorRegisterTable() const
@@ -34,98 +36,160 @@ const std::vector<ErrorRegisterTable>& RegisterInterface::GetErrorRegisterTable(
34CloudV2Register::CloudV2Register()36CloudV2Register::CloudV2Register()
35{37{
36 registerTableMap_ = {38 registerTableMap_ = {
37- {RegisterType::SU, {{GetAddr(0, 0), 32, 8}, // GPR0 - GPR3139+ {RegisterType::SU,
38- {GetAddr(0, 64), 1, 8}, // PC40+ {{GetAddr(0, 0), 32, 8}, // GPR0 - GPR31
39- {GetAddr(0, 66), 8, 8}, // 66-7341+ {GetAddr(0, 64), 1, 8}, // PC
40- {GetAddr(0, 75), 4, 8}, // 75-7842+ {GetAddr(0, 66), 8, 8}, // 66-73
41- {GetAddr(0, 128), 12, 8}}}, // 128-13943+ {GetAddr(0, 75), 4, 8}, // 75-78
42- {RegisterType::VEC, {{GetAddr(256, 0), 2, 16}, // MASK CMPMASK44+ {GetAddr(0, 128), 12, 8}}}, // 128-139
43- {GetAddr(256, 2), 14, 8}, // 2-1545+ {RegisterType::VEC,
44- {GetAddr(257, 0), 8, 16}}}, // VARF0 - VARF746+ {{GetAddr(256, 0), 2, 16}, // MASK CMPMASK
45- {RegisterType::MTE, {{GetAddr(515, 0), 17, 8}, // 0-1647+ {GetAddr(256, 2), 14, 8}, // 2-15
46- {GetAddr(515, 23), 25, 8}}}, // AIPP_SPR_0 - AIPP_SPR_2448+ {GetAddr(257, 0), 8, 16}}}, // VARF0 - VARF7
47- {RegisterType::CUBE, {{GetAddr(768, 0), 1, 8}, // LOW_PRE_TBL49+ {RegisterType::MTE,
48- {GetAddr(768, 0x2000), 1, 8}, // SMASK_INDEX50+ {{GetAddr(515, 0), 17, 8}, // 0-16
49- {GetAddr(768, 0x4000), 1, 8}}}, // FIXP_PRE_BUF51+ {GetAddr(515, 23), 25, 8}}}, // AIPP_SPR_0 - AIPP_SPR_24
52+ {RegisterType::CUBE,
53+ {{GetAddr(768, 0), 1, 8}, // LOW_PRE_TBL
54+ {GetAddr(768, 0x2000), 1, 8}, // SMASK_INDEX
55+ {GetAddr(768, 0x4000), 1, 8}}}, // FIXP_PRE_BUF
50 };56 };
51- registerTypeMap_ = {57+ registerTypeMap_ = {
52 {CORE_TYPE_AIC, {RegisterType::SU, RegisterType::MTE, RegisterType::CUBE, RegisterType::BIU}},58 {CORE_TYPE_AIC, {RegisterType::SU, RegisterType::MTE, RegisterType::CUBE, RegisterType::BIU}},
53- {CORE_TYPE_AIV, {RegisterType::SU, RegisterType::VEC, RegisterType::BIU}}59+ {CORE_TYPE_AIV, {RegisterType::SU, RegisterType::VEC, RegisterType::BIU}}};
54- };
55 ErrorRegisterMap_ = {60 ErrorRegisterMap_ = {
56- {RT_V100_AIC_ERR_0, 0x00000700, 4, "AIC_ERROR_0"},61+ {RT_V100_AIC_ERR_0, 0x00000700, 4, "AIC_ERROR_0"}, {RT_V100_AIC_ERR_1, 0x00000704, 4, "AIC_ERROR_1"},
57- {RT_V100_AIC_ERR_1, 0x00000704, 4, "AIC_ERROR_1"},62+ {RT_V100_AIC_ERR_2, 0x00000760, 4, "AIC_ERROR_2"}, {RT_V100_AIC_ERR_3, 0x00000764, 4, "AIC_ERROR_3"},
58- {RT_V100_AIC_ERR_2, 0x00000760, 4, "AIC_ERROR_2"},63+ {RT_V100_AIC_ERR_4, 0x00000780, 4, "AIC_ERROR_4"}, {RT_V100_AIC_ERR_5, 0x00000790, 4, "AIC_ERROR_5"},
59- {RT_V100_AIC_ERR_3, 0x00000764, 4, "AIC_ERROR_3"},64+ {RT_V100_BIU_ERR_0, 0x00000710, 4, "BIU_ERR_INFO_0"}, {RT_V100_BIU_ERR_1, 0x00000714, 4, "BIU_ERR_INFO_1"},
60- {RT_V100_AIC_ERR_4, 0x00000780, 4, "AIC_ERROR_4"},65+ {RT_V100_CCU_ERR_0, 0x00000718, 4, "CCU_ERR_INFO_0"}, {RT_V100_CCU_ERR_1, 0x0000071C, 4, "CCU_ERR_INFO_1"},
61- {RT_V100_AIC_ERR_5, 0x00000790, 4, "AIC_ERROR_5"},66+ {RT_V100_IFU_ERR_0, 0x00000728, 4, "IFU_ERR_INFO_0"}, {RT_V100_IFU_ERR_1, 0x0000072C, 4, "IFU_ERR_INFO_1"},
62- {RT_V100_BIU_ERR_0, 0x00000710, 4, "BIU_ERR_INFO_0"},67+ {RT_V100_MTE_ERR_0, 0x00000730, 4, "MTE_ERR_INFO_0"}, {RT_V100_MTE_ERR_1, 0x00000734, 4, "MTE_ERR_INFO_1"},
63- {RT_V100_BIU_ERR_1, 0x00000714, 4, "BIU_ERR_INFO_1"},68+ {RT_V100_VEC_ERR_0, 0x00000738, 4, "VEC_ERR_INFO_0"}, {RT_V100_VEC_ERR_1, 0x0000073C, 4, "VEC_ERR_INFO_1"},
64- {RT_V100_CCU_ERR_0, 0x00000718, 4, "CCU_ERR_INFO_0"},69+ {RT_V100_FIXP_ERR_0, 0x0000078C, 4, "FIXP_ERR_INFO_0"}, {RT_V100_FIXP_ERR_1, 0x000007C8, 4, "FIXP_ERR_INFO_1"},
65- {RT_V100_CCU_ERR_1, 0x0000071C, 4, "CCU_ERR_INFO_1"},
66- {RT_V100_IFU_ERR_0, 0x00000728, 4, "IFU_ERR_INFO_0"},
67- {RT_V100_IFU_ERR_1, 0x0000072C, 4, "IFU_ERR_INFO_1"},
68- {RT_V100_MTE_ERR_0, 0x00000730, 4, "MTE_ERR_INFO_0"},
69- {RT_V100_MTE_ERR_1, 0x00000734, 4, "MTE_ERR_INFO_1"},
70- {RT_V100_VEC_ERR_0, 0x00000738, 4, "VEC_ERR_INFO_0"},
71- {RT_V100_VEC_ERR_1, 0x0000073C, 4, "VEC_ERR_INFO_1"},
72- {RT_V100_FIXP_ERR_0, 0x0000078C, 4, "FIXP_ERR_INFO_0"},
73- {RT_V100_FIXP_ERR_1, 0x000007C8, 4, "FIXP_ERR_INFO_1"},
74 {RT_V100_CUBE_ERR_0, 0x00000720, 4, "CUBE_ERR_INFO"},70 {RT_V100_CUBE_ERR_0, 0x00000720, 4, "CUBE_ERR_INFO"},
75 };71 };
76}72}
77 73 
78-uint64_t CloudV2Register::GetAddr(uint64_t regAddrHigh, uint64_t regAddrLow) const {74+uint64_t CloudV2Register::GetAddr(uint64_t regAddrHigh, uint64_t regAddrLow) const
75+{
79 return (regAddrHigh << HIGH_ADDR_SHIFT) | regAddrLow;76 return (regAddrHigh << HIGH_ADDR_SHIFT) | regAddrLow;
80}77}
81 78 
82CloudV4Register::CloudV4Register()79CloudV4Register::CloudV4Register()
83{80{
84 registerTableMap_ = {81 registerTableMap_ = {
85- {RegisterType::SU, {82+ {RegisterType::SU,
86- {GetAddr(1, 0, 0), 32, 8}, {GetAddr(1, 0, 64), 15, 8}, {GetAddr(1, 0, 128), 10, 8},83+ {{GetAddr(1, 0, 0), 32, 8},
87- {GetAddr(1, 5, 0), 1, 8}, {GetAddr(1, 5, 0x800000000000), 1, 8}, {GetAddr(1, 6, 0), 1, 8},84+ {GetAddr(1, 0, 64), 15, 8},
88- {GetAddr(1, 6, 0x800000000000), 1, 8}}},85+ {GetAddr(1, 0, 128), 10, 8},
89- {RegisterType::MTE, {86+ {GetAddr(1, 5, 0), 1, 8},
90- {GetAddr(2, 1, 0), 1, 8}, {GetAddr(2, 2, 0), 2, 8}, {GetAddr(2, 2, 3), 4, 8},87+ {GetAddr(1, 5, 0x800000000000), 1, 8},
91- {GetAddr(2, 2, 0x12), 1, 8}, {GetAddr(2, 2, 0x14), 1, 8}}},88+ {GetAddr(1, 6, 0), 1, 8},
92- {RegisterType::MTE_AIV, {89+ {GetAddr(1, 6, 0x800000000000), 1, 8}}},
93- {GetAddr(2, 1, 0), 1, 8}, {GetAddr(2, 2, 2), 1, 8}, {GetAddr(2, 2, 7), 3, 8},90+ {RegisterType::MTE,
94- {GetAddr(2, 2, 13), 3, 8}, {GetAddr(2, 2, 0x16), 9, 8}}},91+ {{GetAddr(2, 1, 0), 1, 8},
95- {RegisterType::VEC_RB, {92+ {GetAddr(2, 2, 0), 2, 8},
96- {GetAddr(3, 2, 0x600), 4, 32}, {GetAddr(3, 2, 0x800), 4, 32}, {GetAddr(3, 2, 0x804), 4, 8},93+ {GetAddr(2, 2, 3), 4, 8},
97- {GetAddr(3, 2, 0xA00), 64, 8}, {GetAddr(3, 2, 0xC00), 8, 16}, {GetAddr(3, 2, 0xE00), 8, 8},94+ {GetAddr(2, 2, 0x12), 1, 8},
98- {GetAddr(3, 2, 0x1200), 1, 16}, {GetAddr(3, 2, 0x1600), 1, 8}, {GetAddr(3, 2, 0x1800), 1, 8},95+ {GetAddr(2, 2, 0x14), 1, 8}}},
99- {GetAddr(3, 2, 0x1A00), 1, 32}, {GetAddr(3, 2, 0x1C00), 1, 8}, {GetAddr(3, 2, 0x1E00), 1, 8},96+ {RegisterType::MTE_AIV,
100- {GetAddr(3, 2, 0x2000), 64, 8}, {GetAddr(3, 2, 0x2200), 4, 8}, {GetAddr(3, 9, 0), 5, 8},97+ {{GetAddr(2, 1, 0), 1, 8},
101- {GetAddr(3, 9, 0x4000), 1, 8}, {GetAddr(3, 9, 0x8000), 1, 32}, {GetAddr(3, 9, 0xC000), 1, 32},98+ {GetAddr(2, 2, 2), 1, 8},
102- {GetAddr(3, 9, 0x10000), 1, 32}, {GetAddr(3, 9, 0x14000), 1, 32}, {GetAddr(3, 9, 0x18000), 1, 8},99+ {GetAddr(2, 2, 7), 3, 8},
103- {GetAddr(3, 9, 0x1C000), 1, 8}}},100+ {GetAddr(2, 2, 13), 3, 8},
101+ {GetAddr(2, 2, 0x16), 9, 8}}},
102+ {RegisterType::VEC_RB,
103+ {{GetAddr(3, 2, 0x600), 4, 32}, {GetAddr(3, 2, 0x800), 4, 32}, {GetAddr(3, 2, 0x804), 4, 8},
104+ {GetAddr(3, 2, 0xA00), 64, 8}, {GetAddr(3, 2, 0xC00), 8, 16}, {GetAddr(3, 2, 0xE00), 8, 8},
105+ {GetAddr(3, 2, 0x1200), 1, 16}, {GetAddr(3, 2, 0x1600), 1, 8}, {GetAddr(3, 2, 0x1800), 1, 8},
106+ {GetAddr(3, 2, 0x1A00), 1, 32}, {GetAddr(3, 2, 0x1C00), 1, 8}, {GetAddr(3, 2, 0x1E00), 1, 8},
107+ {GetAddr(3, 2, 0x2000), 64, 8}, {GetAddr(3, 2, 0x2200), 4, 8}, {GetAddr(3, 9, 0), 5, 8},
108+ {GetAddr(3, 9, 0x4000), 1, 8}, {GetAddr(3, 9, 0x8000), 1, 32}, {GetAddr(3, 9, 0xC000), 1, 32},
109+ {GetAddr(3, 9, 0x10000), 1, 32}, {GetAddr(3, 9, 0x14000), 1, 32}, {GetAddr(3, 9, 0x18000), 1, 8},
110+ {GetAddr(3, 9, 0x1C000), 1, 8}}},
104 {RegisterType::CUBE, {}},111 {RegisterType::CUBE, {}},
105- {RegisterType::L1, {{GetAddr(6, 0, 0), 10, 8},{GetAddr(6, 1, 0), 10, 8}, {GetAddr(6, 7, 0), 1, 8}}},112+ {RegisterType::L1, {{GetAddr(6, 0, 0), 10, 8}, {GetAddr(6, 1, 0), 10, 8}, {GetAddr(6, 7, 0), 1, 8}}},
106 };113 };
107- GenAddrByStep(RegisterType::VEC_RB,114+ GenAddrByStep(RegisterType::VEC_RB, {{GetAddr(3, 2, 0), 32, 32, 16}, {GetAddr(3, 2, 0x200), 8, 32, 2}});
108- {{GetAddr(3, 2, 0), 32, 32, 16}, {GetAddr(3, 2, 0x200), 8, 32, 2}});115+ registerTypeMap_ = {
109- registerTypeMap_ = {
110 {CORE_TYPE_AIC, {RegisterType::SU, RegisterType::MTE, RegisterType::CUBE, RegisterType::BIF, RegisterType::L1}},116 {CORE_TYPE_AIC, {RegisterType::SU, RegisterType::MTE, RegisterType::CUBE, RegisterType::BIF, RegisterType::L1}},
111- {CORE_TYPE_AIV, {RegisterType::SU, RegisterType::MTE_AIV, RegisterType::VEC_RB, RegisterType::BIF}}117+ {CORE_TYPE_AIV, {RegisterType::SU, RegisterType::MTE_AIV, RegisterType::VEC_RB, RegisterType::BIF}}};
118+ InitErrorRegisterMap();
119+}
120+ 
121+void CloudV4Register::InitErrorRegisterMap()
122+{
123+ ErrorRegisterMap_ = {
124+ {RT_V200_SC_ERROR_T0_0, 0x4700, 4, "SC_ERROR_T0_0"},
125+ {RT_V200_SC_ERR_INFO_T0_0, 0x4730, 4, "SC_ERR_INFO_T0_0"},
126+ {RT_V200_SC_ERR_INFO_T0_1, 0x4734, 4, "SC_ERR_INFO_T0_1"},
127+ {RT_V200_SU_ERROR_T0_0, 0x5700, 4, "SU_ERROR_T0_0"},
128+ {RT_V200_SU_ERR_INFO_T0_0, 0x5730, 4, "SU_ERR_INFO_T0_0"},
129+ {RT_V200_SU_ERR_INFO_T0_1, 0x5734, 4, "SU_ERR_INFO_T0_1"},
130+ {RT_V200_SU_ERR_INFO_T0_2, 0x5738, 4, "SU_ERR_INFO_T0_2"},
131+ {RT_V200_SU_ERR_INFO_T0_3, 0x573C, 4, "SU_ERR_INFO_T0_3"},
132+ {RT_V200_MTE_ERROR_T0_0, 0x6700, 4, "MTE_ERROR_T0_0"},
133+ {RT_V200_MTE_ERROR_T1_0, 0x6708, 4, "MTE_ERROR_T1_0"},
134+ {RT_V200_MTE_ERR_INFO_T0_0, 0x6718, 4, "MTE_ERR_INFO_T0_0"},
135+ {RT_V200_MTE_ERR_INFO_T0_1, 0x671C, 4, "MTE_ERR_INFO_T0_1"},
136+ {RT_V200_MTE_ERR_INFO_T0_2, 0x6720, 4, "MTE_ERR_INFO_T0_2"},
137+ {RT_V200_MTE_ERR_INFO_T1_0, 0x6724, 4, "MTE_ERR_INFO_T1_0"},
138+ {RT_V200_MTE_ERR_INFO_T1_1, 0x6728, 4, "MTE_ERR_INFO_T1_1"},
139+ {RT_V200_MTE_ERR_INFO_T1_2, 0x673C, 4, "MTE_ERR_INFO_T1_2"},
140+ {RT_V200_VEC_ERROR_T0_0, 0x7700, 4, "VEC_ERROR_T0_0"},
141+ {RT_V200_VEC_ERROR_T0_2, 0x7708, 4, "VEC_ERROR_T0_2"},
142+ {RT_V200_VEC_ERR_INFO_T0_0, 0x7730, 4, "VEC_ERR_INFO_T0_0"},
143+ {RT_V200_VEC_ERR_INFO_T0_1, 0x7734, 4, "VEC_ERR_INFO_T0_1"},
144+ {RT_V200_VEC_ERR_INFO_T0_2, 0x7738, 4, "VEC_ERR_INFO_T0_2"},
145+ {RT_V200_VEC_ERR_INFO_T0_3, 0x773C, 4, "VEC_ERR_INFO_T0_3"},
146+ {RT_V200_VEC_ERR_INFO_T0_4, 0x7740, 4, "VEC_ERR_INFO_T0_4"},
147+ {RT_V200_VEC_ERR_INFO_T0_5, 0x7744, 4, "VEC_ERR_INFO_T0_5"},
148+ {RT_V200_CUBE_ERROR_T0_0, 0x8700, 4, "CUBE_ERROR_T0_0"},
149+ {RT_V200_CUBE_ERROR_T0_1, 0x8710, 4, "CUBE_ERROR_T0_1"},
150+ {RT_V200_CUBE_ERR_INFO_T0_0, 0x8730, 4, "CUBE_ERR_INFO_T0_0"},
151+ {RT_V200_CUBE_ERR_INFO_T0_1, 0x8734, 4, "CUBE_ERR_INFO_T0_1"},
152+ {RT_V200_L1_ERROR_T0_0, 0xA700, 4, "L1_ERROR_T0_0"},
153+ {RT_V200_L1_ERROR_T0_1, 0xA704, 4, "L1_ERROR_T0_1"},
154+ {RT_V200_L1_ERR_INFO_T0_0, 0xA718, 4, "L1_ERR_INFO_T0_0"},
155+ {RT_V200_L1_ERR_INFO_T0_1, 0xA71C, 4, "L1_ERR_INFO_T0_1"},
112 };156 };
113}157}
114 158 
115-uint64_t CloudV4Register::GetAddr(uint64_t type, uint64_t regAddrHigh, uint64_t regAddrLow) const {159+uint64_t CloudV4Register::GetAddr(uint64_t type, uint64_t regAddrHigh, uint64_t regAddrLow) const
160+{
116 return (type << MOUDLE_TYPE_SHIFT) | (regAddrHigh << HIGH_ADDR_SHIFT) | regAddrLow;161 return (type << MOUDLE_TYPE_SHIFT) | (regAddrHigh << HIGH_ADDR_SHIFT) | regAddrLow;
117}162}
118 163 
119-void CloudV4Register::GenAddrByStep(RegisterType regType, const std::vector<RegisterStepTable> &regStepTab){164+void CloudV4Register::GenAddrByStep(RegisterType regType, const std::vector<RegisterStepTable>& regStepTab)
120- for (const auto &stepTable: regStepTab){165+{
166+ for (const auto& stepTable : regStepTab) {
121 uint64_t curStartAddr = stepTable.startAddr;167 uint64_t curStartAddr = stepTable.startAddr;
122- for (uint32_t i = 0; i < stepTable.num; i++){168+ for (uint32_t i = 0; i < stepTable.num; i++) {
123- registerTableMap_[regType].emplace_back(curStartAddr, 1, stepTable.byteWith);169+ registerTableMap_[regType].emplace_back(curStartAddr, 1, stepTable.byteWidth);
124 curStartAddr += stepTable.step;170 curStartAddr += stepTable.step;
125 }171 }
126 }172 }
127}173}
128 174 
175+void RegisterManager::CreateRegister()
176+{
177+ uint32_t type = 0;
178+ if (!AdumpDsmi::DrvGetPlatformType(type)) {
179+ return;
180+ }
181+ switch (static_cast<PlatformType>(type)) {
182+ case PlatformType::CHIP_CLOUD_V2:
183+ register_ = std::make_shared<CloudV2Register>();
184+ break;
185+ case PlatformType::CHIP_CLOUD_V4:
186+ register_ = std::make_shared<CloudV4Register>();
187+ break;
188+ default:
189+ break;
190+ }
191+}
192+ 
129RegisterManager::RegisterManager()193RegisterManager::RegisterManager()
130{194{
131 CreateRegister();195 CreateRegister();
Msrc/dfx/adump/adump/exception/register_config/register_config.h+4-3
@@ -26,16 +26,16 @@ constexpr uint32_t MOUDLE_TYPE_SHIFT = 52U;
26 26 
27struct RegisterTable {27struct RegisterTable {
28 RegisterTable(uint64_t regStartAddr, uint32_t regNum, uint8_t regByteWidth):28 RegisterTable(uint64_t regStartAddr, uint32_t regNum, uint8_t regByteWidth):
29- startAddr(regStartAddr), num(regNum), byteWith(regByteWidth) {}29+ startAddr(regStartAddr), num(regNum), byteWidth(regByteWidth) {}
30 uint64_t startAddr;30 uint64_t startAddr;
31 uint32_t num;31 uint32_t num;
32- uint8_t byteWith;32+ uint8_t byteWidth;
33};33};
34 34 
35struct RegisterStepTable {35struct RegisterStepTable {
36 uint64_t startAddr;36 uint64_t startAddr;
37 uint32_t num;37 uint32_t num;
38- uint8_t byteWith;38+ uint8_t byteWidth;
39 uint8_t step;39 uint8_t step;
40};40};
41 41 
@@ -88,6 +88,7 @@ public:
88private:88private:
89 uint64_t GetAddr(uint64_t type, uint64_t regAddrHigh, uint64_t regAddrLow) const;89 uint64_t GetAddr(uint64_t type, uint64_t regAddrHigh, uint64_t regAddrLow) const;
90 void GenAddrByStep(RegisterType regType, const std::vector<RegisterStepTable> &regStepTab);90 void GenAddrByStep(RegisterType regType, const std::vector<RegisterStepTable> &regStepTab);
91+ void InitErrorRegisterMap();
91};92};
92 93 
93class RegisterManager {94class RegisterManager {
Dsrc/dfx/adump/adump/exception/register_config/register_config_platform.cpp+0-27
@@ -1,27 +0,0 @@
1-/**
2- * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3- * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4- * CANN Open Software License Agreement Version 2.0 (the "License").
5- * Please refer to the License for details. You may not use this file except in compliance with the License.
6- * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7- * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8- * See LICENSE in the root of the software repository for the full text of the License.
9- */
10-#include "log/adx_log.h"
11-#include "adump_dsmi.h"
12-#include "register_config.h"
13- 
14-namespace Adx {
15-void RegisterManager::CreateRegister()
16-{
17- uint32_t type = 0;
18- IDE_CTRL_VALUE_FAILED(AdumpDsmi::DrvGetPlatformType(type), return, "Fail to get platform type.");
19- switch (static_cast<PlatformType>(type)) {
20- case PlatformType::CHIP_CLOUD_V2:
21- register_ = std::make_shared<CloudV2Register>();
22- break;
23- default:
24- break;
25- }
26-}
27-}
Msrc/dfx/adump/inc/adump/adx_exception_callback.h+4-3
@@ -51,9 +51,10 @@ enum class DfxTensorType : uint16_t {
51 OVERFLOW_ADDRESS = 10,51 OVERFLOW_ADDRESS = 10,
52 FFTS_ADDRESS,52 FFTS_ADDRESS,
53 SHAPE_TENSOR,53 SHAPE_TENSOR,
54- ARGS = 101, // args以下为 coredump 新增的，中间预留，从101开始定义54+ ARGS = 101, // args以下为 coredump 新增的，中间预留，从101开始定义
55- STACK = 102,55+ STACK = 102, // scalar算子stack数据
56- DEVICE_KERNEL_OBJECT = 103, //device侧GM中算子.o数据56+ DEVICE_KERNEL_OBJECT = 103, // device侧GM中算子.o数据
57+ SIMT_STACK = 104, // simt算子stack数据
57};58};
58 59 
59/**60/**
Msrc/inc/runtime/acc_error_info.h+2-0
@@ -46,6 +46,8 @@ typedef enum ErrRegInfoIdxV200 {
46 RT_V200_CUBE_ERROR_T0_1,46 RT_V200_CUBE_ERROR_T0_1,
47 RT_V200_L1_ERROR_T0_0,47 RT_V200_L1_ERROR_T0_0,
48 RT_V200_L1_ERROR_T0_1,48 RT_V200_L1_ERROR_T0_1,
49+ RT_V200_SC_ERR_INFO_T0_0,
50+ RT_V200_SC_ERR_INFO_T0_1,
49} rtErrRegInfoIdxV200_t;51} rtErrRegInfoIdxV200_t;
50 52 
51#if defined(__cplusplus)53#if defined(__cplusplus)
Msrc/runtime/core/src/device/v200_base/device_error_proc_c.cc+19-12
@@ -483,19 +483,8 @@ static void ProcessCoreErrorClass(const Device * const dev, const StarsDeviceErr
483 SetDeviceFaultTypeByAixErrClass(dev, info, errTaskPtr);483 SetDeviceFaultTypeByAixErrClass(dev, info, errTaskPtr);
484}484}
485 485 
486-static void AddExceptionRegInfo(const StarsDeviceErrorInfo * const starsInfo, const uint32_t coreIdx,486+static void GetRegInfoErrReg(const DavidOneCoreErrorInfo& info, rtExceptionErrRegInfo_t &regInfo)
487- const uint16_t type, const TaskInfo *errTaskPtr)
488{487{
489- COND_RETURN_NORMAL(type != AICORE_ERROR && type != AIVECTOR_ERROR, "the type[%hu] not match", type);
490- COND_RETURN_VOID(errTaskPtr == nullptr || errTaskPtr->stream == nullptr ||
491- errTaskPtr->stream->Device_() == nullptr, "cannot get the device by errTaskPtr");
492- 
493- const DavidOneCoreErrorInfo& info = starsInfo->u.davidCoreErrorInfo.info[coreIdx];
494- rtExceptionErrRegInfo_t regInfo = {};
495- regInfo.coreId = static_cast<uint32_t>(info.coreId);
496- regInfo.coreType = static_cast<rtCoreType_t>(type);
497- regInfo.startPC = info.pcStart;
498- regInfo.currentPC = info.currentPC;
499 const uint8_t REG_OFFSET = 32;488 const uint8_t REG_OFFSET = 32;
500 regInfo.errReg[RT_V200_SU_ERR_INFO_T0_0] = static_cast<uint32_t>(info.suErrInfo[0]);489 regInfo.errReg[RT_V200_SU_ERR_INFO_T0_0] = static_cast<uint32_t>(info.suErrInfo[0]);
501 regInfo.errReg[RT_V200_SU_ERR_INFO_T0_1] = static_cast<uint32_t>(info.suErrInfo[0] >> REG_OFFSET);490 regInfo.errReg[RT_V200_SU_ERR_INFO_T0_1] = static_cast<uint32_t>(info.suErrInfo[0] >> REG_OFFSET);
@@ -527,6 +516,24 @@ static void AddExceptionRegInfo(const StarsDeviceErrorInfo * const starsInfo, co
527 regInfo.errReg[RT_V200_CUBE_ERROR_T0_1] = static_cast<uint32_t>(info.cubeError >> REG_OFFSET);516 regInfo.errReg[RT_V200_CUBE_ERROR_T0_1] = static_cast<uint32_t>(info.cubeError >> REG_OFFSET);
528 regInfo.errReg[RT_V200_L1_ERROR_T0_0] = static_cast<uint32_t>(info.l1Error);517 regInfo.errReg[RT_V200_L1_ERROR_T0_0] = static_cast<uint32_t>(info.l1Error);
529 regInfo.errReg[RT_V200_L1_ERROR_T0_1] = static_cast<uint32_t>(info.l1Error >> REG_OFFSET);518 regInfo.errReg[RT_V200_L1_ERROR_T0_1] = static_cast<uint32_t>(info.l1Error >> REG_OFFSET);
519+ regInfo.errReg[RT_V200_SC_ERR_INFO_T0_0] = static_cast<uint32_t>(info.scErrInfo);
520+ regInfo.errReg[RT_V200_SC_ERR_INFO_T0_1] = static_cast<uint32_t>(info.scErrInfo >> REG_OFFSET);
521+}
522+ 
523+static void AddExceptionRegInfo(const StarsDeviceErrorInfo * const starsInfo, const uint32_t coreIdx,
524+ const uint16_t type, const TaskInfo *errTaskPtr)
525+{
526+ COND_RETURN_NORMAL(type != AICORE_ERROR && type != AIVECTOR_ERROR, "the type[%hu] not match", type);
527+ COND_RETURN_VOID(errTaskPtr == nullptr || errTaskPtr->stream == nullptr ||
528+ errTaskPtr->stream->Device_() == nullptr, "cannot get the device by errTaskPtr");
529+ 
530+ const DavidOneCoreErrorInfo& info = starsInfo->u.davidCoreErrorInfo.info[coreIdx];
531+ rtExceptionErrRegInfo_t regInfo = {};
532+ regInfo.coreId = static_cast<uint32_t>(info.coreId);
533+ regInfo.coreType = static_cast<rtCoreType_t>(type);
534+ regInfo.startPC = info.pcStart;
535+ regInfo.currentPC = info.currentPC;
536+ GetRegInfoErrReg(info, regInfo);
530 537 
531 Device *dev = errTaskPtr->stream->Device_();538 Device *dev = errTaskPtr->stream->Device_();
532 uint32_t taskSn = errTaskPtr->taskSn;539 uint32_t taskSn = errTaskPtr->taskSn;
Mtests/ut/adump/adump_base/CMakeLists.txt+0-2
@@ -86,9 +86,7 @@ set(adumpBaseSrcList
86 ${SRC_CODE_ROOT_PATH}/adump/exception/dump_ELF.cpp86 ${SRC_CODE_ROOT_PATH}/adump/exception/dump_ELF.cpp
87 ${SRC_CODE_ROOT_PATH}/adump/exception/dump_core/dump_core.cpp87 ${SRC_CODE_ROOT_PATH}/adump/exception/dump_core/dump_core.cpp
88 ${SRC_CODE_ROOT_PATH}/adump/exception/dump_core/dump_core_register.cpp88 ${SRC_CODE_ROOT_PATH}/adump/exception/dump_core/dump_core_register.cpp
89- ${SRC_CODE_ROOT_PATH}/adump/exception/dump_core/dump_core_platform.cpp
90 ${SRC_CODE_ROOT_PATH}/adump/exception/register_config/register_config.cpp89 ${SRC_CODE_ROOT_PATH}/adump/exception/register_config/register_config.cpp
91- ${SRC_CODE_ROOT_PATH}/adump/exception/register_config/register_config_platform.cpp
92 ${SRC_CODE_ROOT_PATH}/adump/exception/exception_info_common.cpp90 ${SRC_CODE_ROOT_PATH}/adump/exception/exception_info_common.cpp
93 ${SRC_CODE_ROOT_PATH}/adump/exception/dump_tensor_plugin.cpp91 ${SRC_CODE_ROOT_PATH}/adump/exception/dump_tensor_plugin.cpp
94 ${SRC_CODE_ROOT_PATH}/adump/exception/adx_exception_callback.cpp92 ${SRC_CODE_ROOT_PATH}/adump/exception/adx_exception_callback.cpp
Mtests/ut/adump/adump_base/testcase/exception/dump_args_utest.cpp+3-1
@@ -37,7 +37,9 @@ using namespace Adx;
37 37 
38class DumpArgsUtest : public testing::Test {38class DumpArgsUtest : public testing::Test {
39protected:39protected:
40- virtual void SetUp() {}40+ virtual void SetUp() {
41+ MOCKER(&Adx::KernelInfoCollector::ParseKernelSymbols).stubs().will(invoke(Adx::ParseKernelSymbolsStub));
42+ }
41 virtual void TearDown()43 virtual void TearDown()
42 {44 {
43 ThreadManager::Instance().WaitAll();45 ThreadManager::Instance().WaitAll();
Mtests/ut/adump/adump_base/testcase/exception/dump_core_utest.cpp+75-15
@@ -25,7 +25,9 @@ using namespace Adx;
25 25 
26class DUMP_CORE_UTEST : public testing::Test {26class DUMP_CORE_UTEST : public testing::Test {
27protected:27protected:
28- virtual void SetUp() {}28+ virtual void SetUp() {
29+ MOCKER(&Adx::KernelInfoCollector::ParseKernelSymbols).stubs().will(invoke(Adx::ParseKernelSymbolsStub));
30+ }
29 virtual void TearDown() {31 virtual void TearDown() {
30 DumpManager::Instance().Reset();32 DumpManager::Instance().Reset();
31 FreeExceptionRegInfo();33 FreeExceptionRegInfo();
@@ -100,25 +102,18 @@ std::vector<uint8_t> GetTensorData(T &tensor)
100 return tensorData;102 return tensorData;
101}103}
102 104 
103-TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP)105+void EnableCoreDump(uint32_t chipType)
104{106{
105- uint32_t type = 5; // CHIP_CLOUD_V2107+ uint32_t type = 5;
106 MOCKER_CPP(&Adx::AdumpDsmi::DrvGetPlatformType).stubs().with(outBound(type)).will(returnValue(true));108 MOCKER_CPP(&Adx::AdumpDsmi::DrvGetPlatformType).stubs().with(outBound(type)).will(returnValue(true));
107- MOCKER(&Adx::KernelInfoCollector::ParseKernelSymbols).stubs().will(invoke(Adx::ParseKernelSymbolsStub));
108- 
109 DumpConfig dumpConf;109 DumpConfig dumpConf;
110 dumpConf.dumpPath = "/tmp/adump_coredump_utest";110 dumpConf.dumpPath = "/tmp/adump_coredump_utest";
111 dumpConf.dumpStatus = "on";111 dumpConf.dumpStatus = "on";
112 EXPECT_EQ(AdumpSetDumpConfig(DumpType::AIC_ERR_DETAIL_DUMP, dumpConf), ADUMP_SUCCESS);112 EXPECT_EQ(AdumpSetDumpConfig(DumpType::AIC_ERR_DETAIL_DUMP, dumpConf), ADUMP_SUCCESS);
113- rtSetDevice(0);113+}
114- rtDeviceReset(0);
115- rtSetDevice(0);
116 114 
117- rtExceptionInfo exceptionInfo = {0};115+void InitCoreDumpExceptionArgs(rtExceptionInfo &exceptionInfo)
118- exceptionInfo.streamid = 1;116+{
119- exceptionInfo.taskid = 1;
120- exceptionInfo.deviceid = 1;
121- exceptionInfo.expandInfo.type = RT_EXCEPTION_AICORE;
122 char fftsAddr[] = "ffts addr";117 char fftsAddr[] = "ffts addr";
123 int32_t tensor[] = {1, 2, 3, 4, 5, 6};118 int32_t tensor[] = {1, 2, 3, 4, 5, 6};
124 float input0[] = {1, 2, 3, 4, 5, 6};119 float input0[] = {1, 2, 3, 4, 5, 6};
@@ -155,8 +150,10 @@ TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP)
155 args[21] = reinterpret_cast<uint64_t>(&shapePtrScalar);150 args[21] = reinterpret_cast<uint64_t>(&shapePtrScalar);
156 exceptionInfo.expandInfo.u.aicoreInfo.exceptionArgs.argAddr = args;151 exceptionInfo.expandInfo.u.aicoreInfo.exceptionArgs.argAddr = args;
157 exceptionInfo.expandInfo.u.aicoreInfo.exceptionArgs.argsize = sizeof(args);152 exceptionInfo.expandInfo.u.aicoreInfo.exceptionArgs.argsize = sizeof(args);
153+}
158 154 
159- std::vector<uint8_t> dfxInfoValue;155+void InitCoreDumpExceptionDfxFftsAddrTensor(std::vector<uint8_t> &dfxInfoValue)
156+{
160 // ffts addr157 // ffts addr
161 std::vector<uint8_t> fftsAddrDfxInfo;158 std::vector<uint8_t> fftsAddrDfxInfo;
162 WithoutSizeTensor fftsAddrTensor = {159 WithoutSizeTensor fftsAddrTensor = {
@@ -164,8 +161,12 @@ TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP)
164 (static_cast<uint16_t>(DfxPointerType::LEVEL_1_POINTER) << POINTER_TYPE_SHIFT_BITS)};161 (static_cast<uint16_t>(DfxPointerType::LEVEL_1_POINTER) << POINTER_TYPE_SHIFT_BITS)};
165 generateDfxInfo(fftsAddrDfxInfo, fftsAddrTensor);162 generateDfxInfo(fftsAddrDfxInfo, fftsAddrTensor);
166 dfxInfoValue.insert(dfxInfoValue.end(), fftsAddrDfxInfo.begin(), fftsAddrDfxInfo.end());163 dfxInfoValue.insert(dfxInfoValue.end(), fftsAddrDfxInfo.begin(), fftsAddrDfxInfo.end());
164+}
167 165 
166+void InitCoreDumpExceptionDfxGeneralTensor(std::vector<uint8_t> &dfxInfoValue)
167+{
168 // general tensor168 // general tensor
169+ int32_t tensor[] = {1, 2, 3, 4, 5, 6};
169 std::vector<uint8_t> tensorDfxInfo;170 std::vector<uint8_t> tensorDfxInfo;
170 StaticL1PointerTensor generalTensor;171 StaticL1PointerTensor generalTensor;
171 generalTensor.argsType = static_cast<uint16_t>(DfxTensorType::GENERAL_TENSOR) |172 generalTensor.argsType = static_cast<uint16_t>(DfxTensorType::GENERAL_TENSOR) |
@@ -175,8 +176,12 @@ TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP)
175 generalTensor.shape = {1, 6};176 generalTensor.shape = {1, 6};
176 generateDfxInfo(tensorDfxInfo, generalTensor);177 generateDfxInfo(tensorDfxInfo, generalTensor);
177 dfxInfoValue.insert(dfxInfoValue.end(), tensorDfxInfo.begin(), tensorDfxInfo.end());178 dfxInfoValue.insert(dfxInfoValue.end(), tensorDfxInfo.begin(), tensorDfxInfo.end());
179+}
178 180 
181+void InitCoreDumpExceptionDfxInputTensor(std::vector<uint8_t> &dfxInfoValue)
182+{
179 // input0183 // input0
184+ float input0[] = {1, 2, 3, 4, 5, 6};
180 std::vector<uint8_t> inputDfxInfo;185 std::vector<uint8_t> inputDfxInfo;
181 StaticL1PointerTensor inputTensor;186 StaticL1PointerTensor inputTensor;
182 inputTensor.argsType = static_cast<uint16_t>(DfxTensorType::INPUT_TENSOR) |187 inputTensor.argsType = static_cast<uint16_t>(DfxTensorType::INPUT_TENSOR) |
@@ -186,18 +191,25 @@ TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP)
186 inputTensor.shape = {2, 3};191 inputTensor.shape = {2, 3};
187 generateDfxInfo(inputDfxInfo, inputTensor);192 generateDfxInfo(inputDfxInfo, inputTensor);
188 dfxInfoValue.insert(dfxInfoValue.end(), inputDfxInfo.begin(), inputDfxInfo.end());193 dfxInfoValue.insert(dfxInfoValue.end(), inputDfxInfo.begin(), inputDfxInfo.end());
194+}
189 195 
196+void InitCoreDumpExceptionDfxOutputTensor(std::vector<uint8_t> &dfxInfoValue)
197+{
190 // output0198 // output0
199+ float output0[] = {2, 4, 6, 8, 10, 12};
191 std::vector<uint8_t> outputDfxInfo;200 std::vector<uint8_t> outputDfxInfo;
192 StaticL1PointerTensor outputTensor;201 StaticL1PointerTensor outputTensor;
193 outputTensor.argsType = static_cast<uint16_t>(DfxTensorType::OUTPUT_TENSOR) |202 outputTensor.argsType = static_cast<uint16_t>(DfxTensorType::OUTPUT_TENSOR) |
194 (static_cast<uint16_t>(DfxPointerType::LEVEL_1_POINTER) << POINTER_TYPE_SHIFT_BITS);203 (static_cast<uint16_t>(DfxPointerType::LEVEL_1_POINTER) << POINTER_TYPE_SHIFT_BITS);
195- outputTensor.size = sizeof(input0);204+ outputTensor.size = sizeof(output0);
196 outputTensor.dim = 2;205 outputTensor.dim = 2;
197 outputTensor.shape = {3, 2};206 outputTensor.shape = {3, 2};
198 generateDfxInfo(outputDfxInfo, outputTensor);207 generateDfxInfo(outputDfxInfo, outputTensor);
199 dfxInfoValue.insert(dfxInfoValue.end(), outputDfxInfo.begin(), outputDfxInfo.end());208 dfxInfoValue.insert(dfxInfoValue.end(), outputDfxInfo.begin(), outputDfxInfo.end());
209+}
200 210 
211+void InitCoreDumpExceptionDfxPlaceholdTensor(std::vector<uint8_t> &dfxInfoValue)
212+{
201 // placehold213 // placehold
202 std::vector<uint8_t> placeholdDfxInfo;214 std::vector<uint8_t> placeholdDfxInfo;
203 StaticL1PointerTensor placeholdTensor;215 StaticL1PointerTensor placeholdTensor;
@@ -208,7 +220,10 @@ TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP)
208 placeholdTensor.shape = {4, 2};220 placeholdTensor.shape = {4, 2};
209 generateDfxInfo(placeholdDfxInfo, placeholdTensor);221 generateDfxInfo(placeholdDfxInfo, placeholdTensor);
210 dfxInfoValue.insert(dfxInfoValue.end(), placeholdDfxInfo.begin(), placeholdDfxInfo.end());222 dfxInfoValue.insert(dfxInfoValue.end(), placeholdDfxInfo.begin(), placeholdDfxInfo.end());
223+}
211 224 
225+void InitCoreDumpExceptionDfxNormalTensor(std::vector<uint8_t> &dfxInfoValue)
226+{
212 // normal pointer227 // normal pointer
213 std::vector<uint8_t> normalPointerDfxInfo;228 std::vector<uint8_t> normalPointerDfxInfo;
214 L2PointerTensor normalPointerTensor;229 L2PointerTensor normalPointerTensor;
@@ -218,7 +233,10 @@ TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP)
218 normalPointerTensor.dataTypeSize = 4;233 normalPointerTensor.dataTypeSize = 4;
219 generateDfxInfo(normalPointerDfxInfo, normalPointerTensor);234 generateDfxInfo(normalPointerDfxInfo, normalPointerTensor);
220 dfxInfoValue.insert(dfxInfoValue.end(), normalPointerDfxInfo.begin(), normalPointerDfxInfo.end());235 dfxInfoValue.insert(dfxInfoValue.end(), normalPointerDfxInfo.begin(), normalPointerDfxInfo.end());
236+}
221 237 
238+void InitCoreDumpExceptionDfxShapePointerTensor(std::vector<uint8_t> &dfxInfoValue)
239+{
222 // shape pointer240 // shape pointer
223 std::vector<uint8_t> shapePointerDfxInfo;241 std::vector<uint8_t> shapePointerDfxInfo;
224 L2PointerTensor shapePointerTensor;242 L2PointerTensor shapePointerTensor;
@@ -229,8 +247,12 @@ TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP)
229 shapePointerTensor.dataTypeSize = 4;247 shapePointerTensor.dataTypeSize = 4;
230 generateDfxInfo(shapePointerDfxInfo, shapePointerTensor);248 generateDfxInfo(shapePointerDfxInfo, shapePointerTensor);
231 dfxInfoValue.insert(dfxInfoValue.end(), shapePointerDfxInfo.begin(), shapePointerDfxInfo.end());249 dfxInfoValue.insert(dfxInfoValue.end(), shapePointerDfxInfo.begin(), shapePointerDfxInfo.end());
250+}
232 251 
252+void InitCoreDumpExceptionDfxWorkspaceTensor(std::vector<uint8_t> &dfxInfoValue)
253+{
233 // workspace254 // workspace
255+ int32_t workspace[] = {100, 100, 100};
234 std::vector<uint8_t> workspaceDfxInfo;256 std::vector<uint8_t> workspaceDfxInfo;
235 WithSizeTensor workspaceTensor = {257 WithSizeTensor workspaceTensor = {
236 static_cast<uint16_t>(DfxTensorType::WORKSPACE_TENSOR) |258 static_cast<uint16_t>(DfxTensorType::WORKSPACE_TENSOR) |
@@ -238,6 +260,29 @@ TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP)
238 sizeof(workspace)};260 sizeof(workspace)};
239 generateDfxInfo(workspaceDfxInfo, workspaceTensor);261 generateDfxInfo(workspaceDfxInfo, workspaceTensor);
240 dfxInfoValue.insert(dfxInfoValue.end(), workspaceDfxInfo.begin(), workspaceDfxInfo.end());262 dfxInfoValue.insert(dfxInfoValue.end(), workspaceDfxInfo.begin(), workspaceDfxInfo.end());
263+}
264+ 
265+void CoreDumpBaseProcess(uint32_t chipType)
266+{
267+ uint32_t type = chipType;
268+ MOCKER_CPP(&Adx::AdumpDsmi::DrvGetPlatformType).stubs().with(outBound(type)).will(returnValue(true));
269+ rtSetDevice(0);
270+ rtDeviceReset(0);
271+ rtSetDevice(0);
272+ 
273+ rtExceptionInfo exceptionInfo = {1, 1, 0, 1, 0, {RT_EXCEPTION_AICORE, {0}}};
274+ // exceptionInfo.expandInfo.type = RT_EXCEPTION_AICORE;
275+ InitCoreDumpExceptionArgs(exceptionInfo);
276+ 
277+ std::vector<uint8_t> dfxInfoValue;
278+ InitCoreDumpExceptionDfxFftsAddrTensor(dfxInfoValue);
279+ InitCoreDumpExceptionDfxGeneralTensor(dfxInfoValue);
280+ InitCoreDumpExceptionDfxInputTensor(dfxInfoValue);
281+ InitCoreDumpExceptionDfxOutputTensor(dfxInfoValue);
282+ InitCoreDumpExceptionDfxPlaceholdTensor(dfxInfoValue);
283+ InitCoreDumpExceptionDfxNormalTensor(dfxInfoValue);
284+ InitCoreDumpExceptionDfxShapePointerTensor(dfxInfoValue);
285+ InitCoreDumpExceptionDfxWorkspaceTensor(dfxInfoValue);
241 286 
242 // total dfxInfo287 // total dfxInfo
243 std::vector<uint8_t> dfxInfo;288 std::vector<uint8_t> dfxInfo;
@@ -274,6 +319,21 @@ TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP)
274 system("rm -r /tmp/adump_coredump_utest");319 system("rm -r /tmp/adump_coredump_utest");
275}320}
276 321 
322+TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP_A2A3)
323+{
324+ // CHIP_CLOUD_V2
325+ uint32_t chipType = 5;
326+ EnableCoreDump(chipType);
327+ CoreDumpBaseProcess(chipType);
328+}
329+ 
330+TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP_A5)
331+{
332+ // CHIP_CLOUD_V4
333+ uint32_t chipType = 15;
334+ CoreDumpBaseProcess(chipType);
335+}
336+ 
277TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP_OLD)337TEST_F(DUMP_CORE_UTEST, TEST_CORE_DUMP_OLD)
278{338{
279 rtExceptionInfo exceptionInfo = {0};339 rtExceptionInfo exceptionInfo = {0};
Mtests/ut/adump/adump_base/testcase/exception/register_config_platform_utest.cpp+0-10
@@ -42,13 +42,3 @@ TEST_F(RegisterManagerPlatformUtest, Test_CreateRegisterNotSupport)
42 registerManager.CreateRegister();42 registerManager.CreateRegister();
43 EXPECT_EQ(registerManager.GetRegister(), nullptr);43 EXPECT_EQ(registerManager.GetRegister(), nullptr);
44}44}
45- 
46-TEST_F(RegisterManagerPlatformUtest, Test_CreateRegisterNotCloudV2)
47-{
48- uint32_t vtype = 15;
49- std::shared_ptr<RegisterInterface> register_;
50- MOCKER_CPP(&Adx::AdumpDsmi::DrvGetPlatformType).stubs().with(outBound(vtype)).will(returnValue(true));
51- RegisterManager registerManager = RegisterManager();
52- registerManager.CreateRegister();
53- EXPECT_EQ(registerManager.GetRegister(), nullptr);
54-}
Mtests/ut/adump/adump_base/testcase/operator/kernel_dfx_dumper_utest.cpp+8-0
@@ -23,10 +23,12 @@
23#include "mmpa_api.h"23#include "mmpa_api.h"
24 24 
25using namespace Adx;25using namespace Adx;
26+INT32 mmSleep_stub(UINT32 millseconds);
26 27 
27class KernelDfxDumperUtest: public testing::Test {28class KernelDfxDumperUtest: public testing::Test {
28protected:29protected:
29 virtual void SetUp() {30 virtual void SetUp() {
31+ MOCKER(mmSleep).stubs().will(invoke(mmSleep_stub));
30 KernelDfxDumper::Instance().UnInit();32 KernelDfxDumper::Instance().UnInit();
31 }33 }
32 virtual void TearDown()34 virtual void TearDown()
@@ -36,6 +38,12 @@ protected:
36 }38 }
37};39};
38 40 
41+INT32 mmSleep_stub(UINT32 millseconds)
42+{
43+ usleep(millseconds * 1000);
44+ return 0;
45+}
46+ 
39TEST_F(KernelDfxDumperUtest, Test_DfxDumper_EnableWithEnv)47TEST_F(KernelDfxDumperUtest, Test_DfxDumper_EnableWithEnv)
40{48{
41 (void)system("rm -rf ./Test_DfxDumper_EnableWithEnv");49 (void)system("rm -rf ./Test_DfxDumper_EnableWithEnv");