| 文件 | 最后提交记录 | 最后更新时间 |
|---|---|---|
tcg: Correct invalid mentions of 'softmmu' by 'system-mode' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004090629.37473-6-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> | 2 年前 | |
tests/tcg/xtensa: fix build for cores without windowed registers Don't try to initialize windowbase/windowstart in crt.S if they don't exist. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 4 年前 | |
tests/tcg/xtensa: update test_fp0_arith for DFPU DFPU arithmetic opcodes update FSR flags. Add FSR parameters and expected FSR register values for the arithmetic tests. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 5 年前 | |
tests/tcg/xtensa: support configurations w/o vecbase Configurations w/o vecbase may have vectors not grouped together and not in fixed order. They may not always be grouped into single output sections by assigning next offset to dot, as it may sometimes move dot backwards and sometimes they may even belong to different memory region. Don't group vectors into single output section. Instead put each vector into its own section ant put it at its default virtual address. Reserve 4KBytes from the default vectors base and put rest of the code and data starting from there. Mark vectors sections as executable, otherwise their contents is discarded. There may be as little as 16 bytes reserved for some vectors, load handler address into a0 and use ret.n to jump there to make vector code fit into this 16 byte space. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: fix test execution on ISS Space for test results may be allocated in IRAM which is only word-accessible. Use full 32-bit words to access test results. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 5 年前 | |
tests/tcg/xtensa: fix endianness issues in test_b Use bbci.l/bbsi.l instead of bbci/bbsi, as they are assembly macros that accept little-endian bit number and produce correct immediate for both little and big endian configurations. Choose value loaded into register for bbc/bbs opcodes based on configuration endianness. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 12 年前 | |
tests/tcg/xtensa: enable boolean tests Uncomment test_boolean in the test makefile. Make actual tests code conditional on the presence of boolean option in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: fix watchpoint test xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't hardcode register numbers in the test as 0 and 1, use macros that only index valid DBREAK* registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 4 年前 | |
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 12 年前 | |
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: add DFP0 arithmetic tests Add test for basic double precision opcode properties. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 5 年前 | |
target/xtensa: implement exclusive access option The Exclusive Instructions provide a general-purpose mechanism for atomic updates of memory-based synchronization variables that can be used for exclusion algorithms. Use cmpxchg-based implementation that is sufficient for the typical use of exclusive access in atomic operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 12 年前 | |
target/xtensa: fix break_dependency for repeated resources break_dependency incorrectly handles the case of dependency on an opcode that references the same register multiple times. E.g. the following instruction is translated incorrectly: { or a2, a3, a3 ; or a3, a2, a2 } This happens because resource indices of both dependency graph nodes are incremented, and a copy for the second instance of the same register in the ending node is not done. Only increment resource index of the ending node of the dependency. Add test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: expand madd tests Test that madd doesn't do rounding after multiplication. Test NaN propagation rules for FPU2000 and DFPU madd opcode. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 5 年前 | |
tests/tcg/xtensa: update test_fp0_conv for DFPU DFPU conversion opcodes update FSR flags. Add FSR parameters and expected FSR register values for the conversion tests. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 5 年前 | |
tests/tcg/xtensa: add fp0 div and sqrt tests Test exact division/sqrt DFPU sequences. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 5 年前 | |
tests/tcg/xtensa: add fp0 div and sqrt tests Test exact division/sqrt DFPU sequences. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 5 年前 | |
tests/tcg/xtensa: update test_fp1 for DFPU DFPU sets Invalid flag in FSR when at least one argument of FP comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole. Add checks for FSR and expected FSR values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 5 年前 | |
tests/tcg/xtensa: add FPU2000 coprocessor tests Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: conditionalize interrupt tests Make interrupt tests conditional on the presence of interrupt option and on the presence of level-1 and high level software interrupts. Don't use hard-coded interrupt level for the high level interrupt tests, choose high level software IRQ and use its configured level. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
target/xtensa: clean up unaligned access Xtensa cores may or may not have hardware support for unaligned memory access. Remove TARGET_ALIGNED_ONLY=y from all xtensa configurations and pass MO_ALIGN in memory access flags for all operations that would raise an exception. Simplify use of gen_load_store_alignment by passing access size and alignment requirements in single parameter. Drop condition from xtensa_cpu_do_unaligned_access and replace it with assertion. Add a test. Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 5 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: test double precision load/store Add ldi[p]/sdi[p]/ldx[p]/sdx[p] opcode tests to test_lsc. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 5 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: enable mmu tests for MMUv3 MMU test suite is disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it make testing region virtual addresses explicit and invalidate TLB mappings for entries that conflict with the test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 4 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3 Autorefill tests in the phys_mem test suite are disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it invalidate TLB mappings for entries that conflict with the test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 4 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: conditionalize and fix s32c1i tests Make s32c1i tests conditional on the presence of this option. Initialize ATOMCTL SR when it's present to allow RCW transactions on uncached memory. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 12 年前 | |
tests/tcg/xtensa: add straightforward conditionals Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 12 年前 | |
tests/tcg/xtensa: restore vecbase SR after test Writing garbage into the vecbase SR results in hang in the subsequent tests that expect to raise an exception. Restore vecbase SR to its reset value after the test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 4 年前 | |
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 4 年前 | |
tests/tcg/xtensa: conditionalize windowed register tests Make windowed register tests conditional on the presence of this option. Fix tests to work correctly for both 32 and 64 physical registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 | |
tests/tcg/xtensa: support configurations w/o vecbase Configurations w/o vecbase may have vectors not grouped together and not in fixed order. They may not always be grouped into single output sections by assigning next offset to dot, as it may sometimes move dot backwards and sometimes they may even belong to different memory region. Don't group vectors into single output section. Instead put each vector into its own section ant put it at its default virtual address. Reserve 4KBytes from the default vectors base and put rest of the code and data starting from there. Mark vectors sections as executable, otherwise their contents is discarded. There may be as little as 16 bytes reserved for some vectors, load handler address into a0 and use ret.n to jump there to make vector code fit into this 16 byte space. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | 7 年前 |
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