TThomas Huthtests/tcg/s390x: Test LOAD ADDRESS EXTENDED
| 文件 | 最后提交记录 | 最后更新时间 |
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target/arm: Handle overflow in calculation of next timer tick In commit edac4d8a168 back in 2015 when we added support for the virtual timer offset CNTVOFF_EL2, we didn't correctly update the timer-recalculation code that figures out when the timer interrupt is next going to change state. We got it wrong in two ways: * for the 0->1 transition, we didn't notice that gt->cval + offset can overflow a uint64_t * for the 1->0 transition, we didn't notice that the transition might now happen before the count rolls over, if offset > count In the former case, we end up trying to set the next interrupt for a time in the past, which results in QEMU hanging as the timer fires continuously. In the latter case, we would fail to update the interrupt status when we are supposed to. Fix the calculations in both cases. The test case is Alex Bennée's from the bug report, and tests the 0->1 transition overflow case. Fixes: edac4d8a168 ("target-arm: Add CNTVOFF_EL2") Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/60 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231120173506.3729884-1-peter.maydell@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 2 年前 | |
tests/tcg/alpha: Add test for cvttq Test for invalid, integer overflow, and inexact. Test for proper result, modulo 2**64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230527141910.1885950-3-richard.henderson@linaro.org> | 3 年前 | |
tests/tcg: enable semiconsole test for Arm This still remains a MANUAL test due to blocking issues. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231120150833.2552739-13-alex.bennee@linaro.org> | 2 年前 | |
tests/tcg: Add -fno-stack-protector A build of GCC 13.2 will have stack protector enabled by default if it was configured with --enable-default-ssp option. For such a compiler, it is necessary to explicitly disable stack protector when linking without standard libraries. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230731091042.139159-3-akihiko.odaki@daynix.com> [AJB: fix comment string typo] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231029145033.592566-3-alex.bennee@linaro.org> | 2 年前 | |
tests/tcg: Add -fno-stack-protector A build of GCC 13.2 will have stack protector enabled by default if it was configured with --enable-default-ssp option. For such a compiler, it is necessary to explicitly disable stack protector when linking without standard libraries. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230731091042.139159-3-akihiko.odaki@daynix.com> [AJB: fix comment string typo] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231029145033.592566-3-alex.bennee@linaro.org> | 2 年前 | |
tests/tcg: limit the scope of the plugin tests Running every plugin with every test is getting excessive as well as not really improving coverage that much. Restrict the plugin tests to just the MULTIARCH_TESTS which are shared between most architecture for both system and user-mode. For those that aren't we need to squash MULTIARCH_TESTS so we don't add them when they are not part of the TESTS global. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230424092249.58552-14-alex.bennee@linaro.org> | 3 年前 | |
target/i386: introduce flags writeback mechanism ALU instructions can write to both memory and flags. If the CC_SRC* and CC_DST locations have been written already when a memory access causes a fault, the value in CC_SRC* and CC_DST might be interpreted with the wrong CC_OP (the one that is in effect before the instruction. Besides just using the wrong result for the flags, something like subtracting -1 can have disastrous effects if the current CC_OP is CC_OP_EFLAGS: this is because QEMU does not expect bits outside the ALU flags to be set in CC_SRC, and env->eflags can end up set to all-ones. In the case of the attached testcase, this sets IOPL to 3 and would cause an assertion failure if SUB is moved to the new decoder. This mechanism is not really needed for BMI instructions, which can only write to a register, but put it to use anyway for cleanliness. In the case of BZHI, the code has to be modified slightly to ensure that decode->cc_src is written, otherwise the new assertions trigger. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> | 2 年前 | |
hw/loongarch/virt: Remove unused 'loongarch_virt_pm' region The system test shutdown uses the 'loongarch_virt_pm' region. We can use the write AcpiFadtData.sleep_clt register to realize the shutdown. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20231012072351.1409344-1-gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> | 2 年前 | |
fpu: Handle m68k extended precision denormals properly Motorola treats denormals with explicit integer bit set as having unbiased exponent 0, unlike Intel which treats it as having unbiased exponent 1 (more like all other IEEE formats that have no explicit integer bit). Add a flag on FloatFmt to differentiate the behaviour. Reported-by: Keith Packard <keithp@keithp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 2 年前 | |
tests/tcg: Add -fno-stack-protector A build of GCC 13.2 will have stack protector enabled by default if it was configured with --enable-default-ssp option. For such a compiler, it is necessary to explicitly disable stack protector when linking without standard libraries. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230731091042.139159-3-akihiko.odaki@daynix.com> [AJB: fix comment string typo] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231029145033.592566-3-alex.bennee@linaro.org> | 2 年前 | |
tests/tcg: Add -fno-stack-protector A build of GCC 13.2 will have stack protector enabled by default if it was configured with --enable-default-ssp option. For such a compiler, it is necessary to explicitly disable stack protector when linking without standard libraries. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230731091042.139159-3-akihiko.odaki@daynix.com> [AJB: fix comment string typo] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231029145033.592566-3-alex.bennee@linaro.org> | 2 年前 | |
tests/tcg: finesse the registers check for "hidden" regs The reason the ppc64 and s390x test where failing was because gdb hides them although they are still accessible via regnum. We can re-arrange the test a little bit and include these two arches in our test. We also need to be a bit more careful handling remote-registers as the format isn't easily parsed with pure white space separation. Once we fold types like "long long" and "long double" into a single word we can now assert all registers are either listed or elided. Cc: Ilya Leoshkevich <iii@linux.ibm.com> Cc: <qemu-s390x@nongnu.org> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: <qemu-ppc@nongnu.org> Cc: Luis Machado <luis.machado@arm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231121153606.542101-1-alex.bennee@linaro.org> | 2 年前 | |
Revert "tests/tcg/nios2: Re-enable linux-user tests" nios2 signal tests are broken again: retry.py -n 10 -c -- ./qemu-nios2 ./tests/tcg/nios2-linux-user/signals Results summary: 0: 8 times (80.00%), avg time 2.254 (0.00 varience/0.00 deviation) -11: 2 times (20.00%), avg time 0.253 (0.00 varience/0.00 deviation) Ran command 10 times, 8 passes This wasn't picked up by CI as we don't have a docker container that can build QEMU with the nios2 compiler. I don't have time to bisect the breakage and the target is orphaned anyway so take the easy route and revert it. This reverts commit 20e7524ff9f0cab4c9a0306014d6f3d7b467ae1e. Cc: Chris Wulff <crwulff@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231106185112.2755262-23-alex.bennee@linaro.org> | 2 年前 | |
target/openrisc: Rename the cpu from or32 to or1k This is in keeping with the toolchain and or1ksim. Signed-off-by: Richard Henderson <rth@twiddle.net> | 9 年前 | |
tests/tcg: move configuration to a sub-shell script Avoid the repeated inclusions of config-target.mak, which have risks of namespace pollution, and instead build minimal configuration files in a configuration script. The same configuration files can also be included in Makefile and Makefile.qemu [AJB 10/09/19] In the original PR this had inadvertently enabled tests for ppc64abi32. However as the rest of the multiarch tests work rather than disabling the otherwise correctly functioning build I've just skipped the failing linux-test test. For some reason I can't debug it with TCG so I'm leaving that to the PPC maintainers to look at. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-4-pbonzini@redhat.com> [AJB: s/docker/container/, rm last bits from configure, ppc6432abi hack] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Richard Henderson <rth@twiddle.net> | 6 年前 | |
tests/tcg: finesse the registers check for "hidden" regs The reason the ppc64 and s390x test where failing was because gdb hides them although they are still accessible via regnum. We can re-arrange the test a little bit and include these two arches in our test. We also need to be a bit more careful handling remote-registers as the format isn't easily parsed with pure white space separation. Once we fold types like "long long" and "long double" into a single word we can now assert all registers are either listed or elided. Cc: Ilya Leoshkevich <iii@linux.ibm.com> Cc: <qemu-s390x@nongnu.org> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: <qemu-ppc@nongnu.org> Cc: Luis Machado <luis.machado@arm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231121153606.542101-1-alex.bennee@linaro.org> | 2 年前 | |
tests/tcg: unify ppc64 and ppc64le Makefiles Make tests/tcg/ppc64le include tests/tcg/ppc64 instead of duplicating the rules. Because the ppc64le vpath includes tests/tcg/ppc64 but not vice versa, the tests have to be moved from tests/tcg/ppc64le/ to tests/tcg/ppc64. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-23-alex.bennee@linaro.org> | 3 年前 | |
riscv: Add support for the Zfa extension This patch introduces the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of float register bigger than XLEN * Quiet comparison instructions (fleq/fltq) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) Since QEMU does not support the RISC-V quad-precision floating-point ISA extension (Q), this patch does not include the instructions that depend on this extension. All other instructions are included in this patch. The Zfa specification can be found here: https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex The Zfa specifciation is frozen and is in public review since May 3, 2023: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg The patch also includes a TCG test for the fcvtmod.w.d instruction. The test cases test for correct results and flag behaviour. Note, that the Zfa specification requires fcvtmod's flag behaviour to be identical to a fcvt with the same operands (which is also tested). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230710071243.282464-1-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 3 年前 | |
tests/tcg/s390x: Test LOAD ADDRESS EXTENDED Add a small test to prevent regressions. Userspace runs in primary mode, so LAE should always set the access register to 0. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240111092328.929421-3-iii@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> | 2 年前 | |
tests/tcg: re-enable threadcount for sh4 This test was marked as broken due to bug #856 which was fixed by ab419fd8a0 (target/sh4: Fix TB_FLAG_UNALIGN). Local testing shows this is solid now so lets re-enable the test. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20221027183637.2772968-23-alex.bennee@linaro.org> | 3 年前 | |
tests/tcg/sparc64: Re-enable linux-test It passes now that we support signals properly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210426025334.1168495-26-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> | 5 年前 | |
tests/tcg: Reset result register after each test some insns use the result register implicitly as an input. Thus, we could end up with data from the previous insn spilling over. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-ID: <20230913105326.40832-4-kbastian@mail.uni-paderborn.de> | 2 年前 | |
other architectures: spelling fixes Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 年前 | |
tcg: Correct invalid mentions of 'softmmu' by 'system-mode' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004090629.37473-6-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> | 2 年前 | |
tcg: Correct invalid mentions of 'softmmu' by 'system-mode' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004090629.37473-6-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> | 2 年前 | |
tests/tcg: Add -fno-stack-protector A build of GCC 13.2 will have stack protector enabled by default if it was configured with --enable-default-ssp option. For such a compiler, it is necessary to explicitly disable stack protector when linking without standard libraries. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230731091042.139159-3-akihiko.odaki@daynix.com> [AJB: fix comment string typo] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231029145033.592566-3-alex.bennee@linaro.org> | 2 年前 | |
Drop the deprecated lm32 target Target lm32 was deprecated in commit d8498005122, v5.2.0. See there for rationale. Some of its code lives on in device models derived from milkymist ones: hw/char/digic-uart.c and hw/display/bcm2835_fb.c. Cc: Michael Walle <michael@walle.cc> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210503084034.3804963-2-armbru@redhat.com> Acked-by: Michael Walle <michael@walle.cc> [Trivial conflicts resolved, reST markup fixed] | 5 年前 |