fix: 补齐 BatchNormGradV3 tiling 注册与 UT 数据布局-ops-nn-AtomGit

已合并

fix: 补齐 BatchNormGradV3 tiling 注册与 UT 数据布局 #12100

qianzehong创建于 7 天前从qianzehong/ops-nn： fix/bngv3-tiling-registration-ut-layout 合入到 cann/ops-nn： master

fix: 补齐 BatchNormGradV3 tiling 注册与 UT 数据布局 #12100

已合并

qianzehong创建于 7 天前

从qianzehong/ops-nn fix/bngv3-tiling-registration-ut-layout合入到cann/ops-nn master

共 2 个文件变更+43-7

Mnorm/batch_norm_grad_v3/op_host/batch_norm_grad_v3_tiling.h+2-0

	@@ -164,6 +164,8 @@ TILING_DATA_FIELD_DEF(int64_t, cacheBuffCnt); // cacheBuffer个数
164	END_TILING_DATA_DEF;	164	END_TILING_DATA_DEF;
165		165
166	REGISTER_TILING_DATA_CLASS(BatchNormGradV3_50000000, BatchNormGradV3RASplitRTilingData);	166	REGISTER_TILING_DATA_CLASS(BatchNormGradV3_50000000, BatchNormGradV3RASplitRTilingData);
		167	+REGISTER_TILING_DATA_CLASS(BatchNormGradV3_51000000, BatchNormGradV3RASplitRTilingData);
		168	+REGISTER_TILING_DATA_CLASS(BatchNormGradV3_52000000, BatchNormGradV3RASplitRTilingData);
167		169
168	// inference - channel last format tiling data (NHWC format)	170	// inference - channel last format tiling data (NHWC format)
169	BEGIN_TILING_DATA_DEF(BatchNormGradV3InferChannelLastTilingData)	171	BEGIN_TILING_DATA_DEF(BatchNormGradV3InferChannelLastTilingData)

Mnorm/batch_norm_grad_v3/tests/ut/op_kernel/batch_norm_grad_v3_tiling_def.h+41-7

	@@ -1,12 +1,11 @@
1	/**	1	/**
2	- * This program is free software, you can redistribute it and/or modify.
3	* Copyright (c) 2025 Huawei Technologies Co., Ltd.	2	* Copyright (c) 2025 Huawei Technologies Co., Ltd.
4	- * This file is a part of the CANN Open Software.	3	+ * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
5	- * Licensed under CANN Open Software License Agreement Version 2.0 (the "License").	4	+ * CANN Open Software License Agreement Version 2.0 (the "License").
6	* Please refer to the License for details. You may not use this file except in compliance with the License.	5	* Please refer to the License for details. You may not use this file except in compliance with the License.
7	- * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING	6	+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
8	- * BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. See LICENSE in the root of	7	+ * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
9	- * the software repository for the full text of the License.	8	+ * See LICENSE in the root of the software repository for the full text of the License.
10	*/	9	*/
11		10
12	/*!	11	/*!
	@@ -114,6 +113,32 @@ struct BatchNormGradV3RARecomputeTilingData {
114	float reciprocal = 0;	113	float reciprocal = 0;
115	};	114	};
116		115
		116	+struct BatchNormGradV3RASplitRTilingData {
		117	+ int64_t rDim = 0;
		118	+ int64_t aDim = 0;
		119	+ int64_t usedCoreNum = 0;
		120	+ int64_t rLoopFactor = 0;
		121	+ int64_t blockFactor = 0;
		122	+ int64_t tailBlockFactor = 0;
		123	+ int64_t binaryBlockCnt = 0;
		124	+ int64_t binaryFoldPoint = 0;
		125	+ int64_t binaryBlockTail = 0;
		126	+ int64_t lastCoreBlockCnt = 0;
		127	+ int64_t lastCoreFoldPoint = 0;
		128	+ int64_t lastCoreLoopTail = 0;
		129	+ int64_t aFactor = 0;
		130	+ int64_t aFactorAlign = 0;
		131	+ int64_t aFactorTail = 0;
		132	+ int64_t aLoopTimes = 0;
		133	+ int64_t dxLoopFactor = 0;
		134	+ int64_t dxLoopTail = 0;
		135	+ int64_t dxLoopTimes = 0;
		136	+ int64_t dxLastCoreFactor = 0;
		137	+ int64_t dxLastCoreTail = 0;
		138	+ int64_t dxLastCoreTimes = 0;
		139	+ int64_t cacheBuffCnt = 0;
		140	+};
		141	+
117	struct BatchNormGradV3RARSplitCoreR1TilingData {	142	struct BatchNormGradV3RARSplitCoreR1TilingData {
118	BatchNormGradV3BaseTilingData baseTilingData;	143	BatchNormGradV3BaseTilingData baseTilingData;
119	int64_t r1Dim = 0;	144	int64_t r1Dim = 0;
	@@ -126,6 +151,7 @@ struct BatchNormGradV3RARSplitCoreR1TilingData {
126	int64_t r0InnerStg0 = 0;	151	int64_t r0InnerStg0 = 0;
127	int64_t r0OuterStg0 = 0;	152	int64_t r0OuterStg0 = 0;
128	int64_t r0TailStg0 = 0;	153	int64_t r0TailStg0 = 0;
		154	+ int64_t r0TailAlignedStg0 = 0;
129	int64_t r1InnerInnerStg0 = 0;	155	int64_t r1InnerInnerStg0 = 0;
130	int64_t r1InnerOuterStg0 = 0;	156	int64_t r1InnerOuterStg0 = 0;
131	int64_t r1InnerTailStg0 = 0;	157	int64_t r1InnerTailStg0 = 0;
	@@ -141,6 +167,7 @@ struct BatchNormGradV3RARSplitCoreR1TilingData {
141	int64_t r0InnerStg2 = 0;	167	int64_t r0InnerStg2 = 0;
142	int64_t r0OuterStg2 = 0;	168	int64_t r0OuterStg2 = 0;
143	int64_t r0TailStg2 = 0;	169	int64_t r0TailStg2 = 0;
		170	+ int64_t r0TailAlignedStg2 = 0;
144	int64_t r1InnerInnerStg2 = 0;	171	int64_t r1InnerInnerStg2 = 0;
145	int64_t r1InnerOuterStg2 = 0;	172	int64_t r1InnerOuterStg2 = 0;
146	int64_t r1InnerTailStg2 = 0;	173	int64_t r1InnerTailStg2 = 0;
	@@ -150,6 +177,13 @@ struct BatchNormGradV3RARSplitCoreR1TilingData {
150	int64_t aInnerAlignedStg2 = 0;	177	int64_t aInnerAlignedStg2 = 0;
151	int64_t aOuterStg2 = 0;	178	int64_t aOuterStg2 = 0;
152	int64_t aTailStg2 = 0;	179	int64_t aTailStg2 = 0;
		180	+ int64_t binAddBasicBlockLoop = 0;
		181	+ int64_t binAddMainFoldCount = 0;
		182	+ int64_t binAddCacheBufferCount = 0;
		183	+ int64_t binAddResultCacheID = 0;
		184	+ int64_t lastCoreBinAddBasicBlockLoop = 0;
		185	+ int64_t lastCoreBinAddMainFoldCount = 0;
		186	+ int64_t lastCoreBinAddResultCacheID = 0;
153	};	187	};
154		188
155	struct BatchNormGradV3InferChannelLastTilingData {	189	struct BatchNormGradV3InferChannelLastTilingData {
	@@ -259,4 +293,4 @@ inline void InitTilingData(uint8_t* tiling, T* const_data)
259	tiling_struct tiling_data; \	293	tiling_struct tiling_data; \
260	InitTilingData<tiling_struct>(tiling_arg, &tiling_data)	294	InitTilingData<tiling_struct>(tiling_arg, &tiling_data)
261		295
262	-#endif	296	+#endif