simt子函数添加 __simt_callee_

已合并

simt子函数添加 __simt_callee__标记 #3130

李鑫创建于 3月24日从lixin433/ops-nn： 9.0.0 合入到 cann/ops-nn： 9.0.0

simt子函数添加 __simt_callee__标记 #3130

已合并

李鑫创建于 3月24日

从lixin433/ops-nn 9.0.0合入到cann/ops-nn 9.0.0

共 15 个文件变更+34-34

Mcommon/inc/op_kernel/hashtable_common.h+1-1

	@@ -19,7 +19,7 @@
19		19
20	namespace Hashtbl {	20	namespace Hashtbl {
21		21
22	-__aicore__ inline uint32_t MurmurHash3(__gm__ int64_t* key, int len, uint32_t seed)	22	+__simt_callee__ __aicore__ inline uint32_t MurmurHash3(__gm__ int64_t* key, int len, uint32_t seed)
23	{	23	{
24	const uint32_t c1 = 0xcc9e2d51;	24	const uint32_t c1 = 0xcc9e2d51;
25	const uint32_t c2 = 0x1b873593;	25	const uint32_t c2 = 0x1b873593;

Mconv/deformable_offsets/op_kernel/arch35/deformable_offsets.h+3-3

	@@ -52,13 +52,13 @@ __aicore__ inline void DeformableOffset<T, T1, T2>::Init(
52	tiling_ = tilingData;	52	tiling_ = tilingData;
53	}	53	}
54		54
55	-__aicore__ __attribute__((always_inline)) inline float GetFloorValue(float x)	55	+__simt_callee__ __aicore__ __attribute__((always_inline)) inline float GetFloorValue(float x)
56	{	56	{
57	return __floorf(x);	57	return __floorf(x);
58	}	58	}
59		59
60	template <typename T, typename T1, typename T2>	60	template <typename T, typename T1, typename T2>
61	-__aicore__ __attribute__((always_inline)) inline T GetInputPointValue(	61	+__simt_callee__ __aicore__ __attribute__((always_inline)) inline T GetInputPointValue(
62	__gm__ T* inputImgGmAddr, T1 inputHeight, T1 inputWidth, T1 channelIndex,	62	__gm__ T* inputImgGmAddr, T1 inputHeight, T1 inputWidth, T1 channelIndex,
63	T1 inputDataBatchOffset, T1 imgHeight, T1 imgWidth, T1 imgWidthStride, T1 imgChannel)	63	T1 inputDataBatchOffset, T1 imgHeight, T1 imgWidth, T1 imgWidthStride, T1 imgChannel)
64	{	64	{
	@@ -70,7 +70,7 @@ __aicore__ __attribute__((always_inline)) inline T GetInputPointValue(
70	}	70	}
71		71
72	template <typename T, typename T1, typename T2>	72	template <typename T, typename T1, typename T2>
73	-__aicore__ __attribute__((always_inline)) inline T DeformableOffsetBilinear(	73	+__simt_callee__ __aicore__ __attribute__((always_inline)) inline T DeformableOffsetBilinear(
74	__gm__ T* inputImgGmAddr, float pointHeight, float pointWidth, T1 channelIndex, T offsetPointWeight,	74	__gm__ T* inputImgGmAddr, float pointHeight, float pointWidth, T1 channelIndex, T offsetPointWeight,
75	T1 inputDataBatchOffset, T1 imgHeight, T1 imgWidth, T1 imgWidthStride, T1 imgChannel)	75	T1 inputDataBatchOffset, T1 imgHeight, T1 imgWidth, T1 imgWidthStride, T1 imgChannel)
76	{	76	{

Mindex/gather_nd/op_kernel/arch35/gather_nd_simt.h+1-1

	@@ -40,7 +40,7 @@ constexpr uint32_t THREAD_DIMS = 1024;
40	#endif	40	#endif
41		41
42	template <typename T1>	42	template <typename T1>
43	-__aicore__ inline void SetOutOfBoundValue(__ubuf__ T1 *dstTensor, const uint32_t idx)	43	+__simt_callee__ __aicore__ inline void SetOutOfBoundValue(__ubuf__ T1 *dstTensor, const uint32_t idx)
44	{	44	{
45	if constexpr (IsSameType<T1, int4>::value) {	45	if constexpr (IsSameType<T1, int4>::value) {
46	dstTensor[idx] = (int4){defaultZero[0], defaultZero[1], defaultZero[2], defaultZero[3]};	46	dstTensor[idx] = (int4){defaultZero[0], defaultZero[1], defaultZero[2], defaultZero[3]};

Mindex/index/op_kernel/arch35/index.h+6-6

	@@ -73,9 +73,9 @@ struct is_same<Tp, Tp> : public true_type {};
73	// index assignment function	73	// index assignment function
74	template <typename T, typename T2>	74	template <typename T, typename T2>
75	struct IndexAssign {	75	struct IndexAssign {
76	- __aicore__ inline IndexAssign()	76	+ __simt_callee__ __aicore__ inline IndexAssign()
77	{}	77	{}
78	- __aicore__ inline void operator()(__gm__ T* output, __gm__ T* input, T2 i, T2 idx)	78	+ __simt_callee__ __aicore__ inline void operator()(__gm__ T* output, __gm__ T* input, T2 i, T2 idx)
79	{	79	{
80	output[i] = input[idx];	80	output[i] = input[idx];
81	}	81	}
	@@ -84,9 +84,9 @@ struct IndexAssign {
84	// indexPut assignment function	84	// indexPut assignment function
85	template <typename T>	85	template <typename T>
86	struct IndexPutAssign {	86	struct IndexPutAssign {
87	- __aicore__ inline IndexPutAssign()	87	+ __simt_callee__ __aicore__ inline IndexPutAssign()
88	{}	88	{}
89	- __aicore__ inline void operator()(__gm__ T* output, __gm__ T* input, uint32_t i, uint32_t idx)	89	+ __simt_callee__ __aicore__ inline void operator()(__gm__ T* output, __gm__ T* input, uint32_t i, uint32_t idx)
90	{	90	{
91	output[idx] = input[i];	91	output[idx] = input[i];
92	}	92	}
	@@ -95,9 +95,9 @@ struct IndexPutAssign {
95	// indexPut add function for accumulate mode	95	// indexPut add function for accumulate mode
96	template <typename T>	96	template <typename T>
97	struct IndexPutAdd {	97	struct IndexPutAdd {
98	- __aicore__ inline IndexPutAdd()	98	+ __simt_callee__ __aicore__ inline IndexPutAdd()
99	{}	99	{}
100	- __aicore__ inline void operator()(__gm__ T* output, __gm__ T* input, uint32_t i, uint32_t idx)	100	+ __simt_callee__ __aicore__ inline void operator()(__gm__ T* output, __gm__ T* input, uint32_t i, uint32_t idx)
101	{	101	{
102	if constexpr (is_same<bool, T>::value) {	102	if constexpr (is_same<bool, T>::value) {
103	if(input[i]){	103	if(input[i]){

Mindex/index_put_with_sort_v2/op_kernel/arch35/index_put_with_sort_v2.h+1-1

	@@ -32,7 +32,7 @@ constexpr int32_t THREAD_NUM_FULL = 1024;
32	constexpr int32_t THREAD_NUM_HALF = 512;	32	constexpr int32_t THREAD_NUM_HALF = 512;
33		33
34	template<typename TX, typename TIDX, bool ACCUMULATE, bool ALL_INDEXED, bool INDEXED_BLOCK_MODE>	34	template<typename TX, typename TIDX, bool ACCUMULATE, bool ALL_INDEXED, bool INDEXED_BLOCK_MODE>
35	-__aicore__ __attribute__((always_inline)) inline void SimtIndexPutV2(__gm__ TX* output, __gm__ TIDX* sortIndices,	35	+__simt_callee__ __aicore__ __attribute__((always_inline)) inline void SimtIndexPutV2(__gm__ TX* output, __gm__ TIDX* sortIndices,
36	__gm__ int32_t* posIdx, __gm__ TX* values, __ubuf__ int64_t* tilingUb) {	36	__gm__ int32_t* posIdx, __gm__ TX* values, __ubuf__ int64_t* tilingUb) {
37	const auto& nonIndexedDimNum = tilingUb[0];	37	const auto& nonIndexedDimNum = tilingUb[0];
38	const auto& indexedDimSize = tilingUb[1];	38	const auto& indexedDimSize = tilingUb[1];

Mindex/scatter/op_kernel/arch35/scatter.h+4-4

	@@ -58,7 +58,7 @@ constexpr int8_t SHIFT_ARR_LEN = 3;
58	constexpr int8_t M_ARR_LEN = 3;	58	constexpr int8_t M_ARR_LEN = 3;
59		59
60	template<typename T3>	60	template<typename T3>
61	-__aicore__ inline void CalcIndex2(int32_t addr, uint32_t &i, uint32_t &j, __local_mem__ T3* factorArr, __local_mem__ T3* shiftArr, __local_mem__ T3* mArr) {	61	+__simt_callee__ __aicore__ inline void CalcIndex2(int32_t addr, uint32_t &i, uint32_t &j, __local_mem__ T3* factorArr, __local_mem__ T3* shiftArr, __local_mem__ T3* mArr) {
62	// fast division, addr / factor0	62	// fast division, addr / factor0
63	uint32_t t = Simt::MulHi(static_cast<uint32_t>(addr), static_cast<uint32_t>(mArr[INDEX_ZERO]));	63	uint32_t t = Simt::MulHi(static_cast<uint32_t>(addr), static_cast<uint32_t>(mArr[INDEX_ZERO]));
64	t = t + addr;	64	t = t + addr;
	@@ -71,7 +71,7 @@ __aicore__ inline void CalcIndex2(int32_t addr, uint32_t &i, uint32_t &j, __loca
71	}	71	}
72		72
73	template<typename T3>	73	template<typename T3>
74	-__aicore__ inline void CalcIndex3(int32_t addr, uint32_t &i, uint32_t &j, uint32_t &k, __local_mem__ T3* factorArr, __local_mem__ T3* shiftArr, __local_mem__ T3* mArr) {	74	+__simt_callee__ __aicore__ inline void CalcIndex3(int32_t addr, uint32_t &i, uint32_t &j, uint32_t &k, __local_mem__ T3* factorArr, __local_mem__ T3* shiftArr, __local_mem__ T3* mArr) {
75	// fast division, addr / factor0	75	// fast division, addr / factor0
76	uint32_t t = Simt::MulHi(static_cast<uint32_t>(addr), static_cast<uint32_t>(mArr[INDEX_ZERO]));	76	uint32_t t = Simt::MulHi(static_cast<uint32_t>(addr), static_cast<uint32_t>(mArr[INDEX_ZERO]));
77	t = t + addr;	77	t = t + addr;
	@@ -89,7 +89,7 @@ __aicore__ inline void CalcIndex3(int32_t addr, uint32_t &i, uint32_t &j, uint32
89	}	89	}
90		90
91	template<typename T3>	91	template<typename T3>
92	-__aicore__ inline void CalcUint64Index2(int64_t addr, uint64_t &i, uint64_t &j, __local_mem__ T3* factorArr, __local_mem__ T3* shiftArr, __local_mem__ T3* mArr) {	92	+__simt_callee__ __aicore__ inline void CalcUint64Index2(int64_t addr, uint64_t &i, uint64_t &j, __local_mem__ T3* factorArr, __local_mem__ T3* shiftArr, __local_mem__ T3* mArr) {
93	// uint64_t &i, uint64_t &j	93	// uint64_t &i, uint64_t &j
94	i = Simt::UintDiv(static_cast<uint64_t>(addr), static_cast<uint64_t>(mArr[INDEX_ZERO]), static_cast<uint64_t>(shiftArr[INDEX_ZERO]));	94	i = Simt::UintDiv(static_cast<uint64_t>(addr), static_cast<uint64_t>(mArr[INDEX_ZERO]), static_cast<uint64_t>(shiftArr[INDEX_ZERO]));
95	int64_t remain = addr - i * factorArr[INDEX_ZERO];	95	int64_t remain = addr - i * factorArr[INDEX_ZERO];
	@@ -97,7 +97,7 @@ __aicore__ inline void CalcUint64Index2(int64_t addr, uint64_t &i, uint64_t &j,
97	}	97	}
98		98
99	template<typename T3>	99	template<typename T3>
100	-__aicore__ inline void CalcUint64Index3(int64_t addr, uint64_t &i, uint64_t &j, uint64_t &k, __local_mem__ T3* factorArr, __local_mem__ T3* shiftArr, __local_mem__ T3* mArr) {	100	+__simt_callee__ __aicore__ inline void CalcUint64Index3(int64_t addr, uint64_t &i, uint64_t &j, uint64_t &k, __local_mem__ T3* factorArr, __local_mem__ T3* shiftArr, __local_mem__ T3* mArr) {
101	// uint64_t &i, uint64_t &j, uint64_t &k	101	// uint64_t &i, uint64_t &j, uint64_t &k
102	i = Simt::UintDiv(static_cast<uint64_t>(addr), static_cast<uint64_t>(mArr[INDEX_ZERO]), static_cast<uint64_t>(shiftArr[INDEX_ZERO]));	102	i = Simt::UintDiv(static_cast<uint64_t>(addr), static_cast<uint64_t>(mArr[INDEX_ZERO]), static_cast<uint64_t>(shiftArr[INDEX_ZERO]));
103	int64_t remain = addr - i * factorArr[INDEX_ZERO];	103	int64_t remain = addr - i * factorArr[INDEX_ZERO];

Mindex/scatter_elements/op_kernel/arch35/scatter_elements.h+2-2

	@@ -161,7 +161,7 @@ __simt_vf__ __aicore__ LAUNCH_BOUND(USED_THREAD) inline void SimtComputeDim8(
161	__gm__ CAST_T* xWorkspaceGm, __ubuf__ uint64_t* TilingUint64Ub, COMP_T allAxis, __ubuf__ COMP_T* params);	161	__gm__ CAST_T* xWorkspaceGm, __ubuf__ uint64_t* TilingUint64Ub, COMP_T allAxis, __ubuf__ COMP_T* params);
162		162
163	template <typename DATA_T, typename COMP_T, typename CAST_T, const uint32_t REDU>	163	template <typename DATA_T, typename COMP_T, typename CAST_T, const uint32_t REDU>
164	-__aicore__ inline void ReplaceOut(__gm__ DATA_T* updates, __gm__ DATA_T* y, __gm__ CAST_T* updatesWorkspaceGm,	164	+__simt_callee__ __aicore__ inline void ReplaceOut(__gm__ DATA_T* updates, __gm__ DATA_T* y, __gm__ CAST_T* updatesWorkspaceGm,
165	__gm__ CAST_T* xWorkspaceGm, COMP_T yOffset, COMP_T updatesOffset);	165	__gm__ CAST_T* xWorkspaceGm, COMP_T yOffset, COMP_T updatesOffset);
166		166
167	template <typename DATA_T, typename IDX_T, typename COMP_T, typename CAST_T, const uint32_t REDU>	167	template <typename DATA_T, typename IDX_T, typename COMP_T, typename CAST_T, const uint32_t REDU>
	@@ -480,7 +480,7 @@ __aicore__ inline void KernelScatterElements<DATA_T, IDX_T, COMP_T, CAST_T, REDU
480	}	480	}
481		481
482	template <typename DATA_T, typename COMP_T, typename CAST_T, const uint32_t REDU>	482	template <typename DATA_T, typename COMP_T, typename CAST_T, const uint32_t REDU>
483	-__aicore__ inline void ReplaceOut(__gm__ DATA_T* updates, __gm__ DATA_T* y, __gm__ CAST_T* updatesWorkspaceGm,	483	+__simt_callee__ __aicore__ inline void ReplaceOut(__gm__ DATA_T* updates, __gm__ DATA_T* y, __gm__ CAST_T* updatesWorkspaceGm,
484	__gm__ CAST_T* xWorkspaceGm, COMP_T yOffset, COMP_T updatesOffset)	484	__gm__ CAST_T* xWorkspaceGm, COMP_T yOffset, COMP_T updatesOffset)
485	{	485	{
486	if constexpr (REDU == REDU_ADD) {	486	if constexpr (REDU == REDU_ADD) {

Mindex/scatter_elements/op_kernel/arch35/scatter_elements_deterministic.h+2-2

	@@ -99,7 +99,7 @@ private:
99	};	99	};
100		100
101	template <typename COMP_T, const uint16_t RANK, const uint16_t DIM>	101	template <typename COMP_T, const uint16_t RANK, const uint16_t DIM>
102	-__aicore__ inline void CalcOffset(COMP_T origIndicesOffset, COMP_T sValue, COMP_T& yOffset, COMP_T& updatesOffset,	102	+__simt_callee__ __aicore__ inline void CalcOffset(COMP_T origIndicesOffset, COMP_T sValue, COMP_T& yOffset, COMP_T& updatesOffset,
103	__ubuf__ uint64_t* TilingUint64Ub, __ubuf__ COMP_T* params);	103	__ubuf__ uint64_t* TilingUint64Ub, __ubuf__ COMP_T* params);
104		104
105	template <typename DATA_T, typename IDX_T, typename COMP_T, const uint32_t REDU, const uint16_t RANK,	105	template <typename DATA_T, typename IDX_T, typename COMP_T, const uint32_t REDU, const uint16_t RANK,
	@@ -804,7 +804,7 @@ __aicore__ inline void KernelScatterElementsDeterm<DATA_T, IDX_T, COMP_T, REDU>:
804	}	804	}
805		805
806	template <typename COMP_T, const uint16_t RANK, const uint16_t DIM>	806	template <typename COMP_T, const uint16_t RANK, const uint16_t DIM>
807	-__aicore__ inline void CalcOffset(COMP_T origIndicesOffset, COMP_T sValue, COMP_T& yOffset, COMP_T& updatesOffset,	807	+__simt_callee__ __aicore__ inline void CalcOffset(COMP_T origIndicesOffset, COMP_T sValue, COMP_T& yOffset, COMP_T& updatesOffset,
808	__ubuf__ uint64_t* TilingUint64Ub, __ubuf__ COMP_T* params)	808	__ubuf__ uint64_t* TilingUint64Ub, __ubuf__ COMP_T* params)
809	{	809	{
810	uint64_t dataStride[TILING_ARRAY_LEN] = {};	810	uint64_t dataStride[TILING_ARRAY_LEN] = {};

Mindex/scatter_elements_v2/op_kernel/scatter_elements.h+2-2

	@@ -159,7 +159,7 @@ __simt_vf__ __aicore__ LAUNCH_BOUND(USED_THREAD) inline void SimtComputeDim8(
159	__gm__ CAST_T* xWorkspaceGm, __ubuf__ uint64_t* TilingUint64Ub, COMP_T allAxis, __ubuf__ COMP_T* params);	159	__gm__ CAST_T* xWorkspaceGm, __ubuf__ uint64_t* TilingUint64Ub, COMP_T allAxis, __ubuf__ COMP_T* params);
160		160
161	template <typename DATA_T, typename COMP_T, typename CAST_T, const uint32_t REDU>	161	template <typename DATA_T, typename COMP_T, typename CAST_T, const uint32_t REDU>
162	-__aicore__ inline void ReplaceOut(__gm__ DATA_T* updates, __gm__ DATA_T* y, __gm__ CAST_T* updatesWorkspaceGm,	162	+__simt_callee__ __aicore__ inline void ReplaceOut(__gm__ DATA_T* updates, __gm__ DATA_T* y, __gm__ CAST_T* updatesWorkspaceGm,
163	__gm__ CAST_T* xWorkspaceGm, COMP_T yOffset, COMP_T updatesOffset);	163	__gm__ CAST_T* xWorkspaceGm, COMP_T yOffset, COMP_T updatesOffset);
164		164
165	template <typename DATA_T, typename IDX_T, typename COMP_T, typename CAST_T, const uint32_t REDU, const uint32_t TEMPLATE_V2=0>	165	template <typename DATA_T, typename IDX_T, typename COMP_T, typename CAST_T, const uint32_t REDU, const uint32_t TEMPLATE_V2=0>
	@@ -480,7 +480,7 @@ __aicore__ inline void KernelScatterElements<DATA_T, IDX_T, COMP_T, CAST_T, REDU
480	}	480	}
481		481
482	template <typename DATA_T, typename COMP_T, typename CAST_T, const uint32_t REDU>	482	template <typename DATA_T, typename COMP_T, typename CAST_T, const uint32_t REDU>
483	-__aicore__ inline void ReplaceOut(__gm__ DATA_T* updates, __gm__ DATA_T* y, __gm__ CAST_T* updatesWorkspaceGm,	483	+__simt_callee__ __aicore__ inline void ReplaceOut(__gm__ DATA_T* updates, __gm__ DATA_T* y, __gm__ CAST_T* updatesWorkspaceGm,
484	__gm__ CAST_T* xWorkspaceGm, COMP_T yOffset, COMP_T updatesOffset)	484	__gm__ CAST_T* xWorkspaceGm, COMP_T yOffset, COMP_T updatesOffset)
485	{	485	{
486	if constexpr (REDU == REDU_ADD) {	486	if constexpr (REDU == REDU_ADD) {

Mindex/scatter_elements_v2/op_kernel/scatter_elements_deterministic.h+2-2

	@@ -97,7 +97,7 @@ private:
97	};	97	};
98		98
99	template <typename COMP_T, const uint16_t RANK, const uint16_t DIM>	99	template <typename COMP_T, const uint16_t RANK, const uint16_t DIM>
100	-__aicore__ inline void CalcOffset(COMP_T origIndicesOffset, COMP_T sValue, COMP_T& yOffset, COMP_T& updatesOffset,	100	+__simt_callee__ __aicore__ inline void CalcOffset(COMP_T origIndicesOffset, COMP_T sValue, COMP_T& yOffset, COMP_T& updatesOffset,
101	__ubuf__ uint64_t* TilingUint64Ub, __ubuf__ COMP_T* params);	101	__ubuf__ uint64_t* TilingUint64Ub, __ubuf__ COMP_T* params);
102		102
103	template <typename DATA_T, typename IDX_T, typename COMP_T, const uint32_t REDU, const uint16_t RANK,	103	template <typename DATA_T, typename IDX_T, typename COMP_T, const uint32_t REDU, const uint16_t RANK,
	@@ -804,7 +804,7 @@ __aicore__ inline void KernelScatterElementsDeterm<DATA_T, IDX_T, COMP_T, REDU,
804	}	804	}
805		805
806	template <typename COMP_T, const uint16_t RANK, const uint16_t DIM>	806	template <typename COMP_T, const uint16_t RANK, const uint16_t DIM>
807	-__aicore__ inline void CalcOffset(COMP_T origIndicesOffset, COMP_T sValue, COMP_T& yOffset, COMP_T& updatesOffset,	807	+__simt_callee__ __aicore__ inline void CalcOffset(COMP_T origIndicesOffset, COMP_T sValue, COMP_T& yOffset, COMP_T& updatesOffset,
808	__ubuf__ uint64_t* TilingUint64Ub, __ubuf__ COMP_T* params)	808	__ubuf__ uint64_t* TilingUint64Ub, __ubuf__ COMP_T* params)
809	{	809	{
810	uint64_t dataStride[TILING_ARRAY_LEN] = {};	810	uint64_t dataStride[TILING_ARRAY_LEN] = {};

Mloss/ctc_loss_v2/op_kernel/arch35/ctc_loss_v2_fp16.h+2-2

	@@ -47,7 +47,7 @@ __aicore__ inline void CTCLossV2FP16<T, DataType, ThreadType>::Init(GM_ADDR log_
47	}	47	}
48		48
49	template <typename DataType, typename ThreadType>	49	template <typename DataType, typename ThreadType>
50	-__aicore__ inline DataType ProcessTgBatchOffsetsFp16(__gm__ DataType *targetLengthsGm, int32_t targetsDim,	50	+__simt_callee__ __aicore__ inline DataType ProcessTgBatchOffsetsFp16(__gm__ DataType *targetLengthsGm, int32_t targetsDim,
51	int32_t tgBatchStride, int32_t idx)	51	int32_t tgBatchStride, int32_t idx)
52	{	52	{
53	if (targetsDim == 1) {	53	if (targetsDim == 1) {
	@@ -62,7 +62,7 @@ __aicore__ inline DataType ProcessTgBatchOffsetsFp16(__gm__ DataType *targetLeng
62	}	62	}
63		63
64	template <typename T, typename DataType, typename ThreadType>	64	template <typename T, typename DataType, typename ThreadType>
65	-__aicore__ __attribute__((always_inline)) inline void CalcLogAlphaFp16(int32_t batchSize, int32_t laInputStride,	65	+__simt_callee__ __aicore__ __attribute__((always_inline)) inline void CalcLogAlphaFp16(int32_t batchSize, int32_t laInputStride,
66	ThreadType laBatchStride, ThreadType lpBatchStride, int32_t maxInputLength, ThreadType lpInputStride, int32_t targetsDim,	66	ThreadType laBatchStride, ThreadType lpBatchStride, int32_t maxInputLength, ThreadType lpInputStride, int32_t targetsDim,
67	int32_t tgBatchStride, int32_t blank, int32_t tgTargetStride, __gm__ T logProbsGm, __gm__ DataType targetsGm,	67	int32_t tgBatchStride, int32_t blank, int32_t tgTargetStride, __gm__ T logProbsGm, __gm__ DataType targetsGm,
68	__gm__ DataType inputLengthsGm, __gm__ DataType targetLengthsGm, __gm__ T negLogLikelihoodGm, __gm__ T logAlphaGm, __gm__ float *tmpDataGm)	68	__gm__ DataType inputLengthsGm, __gm__ DataType targetLengthsGm, __gm__ T negLogLikelihoodGm, __gm__ T logAlphaGm, __gm__ float *tmpDataGm)

Mloss/ctc_loss_v2/op_kernel/arch35/ctc_loss_v2_fp32.h+3-3

	@@ -70,21 +70,21 @@ __aicore__ inline void CTCLossV2FP32<T, DataType, ThreadType>::Init(GM_ADDR log_
70	}	70	}
71		71
72	template <typename DataType>	72	template <typename DataType>
73	-__aicore__ inline DataType GetTargetPrime(__gm__ DataType *target, int64_t offset, int64_t stride, int32_t idx,	73	+__simt_callee__ __aicore__ inline DataType GetTargetPrime(__gm__ DataType *target, int64_t offset, int64_t stride, int32_t idx,
74	int64_t blank)	74	int64_t blank)
75	{	75	{
76	return ((idx & 1) == 0) ? blank : target[offset + stride * (idx >> 1)];	76	return ((idx & 1) == 0) ? blank : target[offset + stride * (idx >> 1)];
77	}	77	}
78		78
79	template <typename DataType>	79	template <typename DataType>
80	-__aicore__ inline DataType ProcessTgBatchOffsets(__ubuf__ DataType *tensor, int64_t targetsDim, int64_t tgBatchStride,	80	+__simt_callee__ __aicore__ inline DataType ProcessTgBatchOffsets(__ubuf__ DataType *tensor, int64_t targetsDim, int64_t tgBatchStride,
81	int32_t idx)	81	int32_t idx)
82	{	82	{
83	return (targetsDim == 1) ? tensor[idx] : (tgBatchStride * idx);	83	return (targetsDim == 1) ? tensor[idx] : (tgBatchStride * idx);
84	}	84	}
85		85
86	template <typename T, typename DataType, typename ThreadType>	86	template <typename T, typename DataType, typename ThreadType>
87	-__aicore__ __attribute__((always_inline)) inline void CalcLogAlpha(int32_t batchSize, int32_t laInputStride, ThreadType laBatchStride,	87	+__simt_callee__ __aicore__ __attribute__((always_inline)) inline void CalcLogAlpha(int32_t batchSize, int32_t laInputStride, ThreadType laBatchStride,
88	ThreadType lpBatchStride, int32_t maxInputLength, ThreadType lpInputStride, int32_t targetsDim, int32_t tgBatchStride, int32_t blank,	88	ThreadType lpBatchStride, int32_t maxInputLength, ThreadType lpInputStride, int32_t targetsDim, int32_t tgBatchStride, int32_t blank,
89	int32_t tgTargetStride, __gm__ T logProbsGm, __gm__ DataType targetsGm, __gm__ DataType *inputLengthsGm,	89	int32_t tgTargetStride, __gm__ T logProbsGm, __gm__ DataType targetsGm, __gm__ DataType *inputLengthsGm,
90	__gm__ DataType targetLengthsGm, __gm__ T negLogLikelihoodGm, __gm__ T logAlphaGm, __ubuf__ DataType tensor)	90	__gm__ DataType targetLengthsGm, __gm__ T negLogLikelihoodGm, __gm__ T logAlphaGm, __ubuf__ DataType tensor)

Mloss/ctc_loss_v2_grad/op_kernel/arch35/ctc_loss_v2_grad.h+2-2

	@@ -135,7 +135,7 @@ __aicore__ inline void CTCLossV2Grad<T, DataType, ThreadType>::Init(
135	}	135	}
136		136
137	template <typename T, typename DataType, typename ThreadType>	137	template <typename T, typename DataType, typename ThreadType>
138	-__aicore__ __attribute__((always_inline)) inline ThreadType ProcessTgBatchOffsets(	138	+__simt_callee__ __aicore__ __attribute__((always_inline)) inline ThreadType ProcessTgBatchOffsets(
139	ThreadType idx, __gm__ DataType* targetLengthsGm, ThreadType targetsDimNum, ThreadType sDimRange)	139	ThreadType idx, __gm__ DataType* targetLengthsGm, ThreadType targetsDimNum, ThreadType sDimRange)
140	{	140	{
141	if (targetsDimNum == 1) {	141	if (targetsDimNum == 1) {
	@@ -150,7 +150,7 @@ __aicore__ __attribute__((always_inline)) inline ThreadType ProcessTgBatchOffset
150	}	150	}
151		151
152	template <typename T, typename DataType, typename ThreadType>	152	template <typename T, typename DataType, typename ThreadType>
153	-__aicore__ __attribute__((always_inline)) inline ThreadType GetTargetPrime(	153	+__simt_callee__ __aicore__ __attribute__((always_inline)) inline ThreadType GetTargetPrime(
154	__gm__ DataType* targetsGm, ThreadType offset, ThreadType stride, ThreadType idx, ThreadType blank)	154	__gm__ DataType* targetsGm, ThreadType offset, ThreadType stride, ThreadType idx, ThreadType blank)
155	{	155	{
156	if ((idx & 1) == 0) {	156	if ((idx & 1) == 0) {

Mloss/nll_loss/op_kernel/arch35/nll_loss_simt.h+2-2

	@@ -43,12 +43,12 @@ constexpr int64_t NUMBER_TWO = 2;
43	constexpr int64_t NUMBER_FOUR = 4;	43	constexpr int64_t NUMBER_FOUR = 4;
44		44
45	template <typename U>	45	template <typename U>
46	-__aicore__ inline void TargetCheck(const U idx, const uint32_t xDimC_)	46	+__simt_callee__ __aicore__ inline void TargetCheck(const U idx, const uint32_t xDimC_)
47	{	47	{
48	ASSERT((0 <= idx && idx < xDimC_) && "Target is invalid value");	48	ASSERT((0 <= idx && idx < xDimC_) && "Target is invalid value");
49	}	49	}
50		50
51	-__aicore__ inline void SimtComputeBinaryReduction(__ubuf__ float* tmpOut_, __ubuf__ float* tmpWeight_)	51	+__simt_callee__ __aicore__ inline void SimtComputeBinaryReduction(__ubuf__ float* tmpOut_, __ubuf__ float* tmpWeight_)
52	{	52	{
53	uint32_t countBR = Simt::GetThreadNum();	53	uint32_t countBR = Simt::GetThreadNum();
54	while (countBR > 1) {	54	while (countBR > 1) {

Mloss/nll_loss_grad/op_kernel/arch35/nll_loss_grad.h+1-1

	@@ -110,7 +110,7 @@ __aicore__ inline void KernelNLLLossGrad<T, F>::Init(GM_ADDR x, GM_ADDR y_grad,
110	this->blockTailCore_ = tilingData.blockTailCore;	110	this->blockTailCore_ = tilingData.blockTailCore;
111	}	111	}
112		112
113	-__aicore__ inline void TargetCheck(const int64_t idx, const int64_t classNum)	113	+__simt_callee__ __aicore__ inline void TargetCheck(const int64_t idx, const int64_t classNum)
114	{	114	{
115	ASSERT((0 <= idx && idx < classNum) &&	115	ASSERT((0 <= idx && idx < classNum) &&
116	("Currert target is %ld, which should be in range (0, classNum:%ld)", idx, classNum));	116	("Currert target is %ld, which should be in range (0, classNum:%ld)", idx, classNum));