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1805
已合并
swat load balance #4679
justsozl创建于 5月9日
swat load balance #4679
已合并
justsozl创建于 5月9日
从justsozl/ops-nnswat_load_balance合入到cann/ops-nnmaster
共 15 个文件变更+336-1059
Mmatmul/batch_mat_mul_v3/op_host/op_tiling/arch35/batch_matmul_v3_asw_al1_full_load_basic_tiling.cpp+1-1
@@ -72,7 +72,7 @@ ge::graphStatus BatchMatMulV3AswAL1FullLoadBasicTiling::DoOpTiling()
72 MatMulV3TilingHelper::ResetBase(compileInfo_, args_, runInfo_);72 MatMulV3TilingHelper::ResetBase(compileInfo_, args_, runInfo_);
73 MatMulV3TilingHelper::CalL1Tiling(compileInfo_, args_, runInfo_);73 MatMulV3TilingHelper::CalL1Tiling(compileInfo_, args_, runInfo_);
74 // 复用基础API A全载74 // 复用基础API A全载
75- MatMulV3BasicAswtTiling::DoAL1FullLoad(args_.batchInfo->batchB, args_.batchInfo->batchBias);75+ MatMulV3BasicAswtTiling::DoAL1FullLoad();
76 76 
77 // l1开2db后依然只使用了一半的空间，则开启4 db。该字段仅在基础api场景生效77 // l1开2db后依然只使用了一半的空间，则开启4 db。该字段仅在基础api场景生效
78 uint64_t alignMValue = ops::CeilAlign(args_.mValue, BASIC_BLOCK_SIZE_16);78 uint64_t alignMValue = ops::CeilAlign(args_.mValue, BASIC_BLOCK_SIZE_16);
Mmatmul/batch_mat_mul_v3/op_host/op_tiling/arch35/batch_matmul_v3_asw_basic_tiling.cpp+3-40
@@ -55,8 +55,7 @@ ge::graphStatus BatchMatMulV3AswBasicTiling::DoOpTiling()
55 MatMulV3TilingHelper::ResetBase(compileInfo_, args_, runInfo_);55 MatMulV3TilingHelper::ResetBase(compileInfo_, args_, runInfo_);
56 56 
57 MatMulV3TilingHelper::GetRebalanceBlock(compileInfo_, args_, runInfo_, context_);57 MatMulV3TilingHelper::GetRebalanceBlock(compileInfo_, args_, runInfo_, context_);
58- // 待matmul负载均衡上库后使用MatMulV3TilingHelper58+ MatMulV3TilingHelper::CalL1Tiling(compileInfo_, args_, runInfo_);
59- CalL1Tiling(compileInfo_, args_, runInfo_);
60 59 
61 // l1开2db后依然只使用了一半的空间，则开启4 db。该字段仅在基础api场景生效60 // l1开2db后依然只使用了一半的空间，则开启4 db。该字段仅在基础api场景生效
62 uint64_t abL1TensorSize = runInfo_.baseK * runInfo_.stepKa * (runInfo_.baseM + runInfo_.baseN) * args_.aDtypeSize;61 uint64_t abL1TensorSize = runInfo_.baseK * runInfo_.stepKa * (runInfo_.baseM + runInfo_.baseN) * args_.aDtypeSize;
@@ -118,45 +117,9 @@ ge::graphStatus BatchMatMulV3AswBasicTiling::GetTilingData(TilingResult& tiling)
118 return GetTilingDataImpl<BatchMatMulV3BasicTilingData>(tiling);117 return GetTilingDataImpl<BatchMatMulV3BasicTilingData>(tiling);
119}118}
120 119 
121-uint64_t BatchMatMulV3AswBasicTiling::GetNumBlocks() const { return compileInfo_.aicNum; }120+uint64_t BatchMatMulV3AswBasicTiling::GetNumBlocks() const
122- 
123-// 待matmul负载均衡上库后合并
124-void BatchMatMulV3AswBasicTiling::CalL1Tiling(
125- const MatmulV3CompileInfo& compileInfo, const MatMulV3Args& args, MatMulV3RunInfo& runInfo) const
126{121{
127- bool isKInner = !args.isATrans || args.isBTrans;122+ return compileInfo_.aicNum;
128- uint64_t totalL1Size = compileInfo.l1Size - (args.hasBias ? runInfo.baseN * DB_SIZE * DATA_SIZE_FP32 : 0UL);
129- // Shape约束 && issue queue约束
130- uint64_t maxStepK = std::min(Ops::NN::MathUtil::CeilDivision(args.kValue, runInfo.baseK), NUM_EIGHT);
131- uint64_t kAlignUnit = isKInner ? BASIC_BLOCK_K_512_BYTE / args.aDtypeSize : BASIC_BLOCK_SIZE_16;
132- uint64_t resKL1 = 0;
133- uint64_t singleMovSize = 0;
134- for (uint64_t stepK = 1; stepK <= maxStepK; stepK++) {
135- uint64_t curKL1 = runInfo.baseK * stepK;
136- uint64_t aL1Size = runInfo.baseM * curKL1 * args.aDtypeSize;
137- uint64_t bL1Size = runInfo.baseN * curKL1 * args.bDtypeSize;
138- // 表达式中的2代表让aL1/bL1仅使用一半的L1 Size，避免bank冲突
139- if ((aL1Size + bL1Size) * DB_SIZE > totalL1Size ||
140- std::max(aL1Size, bL1Size) * DB_SIZE * 2 > compileInfo.l1Size) {
141- break;
142- }
143- bool condNoRes = resKL1 == 0;
144- bool condKAlign256B = curKL1 % (BASIC_BLOCK_K_256_BYTE / args.aDtypeSize) == 0;
145- bool condKAlign =
146- resKL1 % kAlignUnit != 0 && (condKAlign256B || (!condKAlign256B && singleMovSize < L1_SINGLE_SIZE_LIMIT));
147- bool condMovSize = resKL1 % kAlignUnit == 0 && curKL1 % kAlignUnit == 0 && singleMovSize < L1_SINGLE_SIZE_LIMIT;
148- if (condNoRes || condKAlign || condMovSize) {
149- resKL1 = curKL1;
150- singleMovSize = std::max(aL1Size, bL1Size);
151- }
152- }
153- runInfo.stepKa = resKL1 / runInfo.baseK;
154- runInfo.stepKb = resKL1 / runInfo.baseK;
155- runInfo.depthA1 = runInfo.stepKa * DB_SIZE;
156- runInfo.depthB1 = runInfo.stepKb * DB_SIZE;
157- runInfo.singleCoreM = runInfo.baseM;
158- runInfo.singleCoreN = runInfo.baseN;
159- return;
160}123}
161} // namespace batch_matmul_v3_advanced124} // namespace batch_matmul_v3_advanced
162} // namespace optiling125} // namespace optiling
Mmatmul/batch_mat_mul_v3/op_host/op_tiling/arch35/batch_matmul_v3_asw_bl1_full_load_basic_tiling.cpp+1-1
@@ -71,7 +71,7 @@ ge::graphStatus BatchMatMulV3AswBL1FullLoadBasicTiling::DoOpTiling()
71 MatMulV3TilingHelper::ResetBase(compileInfo_, args_, runInfo_);71 MatMulV3TilingHelper::ResetBase(compileInfo_, args_, runInfo_);
72 MatMulV3TilingHelper::CalL1Tiling(compileInfo_, args_, runInfo_);72 MatMulV3TilingHelper::CalL1Tiling(compileInfo_, args_, runInfo_);
73 // 复用基础API B全载73 // 复用基础API B全载
74- MatMulV3BasicAswtTiling::DoBL1FullLoad(args_.batchInfo->batchA, args_.batchInfo->batchBias);74+ MatMulV3BasicAswtTiling::DoBL1FullLoad();
75 75 
76 // l1开2db后依然只使用了一半的空间，则开启4 db。该字段仅在基础api场景生效76 // l1开2db后依然只使用了一半的空间，则开启4 db。该字段仅在基础api场景生效
77 uint64_t alignKbValue = ops::CeilAlign(args_.kValue, BASIC_BLOCK_SIZE_16);77 uint64_t alignKbValue = ops::CeilAlign(args_.kValue, BASIC_BLOCK_SIZE_16);
Mmatmul/batch_mat_mul_v3/tests/ut/op_host/test_batch_mat_mul_v3_tiling.cpp+2-2
@@ -422,7 +422,7 @@ static TilingTestParam ascend950_cases_params[] = {
422 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },422 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
423 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",423 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
424 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, {1, 29, 11}, {230, 29, 2687}, {230, 11, 2687}, false, 0, 0, 32, 65553UL,424 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, {1, 29, 11}, {230, 29, 2687}, {230, 11, 2687}, false, 0, 0, 32, 65553UL,
425- "32 11 2687 29 16 256 32 16 256 32 29 1 1 1 1 0 0 16909313 0 16 1 0 230 0 "425+ "32 11 2687 29 16 128 32 256 128 32 29 1 1 1 1 0 0 16909313 0 256 1 0 230 0 "
426 },426 },
427 // singleCoreM 256->64427 // singleCoreM 256->64
428 // 拆分tiling后修复bmm b全载tilingKey和adjustTiling不匹配问题, apiLevel_未赋值导致ubDb未正确计算428 // 拆分tiling后修复bmm b全载tilingKey和adjustTiling不匹配问题, apiLevel_未赋值导致ubDb未正确计算
@@ -433,7 +433,7 @@ static TilingTestParam ascend950_cases_params[] = {
433 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },433 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
434 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",434 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
435 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, {47, 3680, 64}, {1, 3680, 16}, {47, 64, 16}, false, 0, 0, 32, 131089UL,435 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, {47, 3680, 64}, {1, 3680, 16}, {47, 64, 16}, false, 0, 0, 32, 131089UL,
436- "32 64 16 3680 64 16 128 256 16 32 3680 1 1 1 1 0 0 33686017 0 256 1 0 47 0 "436+ "32 64 16 3680 64 16 96 128 256 32 3680 1 1 1 1 0 0 33686529 0 128 1 0 47 0 "
437 },437 },
438 {438 {
439 "BatchMatMulV3_950_test_iterbatch_basicapi_fp32_01", "BatchMatMulV3", R"({"_pattern": "MatMul", "attrs":{"adj_x1":false,"adj_x2":false, "offset_x":0, "enable_hf32":true},439 "BatchMatMulV3_950_test_iterbatch_basicapi_fp32_01", "BatchMatMulV3", R"({"_pattern": "MatMul", "attrs":{"adj_x1":false,"adj_x2":false, "offset_x":0, "enable_hf32":true},
Mmatmul/fused_mat_mul/tests/ut/op_host/test_fused_matmul_tiling.cpp+16-16
@@ -203,7 +203,7 @@ static TilingTestParam ascend950_cases_params[] = {
203 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },203 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
204 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",204 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
205 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{4096, 8192}, {1280, 8192}, {4096, 1280}, {4096, 8192}, {1280, 8192}, {4096, 1280}, false, 0, 0, 32, 33554465UL,205 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{4096, 8192}, {1280, 8192}, {4096, 1280}, {4096, 8192}, {1280, 8192}, {4096, 1280}, false, 0, 0, 32, 33554465UL,
206- "32 4096 1280 8192 256 256 192 256 256 64 8192 2 1 1 1 0 0 16843264 0 256 1 0 "206+ "32 4096 1280 8192 256 224 256 256 224 64 8192 1 1 1 1 0 0 33620480 0 256 1 0 "
207 },207 },
208 {208 {
209 "FusedMatMul_950_basic_01", "FusedMatMul", "mul", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":true, "offset_x":0, "enable_hf32":0},209 "FusedMatMul_950_basic_01", "FusedMatMul", "mul", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":true, "offset_x":0, "enable_hf32":0},
@@ -212,7 +212,7 @@ static TilingTestParam ascend950_cases_params[] = {
212 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },212 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
213 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",213 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
214 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{4096, 8192}, {128, 8192}, {4096, 128}, {4096, 8192}, {128, 8192}, {4096, 128}, false, 0, 0, 32, 33554465UL,214 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{4096, 8192}, {128, 8192}, {4096, 128}, {4096, 8192}, {128, 8192}, {4096, 128}, false, 0, 0, 32, 33554465UL,
215- "32 4096 128 8192 128 128 384 128 128 128 8192 1 1 1 1 0 0 16908800 0 128 1 0 "215+ "32 4096 128 8192 128 128 384 128 128 128 8192 1 1 1 1 0 0 33686016 0 128 1 0 "
216 },216 },
217 {217 {
218 "FusedMatMul_950_basic_02", "FusedMatMul", "add", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":true, "offset_x":0, "enable_hf32":0},218 "FusedMatMul_950_basic_02", "FusedMatMul", "add", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":true, "offset_x":0, "enable_hf32":0},
@@ -221,7 +221,7 @@ static TilingTestParam ascend950_cases_params[] = {
221 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },221 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
222 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",222 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
223 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{4096, 8192}, {1280, 8192}, {4096, 1280}, {4096, 8192}, {1280, 8192}, {4096, 1280}, false, 0, 0, 32, 16777249UL,223 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{4096, 8192}, {1280, 8192}, {4096, 1280}, {4096, 8192}, {1280, 8192}, {4096, 1280}, false, 0, 0, 32, 16777249UL,
224- "32 4096 1280 8192 256 256 192 256 256 64 8192 2 1 1 1 0 0 16843264 0 256 1 0 "224+ "32 4096 1280 8192 256 224 256 256 224 64 8192 1 1 1 1 0 0 33620480 0 256 1 0 "
225 },225 },
226 {226 {
227 "FusedMatMul_950_basic_03", "FusedMatMul", "add", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":true, "offset_x":0, "enable_hf32":0},227 "FusedMatMul_950_basic_03", "FusedMatMul", "add", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":true, "offset_x":0, "enable_hf32":0},
@@ -230,7 +230,7 @@ static TilingTestParam ascend950_cases_params[] = {
230 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },230 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
231 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",231 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
232 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{4096, 8192}, {128, 8192}, {4096, 128}, {4096, 8192}, {128, 8192}, {4096, 128}, false, 0, 0, 32, 16777249UL,232 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{4096, 8192}, {128, 8192}, {4096, 128}, {4096, 8192}, {128, 8192}, {4096, 128}, false, 0, 0, 32, 16777249UL,
233- "32 4096 128 8192 128 128 384 128 128 128 8192 1 1 1 1 0 0 16908800 0 128 1 0 "233+ "32 4096 128 8192 128 128 384 128 128 128 8192 1 1 1 1 0 0 33686016 0 128 1 0 "
234 },234 },
235 // FudesMatmul + "" -> streamK235 // FudesMatmul + "" -> streamK
236 {236 {
@@ -276,7 +276,7 @@ static TilingTestParam ascend950_cases_params[] = {
276 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 28, "vector_core_cnt": 56, "socVersion": "Ascend950" },276 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 28, "vector_core_cnt": 56, "socVersion": "Ascend950" },
277 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",277 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
278 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{128, 18856}, {4096, 18856}, {128, 4096}, {128, 18856}, {4096, 18856}, {128, 4096}, false, 0, 0, 26, 33UL,278 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{128, 18856}, {4096, 18856}, {128, 4096}, {128, 18856}, {4096, 18856}, {128, 4096}, false, 0, 0, 26, 33UL,
279- "26 128 4096 18856 128 160 192 128 160 48 18856 1 1 1 1 0 0 16908800 0 128 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT279+ "26 128 4096 18856 128 160 128 128 160 32 18856 1 1 1 1 0 0 33686016 0 128 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT
280 },280 },
281 {281 {
282 "FusedMatMul_950_mmoe_fused_op_type_relu_basic_asw", "FusedMatMul", "relu", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":true, "offset_x":0, "enable_hf32": 1},282 "FusedMatMul_950_mmoe_fused_op_type_relu_basic_asw", "FusedMatMul", "relu", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":true, "offset_x":0, "enable_hf32": 1},
@@ -285,7 +285,7 @@ static TilingTestParam ascend950_cases_params[] = {
285 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 28, "vector_core_cnt": 56, "socVersion": "Ascend950" },285 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 28, "vector_core_cnt": 56, "socVersion": "Ascend950" },
286 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",286 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
287 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{128, 4096}, {4096, 4096}, {128, 4096}, {128, 4096}, {4096, 4096}, {128, 4096}, false, 0, 0, 26, 83886113UL,287 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{128, 4096}, {4096, 4096}, {128, 4096}, {128, 4096}, {4096, 4096}, {128, 4096}, false, 0, 0, 26, 83886113UL,
288- "26 128 4096 4096 128 160 192 128 160 48 4096 1 1 1 1 0 0 16908800 0 128 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT288+ "26 128 4096 4096 128 160 128 128 160 32 4096 1 1 1 1 0 0 33686016 0 128 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT
289 },289 },
290 // tilingKey 33 289 block 26 28 data？290 // tilingKey 33 289 block 26 28 data？
291 {291 {
@@ -304,7 +304,7 @@ static TilingTestParam ascend950_cases_params[] = {
304 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 28, "vector_core_cnt": 50, "socVersion": "Ascend950" },304 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 28, "vector_core_cnt": 50, "socVersion": "Ascend950" },
305 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",305 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
306 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{128, 4096}, {2048, 4096}, {128, 2048}, {128, 4096}, {2048, 4096}, {128, 2048}, false, 0, 0, 26, 33UL,306 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{128, 4096}, {2048, 4096}, {128, 2048}, {128, 4096}, {2048, 4096}, {128, 2048}, false, 0, 0, 26, 33UL,
307- "26 128 2048 4096 128 80 512 128 80 128 4096 1 1 1 1 0 0 16908800 0 128 1 0 ", ge::DT_BF16, ge::DT_BF16, ge::DT_BF16307+ "26 128 2048 4096 128 80 256 128 80 128 4096 1 1 1 1 0 0 33686016 0 128 1 0 ", ge::DT_BF16, ge::DT_BF16, ge::DT_BF16
308 },308 },
309 // 5243169 5242913 16 28309 // 5243169 5242913 16 28
310 {310 {
@@ -314,7 +314,7 @@ static TilingTestParam ascend950_cases_params[] = {
314 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 28, "vector_core_cnt": 56, "socVersion": "Ascend950" },314 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 28, "vector_core_cnt": 56, "socVersion": "Ascend950" },
315 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",315 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
316 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{128, 18856}, {64, 18856}, {128, 64}, {128, 18856}, {64, 18856}, {128, 64}, false, 0, 0, 28, 83890209UL,316 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, false, true,{128, 18856}, {64, 18856}, {128, 64}, {128, 18856}, {64, 18856}, {128, 64}, false, 0, 0, 28, 83890209UL,
317- "28 128 64 18856 128 64 512 128 64 128 674 1 1 1 1 0 0 16843264 0 128 1 0 1 0 ", ge::DT_BF16, ge::DT_BF16, ge::DT_FLOAT317+ "28 128 64 18856 128 64 256 128 64 128 674 1 1 1 1 0 0 16843264 0 128 1 0 1 0 ", ge::DT_BF16, ge::DT_BF16, ge::DT_FLOAT
318 },318 },
319 {319 {
320 "FusedMatMul_950_bmm_empty_onthefly", "FusedMatMul", "", R"({"_pattern": "BatchMatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "enable_hf32": 1},320 "FusedMatMul_950_bmm_empty_onthefly", "FusedMatMul", "", R"({"_pattern": "BatchMatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "enable_hf32": 1},
@@ -422,7 +422,7 @@ static TilingTestParam ascend950_cases_params[] = {
422 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },422 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
423 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",423 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
424 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, false,{1, 29, 11}, {230, 29, 2687}, {230, 11, 2687}, {1, 29, 11}, {230, 29, 2687}, {230, 11, 2687}, false, 0, 0, 32, 66577UL,424 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, false,{1, 29, 11}, {230, 29, 2687}, {230, 11, 2687}, {1, 29, 11}, {230, 29, 2687}, {230, 11, 2687}, false, 0, 0, 32, 66577UL,
425- "32 11 2687 29 16 256 32 16 256 32 29 1 1 1 1 0 0 16909313 0 16 1 0 230 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT425+ "32 11 2687 29 16 128 32 256 128 32 29 1 1 1 1 0 0 16909313 0 256 1 0 230 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT
426 },426 },
427 {427 {
428 "FusedMatMul_950_bmm_aFullLoad_relu", "FusedMatMul", "relu", R"({"_pattern": "BatchMatMul", "attrs":{"transpose_a":true,"transpose_b":false, "offset_x":0, "enable_hf32": 1},428 "FusedMatMul_950_bmm_aFullLoad_relu", "FusedMatMul", "relu", R"({"_pattern": "BatchMatMul", "attrs":{"transpose_a":true,"transpose_b":false, "offset_x":0, "enable_hf32": 1},
@@ -431,7 +431,7 @@ static TilingTestParam ascend950_cases_params[] = {
431 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },431 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
432 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",432 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
433 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, false,{1, 29, 11}, {230, 29, 2687}, {230, 11, 2687}, {1, 29, 11}, {230, 29, 2687}, {230, 11, 2687}, false, 0, 0, 32, 83952657UL,433 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, false,{1, 29, 11}, {230, 29, 2687}, {230, 11, 2687}, {1, 29, 11}, {230, 29, 2687}, {230, 11, 2687}, false, 0, 0, 32, 83952657UL,
434- "32 11 2687 29 16 256 32 16 256 32 29 1 1 1 1 0 0 16909313 0 16 1 0 230 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT434+ "32 11 2687 29 16 128 32 256 128 32 29 1 1 1 1 0 0 16909313 0 256 1 0 230 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT
435 },435 },
436 {436 {
437 "FusedMatMul_950_bmm_bFullLoad_empty", "FusedMatMul", "", R"({"_pattern": "BatchMatMul", "attrs":{"transpose_a":true,"transpose_b":false, "offset_x":0, "enable_hf32": 1},437 "FusedMatMul_950_bmm_bFullLoad_empty", "FusedMatMul", "", R"({"_pattern": "BatchMatMul", "attrs":{"transpose_a":true,"transpose_b":false, "offset_x":0, "enable_hf32": 1},
@@ -440,7 +440,7 @@ static TilingTestParam ascend950_cases_params[] = {
440 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },440 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
441 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",441 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
442 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, false,{1, 3984, 9040}, {1, 3984, 16}, {1, 9040, 16}, {1, 3984, 9040}, {1, 3984, 16}, {1, 9040, 16}, false, 0, 0, 32, 132113UL,442 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, false,{1, 3984, 9040}, {1, 3984, 16}, {1, 9040, 16}, {1, 3984, 9040}, {1, 3984, 16}, {1, 9040, 16}, false, 0, 0, 32, 132113UL,
443- "32 9040 16 3984 256 16 128 256 16 32 3984 8 1 1 1 0 0 33686017 0 256 1 0 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT443+ "32 9040 16 3984 128 16 96 128 256 32 3984 4 1 1 1 0 0 33686529 0 128 1 0 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT
444 },444 },
445 {445 {
446 "FusedMatMul_950_bmm_bFullLoad_relu", "FusedMatMul", "relu", R"({"_pattern": "BatchMatMul", "attrs":{"transpose_a":true,"transpose_b":false, "offset_x":0, "enable_hf32": 1},446 "FusedMatMul_950_bmm_bFullLoad_relu", "FusedMatMul", "relu", R"({"_pattern": "BatchMatMul", "attrs":{"transpose_a":true,"transpose_b":false, "offset_x":0, "enable_hf32": 1},
@@ -449,7 +449,7 @@ static TilingTestParam ascend950_cases_params[] = {
449 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },449 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
450 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",450 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
451 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, false,{1, 3984, 9040}, {1, 3984, 16}, {1, 9040, 16}, {1, 3984, 9040}, {1, 3984, 16}, {1, 9040, 16}, false, 0, 0, 32, 84018193UL,451 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, false,{1, 3984, 9040}, {1, 3984, 16}, {1, 9040, 16}, {1, 3984, 9040}, {1, 3984, 16}, {1, 9040, 16}, false, 0, 0, 32, 84018193UL,
452- "32 9040 16 3984 256 16 128 256 16 32 3984 8 1 1 1 0 0 33686017 0 256 1 0 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT452+ "32 9040 16 3984 128 16 96 128 256 32 3984 4 1 1 1 0 0 33686529 0 128 1 0 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT
453 },453 },
454 {454 {
455 "FusedMatMul_950_mmoe_basic_aswt_noFixpip_aFullLoad_empty", "FusedMatMul", "", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "enable_hf32":0},455 "FusedMatMul_950_mmoe_basic_aswt_noFixpip_aFullLoad_empty", "FusedMatMul", "", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "enable_hf32":0},
@@ -458,7 +458,7 @@ static TilingTestParam ascend950_cases_params[] = {
458 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },458 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
459 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",459 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
460 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, false, true,{200, 128}, {128, 48000}, {200, 48000}, {200, 128}, {128, 48000}, {200, 48000}, false, 0, 0, 32, 65537UL,460 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, false, true,{200, 128}, {128, 48000}, {200, 48000}, {200, 128}, {128, 48000}, {200, 48000}, false, 0, 0, 32, 65537UL,
461- "32 200 48000 128 208 128 128 208 128 64 128 1 1 1 1 0 0 16909312 0 208 1 0 "461+ "32 200 48000 128 208 128 128 208 128 64 128 1 1 1 1 0 0 33686528 0 208 1 0 "
462 },462 },
463 {463 {
464 "FusedMatMul_950_mmoe_basic_aswt_noFixpip_aFullLoad_relu", "FusedMatMul", "relu", R"({"_pattern": "MatMul", "attrs":{"transpose_a":true,"transpose_b":false, "offset_x":0, "enable_hf32": 1},464 "FusedMatMul_950_mmoe_basic_aswt_noFixpip_aFullLoad_relu", "FusedMatMul", "relu", R"({"_pattern": "MatMul", "attrs":{"transpose_a":true,"transpose_b":false, "offset_x":0, "enable_hf32": 1},
@@ -467,7 +467,7 @@ static TilingTestParam ascend950_cases_params[] = {
467 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },467 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
468 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",468 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
469 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, true,{3584, 4}, {3584, 18944}, {4, 18944}, {3584, 4}, {3584, 18944}, {4, 18944}, false, 0, 0, 32, 83951633UL,469 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, true, true,{3584, 4}, {3584, 18944}, {4, 18944}, {3584, 4}, {3584, 18944}, {4, 18944}, false, 0, 0, 32, 83951633UL,
470- "32 4 18944 3584 16 256 64 16 256 32 3584 1 3 1 1 0 0 16909313 2 16 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT470+ "32 4 18944 3584 16 320 48 16 320 16 3584 1 1 1 1 0 0 33686529 2 16 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT
471 },471 },
472 {472 {
473 "FusedMatMul_950_mmoe_basic_aswt_noFixpip_bFullLoad_empty", "FusedMatMul", "", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "enable_hf32":0},473 "FusedMatMul_950_mmoe_basic_aswt_noFixpip_bFullLoad_empty", "FusedMatMul", "", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "enable_hf32":0},
@@ -484,8 +484,8 @@ static TilingTestParam ascend950_cases_params[] = {
484 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,484 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,
485 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },485 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
486 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",486 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
487- ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, true, true,{11024, 56}, {62, 56}, {11024, 62}, {11024, 56}, {62, 56}, {11024, 62}, false, 0, 0, 32, 84017185UL,487+ ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, true, true,{11024, 56}, {62, 56}, {11024, 62}, {11024, 56}, {62, 56}, {11024, 62}, false, 0, 0, 32, 83886113UL,
488- "32 11024 62 56 256 64 64 256 64 32 56 2 1 1 1 0 0 33686017 0 256 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT488+ "32 11024 62 56 352 64 64 352 64 16 56 1 1 1 1 0 0 33686017 0 352 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT, ge::DT_FLOAT
489 },489 },
490 {490 {
491 "FusedMatMul_950_mmoe_basic_aswt_fixpipe1v2_bFullLoad_empty", "FusedMatMul", "", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "enable_hf32":1},491 "FusedMatMul_950_mmoe_basic_aswt_fixpipe1v2_bFullLoad_empty", "FusedMatMul", "", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "enable_hf32":1},
Mmatmul/gemm_v3/tests/ut/op_host/test_gemm_v3_tiling.cpp+2-2
@@ -207,8 +207,8 @@ static TilingTestParam general_cases_params[] = {
207 "block_dim":{"CORE_NUM":32},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,207 "block_dim":{"CORE_NUM":32},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,
208 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "socVersion": "Ascend950" },208 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "socVersion": "Ascend950" },
209 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",209 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
210- ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, false, {249, 512}, {512, 311}, {249, 311}, false, 0, 0, 28, 0UL,210+ ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, false, {249, 512}, {512, 311}, {249, 311}, false, 0, 0, 30, 0UL,
211- "28 249 311 512 512 64 48 512 64 48 256 8 8 1 1 0 0 0 0 278528 16384 0 1 1 1 1 4 4 0 0 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 4"211+ "30 249 311 512 512 48 64 512 48 64 256 4 4 1 1 0 0 0 0 1 1 1 1 2 2 2 2 2 0 0 1 1 1 1 1 0 0 0 4 0"
212 },212 },
213};213};
214 214 
Dmatmul/mat_mul_v3/op_host/op_tiling/arch35/matmul_v3_asw_loadbalance_table.h+0-91
@@ -1,91 +0,0 @@
1-/**
2- * Copyright (c) 2025 Huawei Technologies Co., Ltd.
3- * This program is free software, you can redistribute it and/or modify it under the terms and conditions of
4- * CANN Open Software License Agreement Version 2.0 (the "License").
5- * Please refer to the License for details. You may not use this file except in compliance with the License.
6- * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED,
7- * INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
8- * See LICENSE in the root of the software repository for the full text of the License.
9- */
10- 
11- 
12-/* !
13- * \file matmul_v3_asw_loadbalance_table.h
14- * \brief
15- */
16-#pragma once
17- 
18-#include <vector>
19-#include <cstdint>
20-#include "matmul_v3_common_advanced.h"
21-namespace optiling {
22-namespace matmul_v3_advanced {
23-// X1维度档位点快速查找索引表{block, counts, index}
24-// block:待查找的base块， counts:base块可用的列表个数，index:base块对应的TABLE索引
25-const std::vector<std::tuple<uint64_t, uint64_t, uint64_t>> BLOCK_LOOKUP_TABLE = {
26- {336, 6, 0}, {320, 5, 6}, {304, 6, 11}, {288, 7, 17}, {272, 8, 24},
27- {256, 9, 32}, {240, 10, 41}, {224, 10, 51}, {208, 11, 61}, {192, 12, 72},
28- {176, 12, 84}, {160, 11, 96}, {144, 9, 107}, {128, 7, 116}, {112, 1, 123}};
29- 
30-// 查找BLOCK在基本块维度表中的位置信息
31-inline bool FindLoadBalanceInfo(uint64_t block, uint64_t& startIndex, uint64_t& count)
32-{
33- for (const auto& entry : BLOCK_LOOKUP_TABLE) {
34- if (std::get<0>(entry) == block) {
35- startIndex = std::get<NUM_TWO>(entry);
36- count = std::get<1>(entry);
37- return true;
38- }
39- }
40- return false;
41-}
42- 
43-// 基本块维度表（X1,X2,X3,X4,X5），按X1,X2,X3从大到小排序,
44-// X4输入折算系数(由于base块调整后需求带宽变高，因此一些base块需要折算系数)，X5输出折算系数(当前未使用，等待fixp优化)
45-const std::vector<std::tuple<uint64_t, uint64_t, uint64_t, double, double>> BLOCK_TABLE = {
46- {336, 192, 48, 1, 1.126}, {336, 176, 48, 1, 1.126}, {336, 160, 48, 1, 1.126},
47- {336, 144, 48, 1.073, 1.126}, {336, 128, 48, 1.167, 1.126}, {336, 112, 48, 1.287, 1.126},
48- {320, 192, 48, 1, 1.126}, {320, 176, 48, 1, 1.126}, {320, 160, 48, 1.014, 1.126},
49- {320, 144, 48, 1.089, 1.126}, {320, 128, 48, 1.183, 1.126}, {304, 208, 48, 1, 1.126},
50- {304, 192, 48, 1, 1.126}, {304, 176, 48, 1, 1.126}, {304, 160, 48, 1.032, 1.126},
51- {304, 144, 48, 1.107, 1.126}, {304, 128, 48, 1.201, 1.126}, {288, 224, 48, 1, 1.126},
52- {288, 208, 48, 1, 1.126}, {288, 192, 48, 1, 1.126}, {288, 176, 48, 1, 1.126},
53- {288, 160, 48, 1.051, 1.126}, {288, 144, 48, 1.126, 1.126}, {288, 128, 48, 1.220, 1.126},
54- {272, 240, 48, 1, 1.126}, {272, 224, 48, 1, 1.126}, {272, 208, 48, 1, 1.126},
55- {272, 192, 48, 1, 1.126}, {272, 176, 48, 1.012, 1.126}, {272, 160, 48, 1.073, 1.126},
56- {272, 144, 48, 1.148, 1.126}, {272, 128, 48, 1.242, 1.126}, {256, 256, 64, 1, 1},
57- {256, 240, 64, 1, 1}, {256, 224, 64, 1, 1}, {256, 208, 64, 1, 1},
58- {256, 192, 64, 1, 1}, {256, 176, 64, 1.037, 1}, {256, 160, 64, 1.098, 1},
59- {256, 144, 64, 1.173, 1}, {256, 128, 64, 1.267, 1}, {240, 272, 48, 1, 1.126},
60- {240, 256, 64, 1, 1}, {240, 240, 64, 1, 1}, {240, 224, 64, 1, 1},
61- {240, 208, 64, 1, 1}, {240, 192, 64, 1.014, 1}, {240, 176, 64, 1.065, 1},
62- {240, 160, 64, 1.126, 1}, {240, 144, 64, 1.201, 1}, {240, 128, 64, 1.295, 1},
63- {224, 288, 48, 1, 1.126}, {224, 272, 48, 1, 1.126}, {224, 256, 64, 1, 1},
64- {224, 240, 64, 1, 1}, {224, 224, 64, 1, 1}, {224, 208, 64, 1.003, 1},
65- {224, 192, 64, 1.046, 1}, {224, 176, 64, 1.097, 1}, {224, 160, 64, 1.159, 1},
66- {224, 144, 64, 1.234, 1}, {208, 304, 48, 1, 1.126}, {208, 288, 48, 1, 1.126},
67- {208, 272, 48, 1, 1.126}, {208, 256, 64, 1, 1}, {208, 240, 64, 1, 1},
68- {208, 224, 64, 1.003, 1}, {208, 208, 64, 1.04, 1}, {208, 192, 64, 1.083, 1},
69- {208, 176, 64, 1.134, 1}, {208, 160, 64, 1.196, 1}, {208, 144, 64, 1.271, 1},
70- {192, 336, 48, 1, 1.126}, {192, 320, 48, 1, 1.126}, {192, 304, 48, 1, 1.126},
71- {192, 288, 48, 1, 1.126}, {192, 272, 48, 1, 1.126}, {192, 256, 64, 1, 1},
72- {192, 240, 64, 1.014, 1}, {192, 224, 64, 1.046, 1}, {192, 208, 64, 1.083, 1},
73- {192, 192, 80, 1.126, 1}, {192, 176, 80, 1.178, 1}, {192, 160, 80, 1.239, 1},
74- {176, 336, 48, 1, 1.126}, {176, 320, 48, 1, 1.126}, {176, 304, 48, 1, 1.126},
75- {176, 288, 48, 1, 1.126}, {176, 272, 48, 1.012, 1.126}, {176, 256, 64, 1.037, 1},
76- {176, 240, 64, 1.065, 1}, {176, 224, 64, 1.097, 1}, {176, 208, 64, 1.134, 1},
77- {176, 192, 80, 1.178, 1}, {176, 176, 80, 1.229, 1}, {176, 160, 80, 1.290, 1},
78- {160, 336, 48, 1, 1.126}, {160, 320, 48, 1.014, 1.126}, {160, 304, 48, 1.032, 1.126},
79- {160, 288, 48, 1.051, 1.126}, {160, 272, 48, 1.073, 1.126}, {160, 256, 64, 1.098, 1},
80- {160, 240, 64, 1.126, 1}, {160, 224, 64, 1.159, 1}, {160, 208, 64, 1.196, 1},
81- {160, 192, 80, 1.239, 1}, {160, 176, 80, 1.290, 1}, {144, 336, 48, 1.073, 1.126},
82- {144, 320, 48, 1.089, 1.126}, {144, 304, 48, 1.107, 1.126}, {144, 288, 48, 1.126, 1.126},
83- {144, 272, 48, 1.148, 1.126}, {144, 256, 64, 1.173, 1}, {144, 240, 64, 1.201, 1},
84- {144, 224, 64, 1.234, 1}, {144, 208, 64, 1.271, 1}, {128, 336, 48, 1.167, 1.126},
85- {128, 320, 48, 1.183, 1.126}, {128, 304, 48, 1.201, 1.126}, {128, 288, 48, 1.220, 1.126},
86- {128, 272, 48, 1.242, 1.126}, {128, 256, 64, 1.267, 1}, {128, 240, 64, 1.295, 1},
87- {112, 336, 48, 1.287, 1.126}
88-};
89-} // namespace matmul_v3_advanced
90-} // namespace optiling
91- 
Mmatmul/mat_mul_v3/op_host/op_tiling/arch35/matmul_v3_asw_tiling.cpp+8-478
@@ -16,101 +16,9 @@
16#include "matmul_v3_tiling_strategy.h"16#include "matmul_v3_tiling_strategy.h"
17#include "./matmul_tiling_registry.h"17#include "./matmul_tiling_registry.h"
18#include "matmul/common/op_host/math_util.h"18#include "matmul/common/op_host/math_util.h"
19-#include "matmul_v3_asw_loadbalance_table.h"
20 19 
21using Ops::NN::MathUtil;20using Ops::NN::MathUtil;
22 21 
23-namespace {
24-using namespace optiling;
25-using namespace matmul_v3_advanced;
26- 
27-constexpr uint64_t MIN_BASE_BLOCK = 112UL;
28-constexpr uint64_t MAX_BASE_BLOCK = 336UL;
29-constexpr double LOAD_BALANCING_THRESHOLD = 0.98;
30-// 负载均衡与重复搬运量归一化阈值
31-constexpr double BALANCE_REDUNDANT_THRESHOLD = 0.97;
32-constexpr double MIN_EQUALIZATION_COEFFICIENT = 1.02;
33-constexpr double LOAD_BALANCE_RATE_LIMIT = 0.88;
34-constexpr double MAX_SINGLE_CORE_ROUND = 10.0;
35-constexpr int MAX_LOOP_NUM = 20;
36-constexpr uint64_t NUM_NINE = 9UL;
37-constexpr uint64_t NUM_TEN = 10UL;
38- 
39-// 计算多核负载均衡率
40-static double CalcMultiCoreBalance(uint64_t M, uint64_t N, uint64_t coreNum, uint64_t baseM, uint64_t baseN)
41-{
42- if (baseM == 0UL || baseN == 0UL) {
43- return 0.0;
44- }
45- uint64_t mCnt = MathUtil::CeilDivision(M, baseM);
46- uint64_t nCnt = MathUtil::CeilDivision(N, baseN);
47- uint64_t mTail = M % baseM;
48- uint64_t nTail = N % baseN;
49- uint64_t mMainCnt = M / baseM;
50- uint64_t nMainCnt = N / baseN;
51- uint64_t totalTiles = mCnt * nCnt;
52- uint64_t totalMainTiles = mMainCnt * nMainCnt;
53- if (totalTiles == 0UL || coreNum == 0UL) {
54- return 0.0;
55- }
56- // 计算每个核分配的块数分布
57- double avgLoad = static_cast<double>(M * N) / coreNum;
58- 
59- // 单核计算最大尾块
60- uint64_t singleMaxTail = std::max(baseM * nTail, baseN * mTail);
61- 
62- // 尾块数
63- uint64_t coreTailNum = totalTiles % coreNum;
64- // 尾块均分比例
65- uint64_t tailRatio = coreTailNum != 0UL ? coreNum / coreTailNum : 1UL;
66- 
67- auto getDiv = [](uint64_t base) -> uint64_t {
68- if (base % BASIC_BLOCK_SIZE_256 == 0UL) {
69- return BASIC_BLOCK_SIZE_16;
70- } else if (base % BASIC_BLOCK_SIZE_128 == 0UL) {
71- return BASIC_BLOCK_SIZE_16 / NUM_TWO;
72- } else if (base % BASIC_BLOCK_SIZE_64 == 0UL) {
73- return NUM_FOUR;
74- } else if (base % BLOCK_BYTE_SIZE == 0UL) {
75- return NUM_TWO;
76- } else {
77- return 1UL;
78- }
79- };
80- uint64_t mDiv = getDiv(baseM);
81- uint64_t nDiv = getDiv(baseN);
82- 
83- tailRatio = std::min(tailRatio, mDiv * nDiv);
84- uint64_t tailNum =
85- MathUtil::CeilDivision(mCnt * nCnt, coreNum) - MathUtil::CeilDivision(mMainCnt * nMainCnt, coreNum);
86- uint64_t noDivTailNum = tailNum >= NUM_TWO ? tailNum - 1UL : 0UL;
87- 
88- // 单核实际计算量
89- double maxLoad;
90- if (tailNum == 0UL) {
91- // 主块+无法切分主块的负载均衡
92- maxLoad = static_cast<double>(totalMainTiles / coreNum) * baseM * baseN +
93- static_cast<double>(MathUtil::CeilDivision(totalMainTiles, coreNum) - totalMainTiles / coreNum) *
94- baseM * baseN / tailRatio;
95- } else {
96- // 主块向上取整+尾块的负载均衡
97- maxLoad = static_cast<double>(
98- MathUtil::CeilDivision(totalMainTiles, coreNum) * baseM * baseN + noDivTailNum * singleMaxTail +
99- (tailNum - noDivTailNum) * singleMaxTail / tailRatio);
100- }
101- return avgLoad / maxLoad; // 负载均衡率：1.0为完全均衡
102-}
103- 
104-// 计算重复搬运量
105-static uint64_t CalcRedundantDataMovement(uint64_t baseM, uint64_t baseN, uint64_t mValue, uint64_t nValue)
106-{
107- uint64_t mBlocks = MathUtil::CeilDivision(mValue, baseM);
108- uint64_t nBlocks = MathUtil::CeilDivision(nValue, baseN);
109- uint64_t totalMovement = mBlocks * nValue + nBlocks * mValue;
110- return totalMovement - (mValue + nValue);
111-}
112-} // namespace
113- 
114namespace optiling {22namespace optiling {
115namespace matmul_v3_advanced {23namespace matmul_v3_advanced {
116using namespace strategy;24using namespace strategy;
@@ -126,401 +34,23 @@ void MatMulV3AswTiling::CalcTailBasicBlock()
126 runInfo_.tailInfo.mCnt = 1UL;34 runInfo_.tailInfo.mCnt = 1UL;
127 runInfo_.tailInfo.nCnt = 1UL;35 runInfo_.tailInfo.nCnt = 1UL;
128 if (tailCnt != 0UL) {36 if (tailCnt != 0UL) {
129- while ((runInfo_.tailInfo.mCnt + 1UL) * runInfo_.tailInfo.nCnt * tailCnt <= compileInfo_.aicNum) {37+ while ((runInfo_.tailInfo.mCnt + 1UL) * runInfo_.tailInfo.nCnt * tailCnt <= compileInfo_.aicNum &&
38+ (!args_.isATrans || MathUtil::CeilDivision(runInfo_.baseM, runInfo_.tailInfo.mCnt) *
39+ args_.aDtypeSize > BASIC_BLOCK_K_128_BYTE)) {
130 runInfo_.tailInfo.mCnt += 1UL;40 runInfo_.tailInfo.mCnt += 1UL;
131- if (runInfo_.tailInfo.mCnt * (runInfo_.tailInfo.nCnt + 1UL) * tailCnt <= compileInfo_.aicNum) {41+ if (runInfo_.tailInfo.mCnt * (runInfo_.tailInfo.nCnt + 1UL) * tailCnt <= compileInfo_.aicNum &&
42+ (args_.isBTrans || MathUtil::CeilDivision(runInfo_.baseN, runInfo_.tailInfo.nCnt) *
43+ args_.bDtypeSize > BASIC_BLOCK_K_128_BYTE)) {
132 runInfo_.tailInfo.nCnt += 1UL;44 runInfo_.tailInfo.nCnt += 1UL;
133 }45 }
134 }46 }
135 }47 }
136}48}
137 49 
138-void MatMulV3AswTiling::GetOuterAxisTailCnt(bool nLoadBalance, uint64_t& baseTailSplitCnt, uint64_t& tailMain)
139-{
140- uint64_t aicNum = compileInfo_.aicNum;
141- uint64_t x = args_.mValue;
142- uint64_t y = args_.nValue;
143- uint64_t baseX = runInfo_.baseM;
144- uint64_t baseY = runInfo_.baseN;
145- if (nLoadBalance) {
146- x = args_.nValue;
147- y = args_.mValue;
148- baseX = runInfo_.baseN;
149- baseY = runInfo_.baseM;
150- }
151- 
152- uint64_t xCnt = MathUtil::CeilDivision(x, baseX);
153- uint64_t yCnt = MathUtil::CeilDivision(y, baseY);
154- uint64_t xTail = x % baseX;
155- 
156- uint64_t aswWindowLen = GetAswWindowLen();
157- uint64_t totalWindows = MathUtil::CeilDivision(xCnt * yCnt, aicNum);
158- uint64_t mainWindows = MathUtil::CeilDivision((xCnt - 1UL) * yCnt + yCnt % aicNum, aicNum);
159- // 未做负载均衡的轴是核数的倍数且做负载均衡的轴是窗口的因子或轴的倍数，说明部分核只做主块
160- if (yCnt % aicNum == 0UL && (xCnt % aswWindowLen == 0UL || aswWindowLen % xCnt == 0UL)) {
161- mainWindows = totalWindows;
162- }
163- uint64_t tailWindows = totalWindows - mainWindows;
164- uint64_t perfRes = mainWindows * baseX + tailWindows * xTail;
165- 
166- uint64_t baseTailCntMax = 1UL;
167- baseTailCntMax = std::min((baseX - xTail) / BASIC_BLOCK_SIZE_16, xCnt);
168- 
169- for (uint64_t mergeLen = 1UL; mergeLen < baseTailCntMax; ++mergeLen) {
170- uint64_t newTailMain =
171- MathUtil::Align(MathUtil::CeilDivision((mergeLen * baseX + xTail), mergeLen + 1UL), BASIC_BLOCK_SIZE_16);
172- uint64_t newTailLast = mergeLen * (baseX - newTailMain) + xTail;
173- uint64_t newMainRound = 0UL;
174- uint64_t newTailRound = 0UL;
175- if (mergeLen < xCnt - 1UL) {
176- // 按照最差的场景计算合并后的主轮，所以性能不会最优
177- newMainRound =
178- MathUtil::CeilDivision((xCnt - 1UL - mergeLen) * yCnt + (mergeLen + 1UL) * yCnt % aicNum, aicNum);
179- }
180- if (mergeLen > 0UL) {
181- newTailRound =
182- std::min(MathUtil::CeilDivision(mergeLen * yCnt + yCnt % aicNum, aicNum), totalWindows - newMainRound);
183- }
184- uint64_t curPerf = newMainRound * baseX + newTailRound * newTailMain +
185- (totalWindows - newMainRound - newTailRound) * newTailLast;
186- // m轴尽量多分基本块，n轴少分基本块
187- if (curPerf < perfRes || (!nLoadBalance && curPerf == perfRes)) {
188- perfRes = curPerf;
189- tailMain = newTailMain;
190- baseTailSplitCnt = mergeLen + 1UL;
191- }
192- }
193-}
194- 
195-void MatMulV3AswTiling::OptimizeEdgeBasicBlock()
196-{
197- uint64_t mCore = MathUtil::CeilDivision(args_.mValue, runInfo_.baseM);
198- uint64_t nCore = MathUtil::CeilDivision(args_.nValue, runInfo_.baseN);
199- if (mCore * nCore < compileInfo_.aicNum || mCore == 1UL || nCore == 1UL) {
200- return;
201- }
202- uint64_t mBaseTail = args_.mValue % runInfo_.baseM;
203- uint64_t nBaseTail = args_.nValue % runInfo_.baseN;
204- 
205- // 判断均衡后是否会进入fixp模板
206- bool balancePostFixp = args_.kValue <= BASIC_BLOCK_SIZE_256 && args_.nValue % BLOCK_BYTE_SIZE == 0UL;
207- if (mBaseTail > 0UL && !args_.isATrans && (nBaseTail == 0UL || mBaseTail <= nBaseTail || balancePostFixp)) {
208- GetOuterAxisTailCnt(false, runInfo_.mBaseTailSplitCnt, runInfo_.tailInfo.mTailMain);
209- } else if (nBaseTail > 0UL && args_.isBTrans && !balancePostFixp) {
210- GetOuterAxisTailCnt(true, runInfo_.nBaseTailSplitCnt, runInfo_.tailInfo.nTailMain);
211- }
212-}
213- 
214-// 计算singleX=√(m * n)/coreNum
215-void MatMulV3AswTiling::CalcSingleX(uint64_t& higherSingleX, uint64_t& lowerSingleX)
216-{
217- double data = static_cast<double>(args_.mValue * args_.nValue) / compileInfo_.aicNum;
218- 
219- while (data > static_cast<double>(BASIC_BLOCK_SIZE_256 * BASIC_BLOCK_SIZE_256)) {
220- data /= NUM_TWO;
221- }
222- 
223- double bestValue = std::sqrt(data);
224- higherSingleX = ops::CeilAlign(static_cast<uint64_t>(std::ceil(bestValue)), BASIC_BLOCK_SIZE_16);
225- lowerSingleX = ops::FloorAlign(static_cast<uint64_t>(std::floor(bestValue)), BASIC_BLOCK_SIZE_16);
226-}
227- 
228-void MatMulV3AswTiling::CalcBasicBlock()
229-{
230- uint64_t mCore = MathUtil::CeilDivision(args_.mValue, runInfo_.baseM);
231- uint64_t nCore = MathUtil::CeilDivision(args_.nValue, runInfo_.baseN);
232- if (mCore == 0UL || nCore == 0UL) {
233- return;
234- }
235- if (mCore <= nCore) {
236- runInfo_.baseM = ops::CeilAlign(MathUtil::CeilDivision(args_.mValue, mCore), BASIC_BLOCK_SIZE_16);
237- mCore = MathUtil::CeilDivision(args_.mValue, runInfo_.baseM);
238- nCore = runInfo_.usedCoreNum / mCore;
239- runInfo_.baseN = ops::CeilAlign(MathUtil::CeilDivision(args_.nValue, nCore), BASIC_BLOCK_SIZE_16);
240- } else {
241- runInfo_.baseN = ops::CeilAlign(MathUtil::CeilDivision(args_.nValue, nCore), BASIC_BLOCK_SIZE_16);
242- nCore = MathUtil::CeilDivision(args_.nValue, runInfo_.baseN);
243- mCore = runInfo_.usedCoreNum / nCore;
244- runInfo_.baseM = ops::CeilAlign(MathUtil::CeilDivision(args_.mValue, mCore), BASIC_BLOCK_SIZE_16);
245- }
246- 
247- while (runInfo_.baseN >= runInfo_.baseM * NUM_TWO && nCore < runInfo_.usedCoreNum / NUM_TWO) {
248- nCore = nCore * NUM_TWO;
249- mCore = runInfo_.usedCoreNum / nCore;
250- runInfo_.baseM = ops::CeilAlign(MathUtil::CeilDivision(args_.mValue, mCore), BASIC_BLOCK_SIZE_16);
251- runInfo_.baseN = ops::CeilAlign(MathUtil::CeilDivision(args_.nValue, nCore), BASIC_BLOCK_SIZE_16);
252- mCore = MathUtil::CeilDivision(args_.mValue, static_cast<uint64_t>(runInfo_.baseM));
253- nCore = MathUtil::CeilDivision(args_.nValue, static_cast<uint64_t>(runInfo_.baseN));
254- }
255- 
256- while (runInfo_.baseM >= runInfo_.baseN * NUM_TWO && mCore < runInfo_.usedCoreNum / NUM_TWO) {
257- mCore = mCore * NUM_TWO;
258- nCore = runInfo_.usedCoreNum / mCore;
259- runInfo_.baseM = ops::CeilAlign(MathUtil::CeilDivision(args_.mValue, mCore), BASIC_BLOCK_SIZE_16);
260- runInfo_.baseN = ops::CeilAlign(MathUtil::CeilDivision(args_.nValue, nCore), BASIC_BLOCK_SIZE_16);
261- mCore = MathUtil::CeilDivision(args_.mValue, static_cast<uint64_t>(runInfo_.baseM));
262- nCore = MathUtil::CeilDivision(args_.nValue, static_cast<uint64_t>(runInfo_.baseN));
263- }
264-}
265- 
266-void MatMulV3AswTiling::FormulateBasicBlock()
267-{
268- uint64_t mCore = MathUtil::CeilDivision(args_.mValue, runInfo_.baseM);
269- uint64_t nCore = MathUtil::CeilDivision(args_.nValue, runInfo_.baseN);
270- if (mCore * nCore >= compileInfo_.aicNum) {
271- runInfo_.baseM = std::min(ops::CeilAlign(args_.mValue, BASIC_BLOCK_SIZE_16), runInfo_.baseM);
272- runInfo_.baseN = std::min(ops::CeilAlign(args_.nValue, BASIC_BLOCK_SIZE_16), runInfo_.baseN);
273- return;
274- }
275- CalcBasicBlock();
276- mCore = MathUtil::CeilDivision(args_.mValue, runInfo_.baseM);
277- nCore = MathUtil::CeilDivision(args_.nValue, runInfo_.baseN);
278- runInfo_.usedCoreNum = mCore * nCore;
279- uint64_t kValueAlign = ops::CeilAlign(static_cast<uint64_t>(args_.kValue), BASIC_BLOCK_SIZE_16);
280- uint64_t kValueMax = ops::FloorAlign(
281- L0A_SIZE_2 / DB_SIZE / args_.aDtypeSize / std::max(runInfo_.baseM, runInfo_.baseN), BASIC_BLOCK_SIZE_16);
282- runInfo_.baseK = std::min(kValueAlign, kValueMax);
283-}
284- 
285-void MatMulV3AswTiling::FormulateLoadBalanceBlock()
286-{
287- runInfo_.baseM = std::min(ops::CeilAlign(args_.mValue, BASIC_BLOCK_SIZE_16), runInfo_.baseM);
288- runInfo_.baseN = std::min(ops::CeilAlign(args_.nValue, BASIC_BLOCK_SIZE_16), runInfo_.baseN);
289- 
290- // 计算默认负载均衡率
291- runInfo_.defaultBalance =
292- CalcMultiCoreBalance(args_.mValue, args_.nValue, compileInfo_.aicNum, runInfo_.baseM, runInfo_.baseN);
293- // 重复搬运量
294- runInfo_.redundantData = CalcRedundantDataMovement(runInfo_.baseM, runInfo_.baseN, args_.mValue, args_.nValue);
295- 
296- uint64_t mCore = MathUtil::CeilDivision(args_.mValue, runInfo_.baseM);
297- uint64_t nCore = MathUtil::CeilDivision(args_.nValue, runInfo_.baseN);
298- 
299- double singleBlockNum = static_cast<double>(mCore * nCore / compileInfo_.aicNum);
300- 
301- // 判断是否需要重选基本块
302- bool needReselect = singleBlockNum >= 1.0 && singleBlockNum <= MAX_SINGLE_CORE_ROUND &&
303- runInfo_.defaultBalance < LOAD_BALANCE_RATE_LIMIT;
304- 
305- // 如果不需要重选，直接使用默认值
306- if (needReselect) {
307- uint64_t higherSingleX;
308- uint64_t lowerSingleX;
309- CalcSingleX(higherSingleX, lowerSingleX);
310- 
311- uint64_t minMN = ops::CeilAlign(std::min(args_.mValue, args_.nValue), BASIC_BLOCK_SIZE_16);
312- uint64_t maxMN = ops::CeilAlign(std::max(args_.mValue, args_.nValue), BASIC_BLOCK_SIZE_16);
313- bool isMLarger = (args_.mValue > args_.nValue);
314- // 根据不同场景选择基本块
315- if (lowerSingleX >= minMN) {
316- HandleLargeSingleSide(minMN, maxMN, isMLarger);
317- } else {
318- HandleLargeBothSides(higherSingleX, lowerSingleX, minMN, isMLarger);
319- }
320- }
321- 
322- // 处理mCore * nCore / coreNum < 1的情况
323- if (singleBlockNum < 1.0) {
324- CalcBasicBlock();
325- }
326- runInfo_.baseM = ops::CeilAlign(runInfo_.baseM, BASIC_BLOCK_SIZE_16);
327- runInfo_.baseN = ops::CeilAlign(runInfo_.baseN, BASIC_BLOCK_SIZE_16);
328- // l0c的dtype是fp32
329- runInfo_.dbL0C = runInfo_.baseM * runInfo_.baseN * sizeof(float) * DB_SIZE <= compileInfo_.l0CSize ? DB_SIZE : 1UL;
330- 
331- mCore = MathUtil::CeilDivision(args_.mValue, runInfo_.baseM);
332- nCore = MathUtil::CeilDivision(args_.nValue, runInfo_.baseN);
333- runInfo_.usedCoreNum = std::min(mCore * nCore, compileInfo_.aicNum);
334- // 如果k是内轴，则可以对齐C0_size,否则以16个元素对齐
335- uint64_t baseKAlignValue = !args_.isATrans && args_.isBTrans && args_.aType == ge::DT_FLOAT ?
336- BLOCK_BYTE_SIZE / args_.aDtypeSize :
337- BASIC_BLOCK_SIZE_16;
338- uint64_t kValueAlign = ops::CeilAlign(static_cast<uint64_t>(args_.kValue), baseKAlignValue);
339- uint64_t kValueMax = ops::FloorAlign(
340- L0A_SIZE_2 / DB_SIZE / args_.aDtypeSize / std::max(runInfo_.baseM, runInfo_.baseN), baseKAlignValue);
341- runInfo_.baseK = std::min(kValueAlign, kValueMax);
342-}
343- 
344-// 单边大场景处理
345-uint64_t MatMulV3AswTiling::UpdateBaseBlock(uint64_t baseBlock, bool isMLarger)
346-{
347- if (!isMLarger) {
348- if (!args_.isBTrans || args_.kValue <= BASIC_BLOCK_SIZE_256) {
349- // n较大, n是内轴或k<=256 n对齐128B,外轴对齐64B
350- return ops::CeilAlign(baseBlock, BASIC_BLOCK_SIZE_128 / args_.bDtypeSize);
351- } else {
352- return ops::CeilAlign(baseBlock, BASIC_BLOCK_SIZE_64 / args_.bDtypeSize);
353- }
354- } else {
355- return ops::CeilAlign(baseBlock, BASIC_BLOCK_SIZE_16);
356- }
357-}
358- 
359-void MatMulV3AswTiling::CalcLargeSingleSide(uint64_t minMN, uint64_t maxMN, uint64_t& targetBase, bool isMLarger)
360-{
361- // ceil(核数*0.9)
362- uint64_t minCoreNum = (compileInfo_.aicNum + 1UL) * NUM_NINE / NUM_TEN;
363- for (uint64_t tmpCoreNum = compileInfo_.aicNum; tmpCoreNum >= minCoreNum; tmpCoreNum--) {
364- int loop = 1;
365- while (loop <= MAX_LOOP_NUM) { // loop/(loop+1)>=0.95 loop=19
366- uint64_t baseBlock = MathUtil::CeilDivision(maxMN, tmpCoreNum * loop);
367- baseBlock = UpdateBaseBlock(baseBlock, isMLarger);
368- uint64_t tileSize = baseBlock * minMN * sizeof(float);
369- if (baseBlock >= MIN_BASE_BLOCK && baseBlock <= MAX_BASE_BLOCK && tileSize <= compileInfo_.l0CSize) {
370- targetBase = baseBlock;
371- return;
372- }
373- loop++;
374- }
375- }
376- return;
377-}
378- 
379-void MatMulV3AswTiling::HandleLargeSingleSide(uint64_t minMN, uint64_t maxMN, bool isMLarger)
380-{
381- if (isMLarger) {
382- runInfo_.baseN = minMN;
383- runInfo_.baseM = compileInfo_.l0CSize / runInfo_.dbL0C / runInfo_.baseN / sizeof(float);
384- runInfo_.baseM = ops::FloorAlign(runInfo_.baseM, BASIC_BLOCK_SIZE_16);
385- CalcLargeSingleSide(minMN, maxMN, runInfo_.baseM, isMLarger);
386- } else {
387- runInfo_.baseM = minMN;
388- runInfo_.baseN = compileInfo_.l0CSize / runInfo_.dbL0C / runInfo_.baseM / sizeof(float);
389- runInfo_.baseN = ops::FloorAlign(runInfo_.baseN, BLOCK_BYTE_SIZE);
390- CalcLargeSingleSide(minMN, maxMN, runInfo_.baseN, isMLarger);
391- }
392-}
393- 
394-// 两边都比较大场景处理
395-bool MatMulV3AswTiling::UpdateBothBaseBlock(
396- double balance, CalcParams& params, uint64_t currentBaseM, uint64_t currentBaseN, uint64_t baseK)
397-{
398- // 调整base块后如果负载均衡率大于重复搬运率比值-1+0.03
399- if (balance > LOAD_BALANCING_THRESHOLD) {
400- // 如果调整base块后负载均衡率大于0.98则直接设置base块
401- runInfo_.baseM = currentBaseM;
402- runInfo_.baseN = currentBaseN;
403- runInfo_.baseK = baseK;
404- return true;
405- } else if ((balance > params.bestBalance) && (balance > MIN_EQUALIZATION_COEFFICIENT * runInfo_.defaultBalance)) {
406- params.bestBalance = balance;
407- params.baseM = currentBaseM;
408- params.baseN = currentBaseN;
409- params.baseK = baseK;
410- }
411- return false;
412-}
413- 
414-bool MatMulV3AswTiling::CalcBestBalance(CalcParams& params, bool isMLarger)
415-{
416- uint64_t startIndex;
417- uint64_t count;
418- uint64_t baseX = params.baseStart;
419- bool condition = params.isNegativeSign ? baseX >= params.baseEnd : baseX <= params.baseEnd;
420- while (condition) {
421- bool isFindStartIndex = FindLoadBalanceInfo(baseX, startIndex, count);
422- if (!isFindStartIndex) {
423- baseX = params.isNegativeSign ? baseX - BASIC_BLOCK_SIZE_16 : baseX + BASIC_BLOCK_SIZE_16;
424- condition = params.isNegativeSign ? baseX >= params.baseEnd : baseX <= params.baseEnd;
425- continue;
426- }
427- 
428- for (uint64_t i = 0; i < count; i++) {
429- if (startIndex + i >= BLOCK_TABLE.size()) {
430- break;
431- }
432- auto [x1, x2, x3, x4, x5] = BLOCK_TABLE[startIndex + i];
433- (void)x5;
434- // 如果k是外轴，则跳过无法对齐16的baseK
435- bool skipK = (args_.isATrans || !args_.isBTrans) && args_.aType == ge::DT_FLOAT &&
436- x3 / NUM_TWO % BASIC_BLOCK_SIZE_16 != 0;
437- if (x3 > args_.kValue || skipK) {
438- continue;
439- }
440- uint64_t currentBaseM = isMLarger ? x2 : x1;
441- uint64_t currentBaseN = isMLarger ? x1 : x2;
442- // n是内轴或k<=256 n对齐128B 否则对齐64B；m是内轴则对齐128B否则对齐64B
443- bool nNotAligned = !args_.isBTrans || args_.kValue <= BASIC_BLOCK_SIZE_256 ?
444- currentBaseN * args_.bDtypeSize % BASIC_BLOCK_SIZE_128 != 0UL :
445- currentBaseN * args_.bDtypeSize % BASIC_BLOCK_SIZE_64 != 0UL;
446- bool mNotAligned = args_.isATrans ? currentBaseM * args_.aDtypeSize % BASIC_BLOCK_SIZE_128 != 0UL :
447- currentBaseM * args_.aDtypeSize % BASIC_BLOCK_SIZE_64 != 0UL;
448- if (mNotAligned || nNotAligned) {
449- continue;
450- }
451- double balance =
452- CalcMultiCoreBalance(args_.mValue, args_.nValue, compileInfo_.aicNum, currentBaseM, currentBaseN) / x4;
453- double removeRatio = static_cast<double>(
454- CalcRedundantDataMovement(currentBaseM, currentBaseN, args_.mValue, args_.nValue) /
455- runInfo_.redundantData);
456- bool isUpdateBaseBlock = false;
457- if (balance - runInfo_.defaultBalance > removeRatio - BALANCE_REDUNDANT_THRESHOLD) {
458- isUpdateBaseBlock = UpdateBothBaseBlock(balance, params, currentBaseM, currentBaseN, x3);
459- }
460- if (isUpdateBaseBlock) {
461- return true;
462- }
463- }
464- baseX = params.isNegativeSign ? baseX - BASIC_BLOCK_SIZE_16 : baseX + BASIC_BLOCK_SIZE_16;
465- condition = params.isNegativeSign ? baseX >= params.baseEnd : baseX <= params.baseEnd;
466- }
467- return false;
468-}
469- 
470-void MatMulV3AswTiling::HandleLargeBothSides(
471- uint64_t higherSingleX, uint64_t lowerSingleX, uint64_t minMN, bool isMLarger)
472-{
473- CalcParams params1 = {
474- lowerSingleX,
475- MIN_BASE_BLOCK,
476- true,
477- runInfo_.defaultBalance,
478- BASIC_BLOCK_K_256_BYTE,
479- BASIC_BLOCK_K_256_BYTE,
480- BASIC_BLOCK_K_128_BYTE / args_.aDtypeSize};
481- if (CalcBestBalance(params1, isMLarger)) {
482- return;
483- }
484- 
485- CalcParams params2 = {
486- higherSingleX,
487- std::min(MAX_BASE_BLOCK, minMN),
488- false,
489- runInfo_.defaultBalance,
490- BASIC_BLOCK_K_256_BYTE,
491- BASIC_BLOCK_K_256_BYTE,
492- BASIC_BLOCK_K_128_BYTE / args_.aDtypeSize};
493- if (CalcBestBalance(params2, isMLarger)) {
494- return;
495- }
496- 
497- runInfo_.baseM = params1.baseM;
498- runInfo_.baseN = params1.baseN;
499- runInfo_.baseK = params1.baseK;
500- if (params1.bestBalance < params2.bestBalance) {
501- runInfo_.baseM = params2.baseM;
502- runInfo_.baseN = params2.baseN;
503- runInfo_.baseK = params2.baseK;
504- }
505-}
506- 
507-ge::graphStatus MatMulV3AswTiling::DoNormOpTiling()
508-{
509- MatMulV3TilingHelper::ResetBase(compileInfo_, args_, runInfo_);
510- FormulateBasicBlock();
511- OptimizeEdgeBasicBlock();
512- CalcTailBasicBlock();
513- MatMulV3TilingHelper::CalL1Tiling(compileInfo_, args_, runInfo_);
514- return ge::GRAPH_SUCCESS;
515-}
516- 
517ge::graphStatus MatMulV3AswTiling::DoOpTiling()50ge::graphStatus MatMulV3AswTiling::DoOpTiling()
518{51{
519 MatMulV3TilingHelper::ResetBase(compileInfo_, args_, runInfo_);52 MatMulV3TilingHelper::ResetBase(compileInfo_, args_, runInfo_);
520- FormulateLoadBalanceBlock();53+ MatMulV3TilingHelper::GetRebalanceBlock(compileInfo_, args_, runInfo_, context_);
521- if (runInfo_.baseM == BASIC_BLOCK_SIZE_256 && runInfo_.baseN == BASIC_BLOCK_SIZE_256) {
522- OptimizeEdgeBasicBlock();
523- }
524 CalcTailBasicBlock();54 CalcTailBasicBlock();
525 MatMulV3TilingHelper::CalL1Tiling(compileInfo_, args_, runInfo_);55 MatMulV3TilingHelper::CalL1Tiling(compileInfo_, args_, runInfo_);
526 return ge::GRAPH_SUCCESS;56 return ge::GRAPH_SUCCESS;
@@ -541,4 +71,4 @@ ge::graphStatus MatMulV3AswTiling::GetTilingData(TilingResult& tiling) const
541 return GetTilingDataImpl<MatMulV3TilingData>(tiling);71 return GetTilingDataImpl<MatMulV3TilingData>(tiling);
542}72}
543} // namespace matmul_v3_advanced73} // namespace matmul_v3_advanced
544-} // namespace optiling74+} // namespace optiling
Mmatmul/mat_mul_v3/op_host/op_tiling/arch35/matmul_v3_asw_tiling.h+0-27
@@ -32,38 +32,11 @@ protected:
32 32 
33 ge::graphStatus DoOpTiling() override;33 ge::graphStatus DoOpTiling() override;
34 34 
35- ge::graphStatus DoNormOpTiling();
36- 
37 uint64_t GetTilingKey() const override;35 uint64_t GetTilingKey() const override;
38 36 
39 ge::graphStatus GetTilingData(TilingResult &tiling) const override;37 ge::graphStatus GetTilingData(TilingResult &tiling) const override;
40-private:
41- struct CalcParams {
42- uint64_t baseStart;
43- uint64_t baseEnd;
44- bool isNegativeSign;
45- double bestBalance;
46- uint64_t baseM;
47- uint64_t baseN;
48- uint64_t baseK;
49- };
50 38 
51- void CalcBasicBlock();
52- void FormulateBasicBlock();
53- void FormulateLoadBalanceBlock();
54 void CalcTailBasicBlock();39 void CalcTailBasicBlock();
55- void OptimizeEdgeBasicBlock();
56- void GetOuterAxisTailCnt(bool nLoadBalance, uint64_t& baseTailSplitCnt, uint64_t& tailMain);
57- void CalcSingleX(uint64_t& higherSingleX, uint64_t& lowerSingleX);
58- // 单边大场景处理
59- uint64_t UpdateBaseBlock(uint64_t baseBlock, bool isMLarger);
60- void CalcLargeSingleSide(uint64_t minMN, uint64_t maxMN, uint64_t& targetBase, bool isMLarger);
61- void HandleLargeSingleSide(uint64_t minMN, uint64_t maxMN, bool isMLarger);
62- // 两边都比较大场景处理
63- bool UpdateBothBaseBlock(
64- double balance, CalcParams& params, uint64_t currentBaseM, uint64_t currentBaseN, uint64_t baseK);
65- bool CalcBestBalance(CalcParams& params, bool isMLarger);
66- void HandleLargeBothSides(uint64_t higherSingleX, uint64_t lowerSingleX, uint64_t minMN, bool isMLarger);
67};40};
68} // namespace matmul_v3_advanced41} // namespace matmul_v3_advanced
69} // namespace optiling42} // namespace optiling
Mmatmul/mat_mul_v3/op_host/op_tiling/arch35/matmul_v3_basic_aswt_tiling.cpp+199-204文件内容审核中，请稍后刷新重试
Mmatmul/mat_mul_v3/op_host/op_tiling/arch35/matmul_v3_basic_aswt_tiling.h+4-13
@@ -25,10 +25,6 @@ public:
25 MatMulV3BasicAswtTiling(gert::TilingContext *context, MatMulTilingCfg &cfg)25 MatMulV3BasicAswtTiling(gert::TilingContext *context, MatMulTilingCfg &cfg)
26 : MatMulV3AswTiling(context, cfg) {};26 : MatMulV3AswTiling(context, cfg) {};
27 ~MatMulV3BasicAswtTiling() override = default;27 ~MatMulV3BasicAswtTiling() override = default;
28- bool CheckBL1FullLoadDav3510(const uint64_t kAlignedValue, const uint64_t nAlignedValue) const;
29- bool CheckAL1FullLoadDav3510(const uint64_t kAlignedValue, const uint64_t mAlignedValue) const;
30- void AdjustBL1Tiling3510Basic(uint64_t biasBatchDimAll);
31- void AdjustAL1Tiling3510Basic(uint64_t biasBatchDimAll);
32 void CheckTensorApiSupport();28 void CheckTensorApiSupport();
33 29 
34protected:30protected:
@@ -36,24 +32,19 @@ protected:
36 ge::graphStatus DoOpTiling() override;32 ge::graphStatus DoOpTiling() override;
37 uint64_t GetTilingKey() const override;33 uint64_t GetTilingKey() const override;
38 ge::graphStatus GetTilingData(TilingResult& tiling) const override;34 ge::graphStatus GetTilingData(TilingResult& tiling) const override;
39- void DoBL1FullLoad(uint64_t aBatchDimAll = 1UL, uint64_t biasBatchDimAll = 1UL);35+ void DoBL1FullLoad();
40- void DoAL1FullLoad(uint64_t bBatchDimAll = 1UL, uint64_t biasBatchDimAll = 1UL);36+ void DoAL1FullLoad();
41 MatMulV3FullLoad fullLoad_ {MatMulV3FullLoad::NONE_FULL_LOAD};37 MatMulV3FullLoad fullLoad_ {MatMulV3FullLoad::NONE_FULL_LOAD};
42 MatMulV3L0C2Out l0C2Out_ {MatMulV3L0C2Out::ON_THE_FLY};38 MatMulV3L0C2Out l0C2Out_ {MatMulV3L0C2Out::ON_THE_FLY};
43 MatMulV3ApiLevel apiLevel_ {MatMulV3ApiLevel::BASIC_LEVEL};39 MatMulV3ApiLevel apiLevel_ {MatMulV3ApiLevel::BASIC_LEVEL};
44 40 
45private:41private:
46- void FullLoadPre();42+ void ResetFullLoadLoadBalance();
47- uint64_t GetAFullLoadBasicNL1() const;43+ 
48 void CalcTailBasicBlockBL1Full();44 void CalcTailBasicBlockBL1Full();
49 void CalcTailBasicBlockAL1Full();45 void CalcTailBasicBlockAL1Full();
50 bool CheckBL1FullLoad() const;46 bool CheckBL1FullLoad() const;
51 bool CheckAL1FullLoad() const;47 bool CheckAL1FullLoad() const;
52- 
53- uint64_t biasSize_ {0};
54- bool isSingleRound_ {false};
55- bool isAFullLoad_ {false};
56- bool isBFullLoad_ {false};
57};48};
58} // namespace matmul_v349} // namespace matmul_v3
59} // namespace optiling50} // namespace optiling
Mmatmul/mat_mul_v3/op_host/op_tiling/arch35/matmul_v3_tiling_helper.cpp+69-154
@@ -25,43 +25,38 @@ using namespace optiling::matmul_v3_advanced;
25using StrideIndexPairs = std::vector<std::pair<int64_t, std::pair<int64_t, int64_t>>>;25using StrideIndexPairs = std::vector<std::pair<int64_t, std::pair<int64_t, int64_t>>>;
26 26 
27// ------------------------------ CalL1Tiling -------------------------------------------//27// ------------------------------ CalL1Tiling -------------------------------------------//
28-void CalL1TilingDefault(const MatmulV3CompileInfo &compileInfo, const MatMulV3Args &args, MatMulV3RunInfo &runInfo)28+void CalL1TilingDefault(const MatmulV3CompileInfo& compileInfo, const MatMulV3Args& args, MatMulV3RunInfo& runInfo)
29{29{
30- uint64_t totalL1Size = compileInfo.l1Size;30+ bool isKInner = !args.isATrans || args.isBTrans;
31- if (args.hasScale) {31+ uint64_t totalL1Size = compileInfo.l1Size - (args.hasBias ? runInfo.baseN * DB_SIZE * DATA_SIZE_FP32 : 0UL);
32- totalL1Size -= runInfo.baseN * sizeof(uint64_t);32+ totalL1Size -= args.hasScale ? runInfo.baseN * sizeof(uint64_t) : 0UL;
33- }33+ // Shape约束 && issue queue约束
34- uint64_t reserveBTSize = args.hasBias ? BIAS_TABLE_NUM * DATA_SIZE_FP32 : 0UL;34+ uint64_t maxStepK = std::min(MathUtil::CeilDivision(args.kValue, runInfo.baseK), 8UL);
35- runInfo.depthA1 = totalL1Size / NUM_TWO / runInfo.baseM / runInfo.baseK / args.aDtypeSize; // 2: half of l135+ uint64_t kAlignUnit = isKInner ? BASIC_BLOCK_K_512_BYTE / args.aDtypeSize : BASIC_BLOCK_SIZE_16;
36- runInfo.depthB1 = totalL1Size / NUM_TWO / runInfo.baseN / runInfo.baseK / args.bDtypeSize; // 2: half of l136+ uint64_t resKL1 = 0;
37- 37+ uint64_t singleMteSize = 0;
38- uint64_t depthASize = runInfo.depthA1 * runInfo.baseM * runInfo.baseK * args.aDtypeSize;38+ for (uint64_t stepK = 1; stepK <= maxStepK; stepK++) {
39- uint64_t depthBSize = runInfo.depthB1 * runInfo.baseN * runInfo.baseK * args.bDtypeSize;39+ uint64_t curKL1 = runInfo.baseK * stepK;
40- if (depthASize + depthBSize > totalL1Size - reserveBTSize) {40+ uint64_t aL1Size = runInfo.baseM * curKL1 * args.aDtypeSize;
41- if (runInfo.baseM <= runInfo.baseN) {41+ uint64_t bL1Size = runInfo.baseN * curKL1 * args.bDtypeSize;
42- runInfo.depthA1 = std::max(runInfo.depthA1 / NUM_TWO, 1UL); // 2: adjust deptch for l1 buffer42+ if ((aL1Size + bL1Size) * DB_SIZE > totalL1Size ||
43- } else {43+ std::max(aL1Size, bL1Size) * DB_SIZE * 2 > compileInfo.l1Size) {
44- runInfo.depthB1 = std::max(runInfo.depthB1 / NUM_TWO, 1UL); // 2: adjust deptch for l1 buffer44+ break;
45+ }
46+ bool condNoRes = resKL1 == 0;
47+ bool condKAlign256B = curKL1 % (BASIC_BLOCK_K_256_BYTE / args.aDtypeSize) == 0;
48+ bool condKAlign =
49+ resKL1 % kAlignUnit != 0 && (condKAlign256B || (!condKAlign256B && singleMteSize < L1_SINGLE_SIZE_LIMIT));
50+ bool condMteSize = resKL1 % kAlignUnit == 0 && curKL1 % kAlignUnit == 0 && singleMteSize < L1_SINGLE_SIZE_LIMIT;
51+ if (condNoRes || condKAlign || condMteSize) {
52+ resKL1 = curKL1;
53+ singleMteSize = std::max(aL1Size, bL1Size);
45 }54 }
46 }55 }
47- runInfo.stepKa = std::max(runInfo.depthA1 / DB_SIZE, 1UL);56+ runInfo.stepKa = resKL1 / runInfo.baseK;
48- runInfo.stepKb = std::max(runInfo.depthB1 / DB_SIZE, 1UL);57+ runInfo.stepKb = resKL1 / runInfo.baseK;
49- // 对齐且基本块为[256, 256]则stepK改为258+ runInfo.depthA1 = runInfo.stepKa * DB_SIZE;
50- if (runInfo.baseM == BASIC_BLOCK_SIZE_256 && runInfo.baseN == BASIC_BLOCK_SIZE_256 &&59+ runInfo.depthB1 = runInfo.stepKb * DB_SIZE;
51- args.mValue % BASIC_BLOCK_SIZE_16 == 0 && args.nValue % BASIC_BLOCK_SIZE_16 == 0 &&
52- args.kValue % BASIC_BLOCK_SIZE_16 == 0 && runInfo.singleCoreK <= BASIC_BLOCK_SIZE_256) {
53- runInfo.stepKa = std::min(runInfo.stepKa, 2UL);
54- runInfo.stepKb = std::min(runInfo.stepKb, 2UL);
55- }
56- // 调整stepKa和stepKb为整数倍关系
57- if (runInfo.stepKa >= runInfo.stepKb) {
58- runInfo.stepKa = runInfo.stepKa / runInfo.stepKb * runInfo.stepKb;
59- } else {
60- runInfo.stepKb = runInfo.stepKb / runInfo.stepKa * runInfo.stepKa;
61- }
62- // 默认开启double buffer
63- runInfo.depthA1 = runInfo.stepKa * DB_SIZE; // depth % (stepKa * stepM) == 0
64- runInfo.depthB1 = runInfo.stepKb * DB_SIZE; // depth % (stepKb * stepN) == 0
65 runInfo.singleCoreM = runInfo.baseM;60 runInfo.singleCoreM = runInfo.baseM;
66 runInfo.singleCoreN = runInfo.baseN;61 runInfo.singleCoreN = runInfo.baseN;
67 return;62 return;
@@ -156,7 +151,7 @@ MatMulV3L0C2Out GetL0C2OutDav3510(const MatmulV3CompileInfo &compileInfo, const
156 uint64_t mCnt = MathUtil::CeilDivision(args.mValue, runInfo.singleCoreM);151 uint64_t mCnt = MathUtil::CeilDivision(args.mValue, runInfo.singleCoreM);
157 uint64_t nCnt = MathUtil::CeilDivision(args.nValue, runInfo.singleCoreN);152 uint64_t nCnt = MathUtil::CeilDivision(args.nValue, runInfo.singleCoreN);
158 // make sure the fixpipe stream is large enough to be bound153 // make sure the fixpipe stream is large enough to be bound
159- bool isMultiRound = mCnt * nCnt >= NUM_TWO * compileInfo.aicNum;154+ bool isMultiRound = mCnt * nCnt > compileInfo.aicNum;
160 uint64_t cDtypeSize = ge::GetSizeByDataType(args.cType);155 uint64_t cDtypeSize = ge::GetSizeByDataType(args.cType);
161 // 128: SMALL_SHAPE_LOWER_THRES156 // 128: SMALL_SHAPE_LOWER_THRES
162 bool isUnalignedN = args.nValue * cDtypeSize % 128UL != 0 && args.nValue * cDtypeSize > BASIC_BLOCK_SIZE_256;157 bool isUnalignedN = args.nValue * cDtypeSize % 128UL != 0 && args.nValue * cDtypeSize > BASIC_BLOCK_SIZE_256;
@@ -176,48 +171,7 @@ const static std::map<NpuArch, GetL0C2OutFunc> GetL0C2OutFuncMap = {
176 {NpuArch::DAV_3510, GetL0C2OutDav3510},171 {NpuArch::DAV_3510, GetL0C2OutDav3510},
177};172};
178 173 
179- 174+uint64_t GetMaxBaseWithLimit(
180-// ------------------------------ GetStepSmallK -------------------------------------------//
181-uint64_t GetStepSmallKDefault(const MatMulV3Args& /* args */, const MatMulV3RunInfo& runInfo, bool isBL1FullLoad)
182-{
183- return isBL1FullLoad ? runInfo.stepKa : runInfo.stepKb;
184-}
185- 
186-uint64_t GetStepSmallKDav3510(const MatMulV3Args& args, const MatMulV3RunInfo& runInfo, bool isBL1FullLoad)
187-{
188- uint64_t stepBigK = runInfo.stepKa;
189- uint64_t stepSmallK = runInfo.stepKb;
190- uint64_t dtypeSize = args.aDtypeSize;
191- ge::DataType inputType = args.aType;
192- bool isTrans = args.isBTrans;
193- if (isBL1FullLoad) {
194- stepBigK = runInfo.stepKb;
195- stepSmallK = runInfo.stepKa;
196- dtypeSize = args.bDtypeSize;
197- inputType = args.bType;
198- isTrans = args.isATrans;
199- }
200- 
201- static const double SMALL_TAIL = 0.25;
202- bool isSmallTail = static_cast<double>(stepBigK % stepSmallK) / stepSmallK <= SMALL_TAIL;
203- isSmallTail = (isSmallTail && !isTrans) || runInfo.baseK * dtypeSize >= BASIC_BLOCK_SIZE_256;
204- // A/B全载场景，stepK big为全载矩阵的stepK, 调整stepK small为2, 减少mte2耗时, 提高搬运带宽
205- if ((inputType == ge::DT_FLOAT && !args.isHf32)) {
206- stepSmallK = 1UL;
207- } else if (isSmallTail) {
208- stepSmallK = 2UL;
209- }
210- return stepSmallK;
211-}
212- 
213-using GetStepSmallKFunc = uint64_t (*)(const MatMulV3Args&, const MatMulV3RunInfo&, bool);
214- 
215-// 全载模板修改stepK
216-const static std::map<NpuArch, GetStepSmallKFunc> GetStepSmallKFuncMap = {
217- {NpuArch::DAV_3510, GetStepSmallKDav3510},
218-};
219- 
220-static uint64_t GetMaxBaseWithLimit(
221 const MatmulV3CompileInfo& compileInfo, const MatMulV3Args& args,175 const MatmulV3CompileInfo& compileInfo, const MatMulV3Args& args,
222 uint64_t baseMNBufferLimit, uint64_t baseAlignUnit, bool isRightMatrix, bool isMemoryBound)176 uint64_t baseMNBufferLimit, uint64_t baseAlignUnit, bool isRightMatrix, bool isMemoryBound)
223{177{
@@ -245,6 +199,9 @@ static uint64_t GetMaxBaseWithLimit(
245 // 输入shape约束199 // 输入shape约束
246 maxBaseBlock =200 maxBaseBlock =
247 std::min(ops::CeilAlign(shapeValue, baseAlignUnit), ops::FloorAlign(maxBaseBlock, baseAlignUnit));201 std::min(ops::CeilAlign(shapeValue, baseAlignUnit), ops::FloorAlign(maxBaseBlock, baseAlignUnit));
202+ if (shapeValue < baseAlignUnit) {
203+ maxBaseBlock = std::min(maxBaseBlock, ops::CeilAlign(shapeValue, BASIC_BLOCK_SIZE_16));
204+ }
248 return maxBaseBlock;205 return maxBaseBlock;
249}206}
250 207 
@@ -291,6 +248,20 @@ static void GetBaseK(const MatmulV3CompileInfo& compileInfo, const MatMulV3Args&
291 }248 }
292 }249 }
293}250}
251+ 
252+bool PreCheckFullLoad(const MatmulV3CompileInfo& compileInfo, const MatMulV3Args& args,
253+ const MatMulV3RunInfo& runInfo)
254+{
255+ uint64_t mAlignedValue = ops::CeilAlign(args.mValue, BASIC_BLOCK_SIZE_16);
256+ uint64_t nAlignedValue = ops::CeilAlign(args.nValue, BASIC_BLOCK_SIZE_16);
257+ uint64_t kAlignedValue = ops::CeilAlign(args.kValue, BASIC_BLOCK_SIZE_16);
258+ uint64_t al1Size = mAlignedValue * kAlignedValue * args.aDtypeSize;
259+ uint64_t bl1Size = nAlignedValue * kAlignedValue * args.bDtypeSize;
260+ uint64_t biasSize = args.hasBias ? runInfo.baseN * DB_SIZE * GetSizeByDataType(args.biasType) : 0;
261+ // 全载数据不超过3/4 L1 Buffer
262+ return al1Size + biasSize <= compileInfo.l1Size * 3UL / 4UL ||
263+ bl1Size + biasSize <= compileInfo.l1Size * 3UL / 4UL;
264+}
294} // namespace265} // namespace
295 266 
296namespace optiling {267namespace optiling {
@@ -322,62 +293,6 @@ MatMulV3L0C2Out MatMulV3TilingHelper::GetL0C2Out(const MatmulV3CompileInfo &comp
322 return iter(compileInfo, args, runInfo);293 return iter(compileInfo, args, runInfo);
323}294}
324 295 
325-uint64_t MatMulV3TilingHelper::GetStepSmallK(
326- bool isBL1FullLoad, const MatmulV3CompileInfo& compileInfo, const MatMulV3Args& args, MatMulV3RunInfo& runInfo)
327-{
328- auto iter = (GetStepSmallKFuncMap.find(compileInfo.npuArch) == GetStepSmallKFuncMap.end()) ?
329- GetStepSmallKDefault :
330- GetStepSmallKFuncMap.at(compileInfo.npuArch);
331- return iter(args, runInfo, isBL1FullLoad);
332-}
333- 
334-void MatMulV3TilingHelper::AdjustBL1TilingCommon(
335- uint64_t aBatchDimAll, const MatmulV3CompileInfo& compileInfo, const MatMulV3Args& args, MatMulV3RunInfo& runInfo)
336-{
337- // fine tune tiling basen
338- uint64_t nAlignedValue = ops::CeilAlign(args.nValue, BASIC_BLOCK_SIZE_16);
339- uint64_t bl0Size = nAlignedValue * runInfo.baseK * args.bDtypeSize * DB_SIZE;
340- runInfo.baseN = bl0Size <= compileInfo.l0BSize ? nAlignedValue : std::min(nAlignedValue, runInfo.baseN);
341- runInfo.stepN = MathUtil::CeilDivision(args.nValue, runInfo.baseN);
342- runInfo.stepKb = MathUtil::CeilDivision(args.kValue, runInfo.baseK);
343- // fine tune stepK for fullload
344- runInfo.stepKa = GetStepSmallK(true, compileInfo, args, runInfo);
345- // take full use of cores
346- if (aBatchDimAll * MathUtil::CeilDivision(args.mValue, runInfo.baseM) < compileInfo.aicNum) {
347- runInfo.baseM =
348- ops::CeilAlign(MathUtil::CeilDivision(aBatchDimAll * args.mValue, compileInfo.aicNum), BASIC_BLOCK_SIZE_16);
349- }
350- runInfo.depthA1 = DB_SIZE * runInfo.stepKa;
351- runInfo.depthB1 = runInfo.stepN * runInfo.stepKb;
352-}
353- 
354-void MatMulV3TilingHelper::AdjustAL1TilingCommon(
355- uint64_t bBatchDimAll, const MatmulV3CompileInfo& compileInfo, const MatMulV3Args& args, MatMulV3RunInfo& runInfo)
356-{
357- uint64_t mAlignedValue = ops::CeilAlign(args.mValue, BASIC_BLOCK_SIZE_16);
358- uint64_t al0Size = mAlignedValue * runInfo.baseK * args.aDtypeSize * DB_SIZE;
359- runInfo.baseM = al0Size <= compileInfo.l0ASize ? mAlignedValue : std::min(mAlignedValue, runInfo.baseM);
360- runInfo.stepM = MathUtil::CeilDivision(args.mValue, runInfo.baseM);
361- runInfo.stepKa = MathUtil::CeilDivision(args.kValue, runInfo.baseK);
362- runInfo.stepKb = GetStepSmallK(false, compileInfo, args, runInfo);
363- // take full use of cores
364- if (bBatchDimAll * MathUtil::CeilDivision(args.nValue, runInfo.baseN) < compileInfo.aicNum) {
365- runInfo.baseN =
366- ops::CeilAlign(MathUtil::CeilDivision(bBatchDimAll * args.nValue, compileInfo.aicNum), BASIC_BLOCK_SIZE_16);
367- }
368- runInfo.depthB1 = DB_SIZE * runInfo.stepKb;
369- runInfo.depthA1 = runInfo.stepM * runInfo.stepKa;
370-}
371- 
372-void MatMulV3TilingHelper::ResetFullLoadLoadBalance(MatMulV3RunInfo& runInfo)
373-{
374- // 全载模板需重置负载均衡计算
375- runInfo.mBaseTailSplitCnt = 1UL;
376- runInfo.nBaseTailSplitCnt = 1UL;
377- runInfo.tailInfo.mTailMain = 0UL;
378- runInfo.tailInfo.nTailMain = 0UL;
379-}
380- 
381bool MatMulV3TilingHelper::IsSelfNonContiguous(const gert::TilingContext* context)296bool MatMulV3TilingHelper::IsSelfNonContiguous(const gert::TilingContext* context)
382{297{
383 auto selfShape = context->GetInputShape(0)->GetOriginShape();298 auto selfShape = context->GetInputShape(0)->GetOriginShape();
@@ -454,28 +369,24 @@ void MatMulV3TilingHelper::GetRebalanceBlock(const MatmulV3CompileInfo& compileI
454 double hbmBW = GetHbmBW(platformInfo);369 double hbmBW = GetHbmBW(platformInfo);
455 double l2BW = GetL2BW(platformInfo);370 double l2BW = GetL2BW(platformInfo);
456 double singleCoreComputePower = GetCoreFreq(platformInfo) * NUM_EIGHT;371 double singleCoreComputePower = GetCoreFreq(platformInfo) * NUM_EIGHT;
457- // balanceRateEdge用于判断是否取得最优解，进行减枝372+ // balanceRateEdge用于判断是否取得最优解，进行减枝, 默认0.9
458 double balanceRateEdge = 0.9;373 double balanceRateEdge = 0.9;
459 double cmr = (static_cast<double>(args.mValue) + args.nValue) / (static_cast<double>(args.mValue) * args.nValue);374 double cmr = (static_cast<double>(args.mValue) + args.nValue) / (static_cast<double>(args.mValue) * args.nValue);
460 double computePower = singleCoreComputePower * compileInfo.aicNum;375 double computePower = singleCoreComputePower * compileInfo.aicNum;
461 376 
462 // 切K场景，要求输出size同时小于L0C和UB377 // 切K场景，要求输出size同时小于L0C和UB
463- uint64_t baseMNBufferLimit = runInfo.usedCoreNum == compileInfo.aicNum ?378+ uint64_t baseMNBufferLimit = runInfo.usedCoreNum == compileInfo.aicNum ? compileInfo.l0CSize :
464- compileInfo.l0CSize :379+ std::min(compileInfo.l0CSize, compileInfo.ubSize);
465- std::min(compileInfo.l0CSize, compileInfo.ubSize);
466 380 
467 uint64_t batchNum = args.batchInfo == nullptr ? 1 : args.batchInfo->batchA;381 uint64_t batchNum = args.batchInfo == nullptr ? 1 : args.batchInfo->batchA;
468 double l2CacheUsage =382 double l2CacheUsage =
469 std::max(static_cast<double>(batchNum * (args.mValue + args.nValue) * args.kValue * args.aDtypeSize) /383 std::max(static_cast<double>(batchNum * (args.mValue + args.nValue) * args.kValue * args.aDtypeSize) /
470- compileInfo.l2Size,384+ compileInfo.l2Size, 1.0);
471- 1.0);
472 runInfo.cubeBoundEdge =385 runInfo.cubeBoundEdge =
473 (l2BW / computePower) + l2CacheUsage * (1 - l2BW / hbmBW) * cmr - (1 + l2BW / hbmBW) / args.kValue;386 (l2BW / computePower) + l2CacheUsage * (1 - l2BW / hbmBW) * cmr - (1 + l2BW / hbmBW) / args.kValue;
474 uint64_t baseMBest = std::min(ops::CeilAlign(args.mValue, BASIC_BLOCK_SIZE_16), BASIC_BLOCK_SIZE_256);387 uint64_t baseMBest = std::min(ops::CeilAlign(args.mValue, BASIC_BLOCK_SIZE_16), BASIC_BLOCK_SIZE_256);
475- uint64_t baseNBest =388+ uint64_t baseNBest = std::max(BASIC_BLOCK_SIZE_16, std::min(ops::CeilAlign(args.nValue, BASIC_BLOCK_SIZE_16),
476- std::max(BASIC_BLOCK_SIZE_16,389+ ops::FloorAlign(baseMNBufferLimit / DATA_SIZE_FP32 / baseMBest, BASIC_BLOCK_SIZE_16)));
477- std::min(ops::CeilAlign(args.nValue, BASIC_BLOCK_SIZE_16),
478- ops::FloorAlign(baseMNBufferLimit / DATA_SIZE_FP32 / baseMBest, BASIC_BLOCK_SIZE_16)));
479 double cubeBoundParamBest = (1.0 / baseMBest) + (1.0 / baseNBest);390 double cubeBoundParamBest = (1.0 / baseMBest) + (1.0 / baseNBest);
480 bool isMemoryBound = cubeBoundParamBest > runInfo.cubeBoundEdge;391 bool isMemoryBound = cubeBoundParamBest > runInfo.cubeBoundEdge;
481 uint64_t innerAlignUnit = isMemoryBound ? BASIC_BLOCK_SIZE_128 : BASIC_BLOCK_SIZE_64;392 uint64_t innerAlignUnit = isMemoryBound ? BASIC_BLOCK_SIZE_128 : BASIC_BLOCK_SIZE_64;
@@ -484,8 +395,8 @@ void MatMulV3TilingHelper::GetRebalanceBlock(const MatmulV3CompileInfo& compileI
484 double fixpBoundEdge = (args.mValue * args.nValue * hbmBW) / ((args.mValue + args.nValue) * l2BW);395 double fixpBoundEdge = (args.mValue * args.nValue * hbmBW) / ((args.mValue + args.nValue) * l2BW);
485 uint64_t baseMAlignUnit = args.isATrans ? innerAlignUnit / args.aDtypeSize : BASIC_BLOCK_SIZE_16;396 uint64_t baseMAlignUnit = args.isATrans ? innerAlignUnit / args.aDtypeSize : BASIC_BLOCK_SIZE_16;
486 uint64_t baseNAlignUnit = (static_cast<double>(args.kValue) < fixpBoundEdge) ?397 uint64_t baseNAlignUnit = (static_cast<double>(args.kValue) < fixpBoundEdge) ?
487- (BASIC_BLOCK_K_256_BYTE / args.bDtypeSize) :398+ (BASIC_BLOCK_K_256_BYTE / args.bDtypeSize) :
488- (args.isBTrans ? BASIC_BLOCK_SIZE_16 : innerAlignUnit / args.bDtypeSize);399+ (args.isBTrans ? BASIC_BLOCK_SIZE_16 : innerAlignUnit / args.bDtypeSize);
489 400 
490 // 计算候选解集的上界401 // 计算候选解集的上界
491 uint64_t maxBaseM =402 uint64_t maxBaseM =
@@ -494,31 +405,35 @@ void MatMulV3TilingHelper::GetRebalanceBlock(const MatmulV3CompileInfo& compileI
494 GetMaxBaseWithLimit(compileInfo, args, baseMNBufferLimit, baseNAlignUnit, true, isMemoryBound);405 GetMaxBaseWithLimit(compileInfo, args, baseMNBufferLimit, baseNAlignUnit, true, isMemoryBound);
495 406 
496 runInfo.baseM = std::max(BASIC_BLOCK_SIZE_16, std::min(maxBaseM, BASIC_BLOCK_SIZE_256));407 runInfo.baseM = std::max(BASIC_BLOCK_SIZE_16, std::min(maxBaseM, BASIC_BLOCK_SIZE_256));
497- runInfo.baseN = std::max(408+ runInfo.baseN = std::max(BASIC_BLOCK_SIZE_16,
498- BASIC_BLOCK_SIZE_16,
499 std::min(maxBaseN, ops::FloorAlign(baseMNBufferLimit / DATA_SIZE_FP32 / runInfo.baseM, baseNAlignUnit)));409 std::min(maxBaseN, ops::FloorAlign(baseMNBufferLimit / DATA_SIZE_FP32 / runInfo.baseM, baseNAlignUnit)));
500 runInfo.cubeBoundParam = (1.0 / runInfo.baseM) + (1.0 / runInfo.baseN);410 runInfo.cubeBoundParam = (1.0 / runInfo.baseM) + (1.0 / runInfo.baseN);
501 runInfo.cubeBoundEdge = runInfo.cubeBoundEdge * CUBE_BOUND_RATIO;411 runInfo.cubeBoundEdge = runInfo.cubeBoundEdge * CUBE_BOUND_RATIO;
502 double balanceRate = GetBalanceRateWithTail(args, runInfo.usedCoreNum, runInfo.baseM, runInfo.baseN);412 double balanceRate = GetBalanceRateWithTail(args, runInfo.usedCoreNum, runInfo.baseM, runInfo.baseN);
503 413 
504 for (uint64_t curBaseM = maxBaseM; curBaseM >= 1 && curBaseM <= maxBaseM; curBaseM -= baseMAlignUnit) {414 for (uint64_t curBaseM = maxBaseM; curBaseM >= 1 && curBaseM <= maxBaseM; curBaseM -= baseMAlignUnit) {
505- uint64_t curMaxBaseN =415+ uint64_t curMaxBaseN = std::min(maxBaseN, ops::FloorAlign(baseMNBufferLimit / DATA_SIZE_FP32 / curBaseM /
506- std::min(maxBaseN, ops::FloorAlign(baseMNBufferLimit / DATA_SIZE_FP32 / curBaseM, baseNAlignUnit));416+ (PreCheckFullLoad(compileInfo, args, runInfo) ? DB_OFF_SIZE : 1), baseNAlignUnit));
L
Lliutao2497月16日

DB_OFF_SIZE的定义是否为1，如果是，三元表达式无效

likedislike
507 for (uint64_t curBaseN = curMaxBaseN; curBaseN >= 1 && curBaseN <= curMaxBaseN; curBaseN -= baseNAlignUnit) {417 for (uint64_t curBaseN = curMaxBaseN; curBaseN >= 1 && curBaseN <= curMaxBaseN; curBaseN -= baseNAlignUnit) {
508 double curCubeBoundParam = (1.0 / curBaseM) + (1.0 / curBaseN);418 double curCubeBoundParam = (1.0 / curBaseM) + (1.0 / curBaseN);
509 double curBalanceRate = GetBalanceRateWithTail(args, runInfo.usedCoreNum, curBaseM, curBaseN);419 double curBalanceRate = GetBalanceRateWithTail(args, runInfo.usedCoreNum, curBaseM, curBaseN);
510 // 当前最优解满足负载均衡阈值时，本轮解集无法在计算访存拿到收益时过滤本轮解集420 // 当前最优解满足负载均衡阈值时，本轮解集无法在计算访存拿到收益时过滤本轮解集
511- if (balanceRate >= balanceRateEdge && curCubeBoundParam > runInfo.cubeBoundParam &&421+ bool skipCond = balanceRate >= balanceRateEdge && curCubeBoundParam > runInfo.cubeBoundParam &&
512- curCubeBoundParam > runInfo.cubeBoundEdge) {422+ curCubeBoundParam > runInfo.cubeBoundEdge && runInfo.cubeBoundEdge > 0;
423+ if (skipCond) {
513 continue;424 continue;
514 }425 }
515 // 当前解满足cubebound并且负载均衡率更高426 // 当前解满足cubebound并且负载均衡率更高
516 bool cubeBoundCond = curCubeBoundParam <= runInfo.cubeBoundEdge && curBalanceRate > balanceRate;427 bool cubeBoundCond = curCubeBoundParam <= runInfo.cubeBoundEdge && curBalanceRate > balanceRate;
517 // 综合评选负载均衡和计算访存能力428 // 综合评选负载均衡和计算访存能力
518 bool balanceCond = ((curCubeBoundParam / curBalanceRate) < (runInfo.cubeBoundParam / balanceRate)) ||429 bool balanceCond = ((curCubeBoundParam / curBalanceRate) < (runInfo.cubeBoundParam / balanceRate)) ||
519- ((std::abs(curCubeBoundParam / curBalanceRate - runInfo.cubeBoundParam / balanceRate) < EPSILON) &&430+ ((std::abs(curCubeBoundParam / curBalanceRate - runInfo.cubeBoundParam / balanceRate) <
520- curBalanceRate > balanceRate);431+ EPSILON) && curBalanceRate > balanceRate);
521- if (cubeBoundCond || balanceCond) {432+ bool updateCond = cubeBoundCond || balanceCond;
433+ if (updateCond) {
434+ if (cubeBoundCond) {
435+ runInfo.cubeBoundEdge = curCubeBoundParam;
436+ }
522 runInfo.baseM = curBaseM;437 runInfo.baseM = curBaseM;
523 runInfo.baseN = curBaseN;438 runInfo.baseN = curBaseN;
524 runInfo.cubeBoundParam = curCubeBoundParam;439 runInfo.cubeBoundParam = curCubeBoundParam;
Mmatmul/mat_mul_v3/tests/ut/op_host/test_matmul_v3_tiling.cpp+29-29
@@ -853,7 +853,7 @@ static TilingTestParam ascend950_cases_params[] = {
853 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },853 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
854 "format_a":"ND","format_b":"FRACTAL_NZ","repo_range":{},"repo_seeds":{}})",854 "format_a":"ND","format_b":"FRACTAL_NZ","repo_range":{},"repo_seeds":{}})",
855 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_FRACTAL_NZ, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {89, 11665}, {3, 6, 16, 16}, {11665, 47}, {89, 11665}, {89, 47}, {11665, 47}, false, 0, 0, 32, 131089UL,855 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_FRACTAL_NZ, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {89, 11665}, {3, 6, 16, 16}, {11665, 47}, {89, 11665}, {89, 47}, {11665, 47}, false, 0, 0, 32, 131089UL,
856- "32 11665 47 89 256 48 128 256 48 64 89 2 1 1 1 0 0 33686016 0 256 1 0 "856+ "32 11665 47 89 320 48 96 320 48 48 89 5 1 1 1 0 0 33686528 0 320 1 0 "
857 },857 },
858 {858 {
859 "MatMulV3_950_basic_testNZ_aFullLoad", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":true,"transpose_b":true, "offset_x":0, "opImplMode":0},859 "MatMulV3_950_basic_testNZ_aFullLoad", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":true,"transpose_b":true, "offset_x":0, "opImplMode":0},
@@ -861,8 +861,8 @@ static TilingTestParam ascend950_cases_params[] = {
861 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,861 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,
862 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },862 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
863 "format_a":"ND","format_b":"FRACTAL_NZ","repo_range":{},"repo_seeds":{}})",863 "format_a":"ND","format_b":"FRACTAL_NZ","repo_range":{},"repo_seeds":{}})",
864- ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_FRACTAL_NZ, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, true, 0, 0, {16, 32}, {1, 525, 16, 16}, {32, 8400}, {16, 32}, {8400, 16}, {32, 8400}, false, 0, 0, 32, 65617UL,864+ ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_FRACTAL_NZ, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, true, 0, 0, {16, 32}, {1, 525, 16, 16}, {32, 8400}, {16, 32}, {8400, 16}, {32, 8400}, false, 0, 0, 31, 82UL,
865- "32 32 8400 16 32 256 64 32 256 64 16 1 32 1 1 0 0 16908800 0 32 1 0 "865+ "31 32 8400 16 32 272 16 32 272 16 16 1 1 1 1 0 0 33686016 0 32 1 0 "
866 },866 },
867 {867 {
868 "MatMulV3_950_basic_testNZ_aswt", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":true,"transpose_b":false, "offset_x":0, "opImplMode":0},868 "MatMulV3_950_basic_testNZ_aswt", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":true,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -870,8 +870,8 @@ static TilingTestParam ascend950_cases_params[] = {
870 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,870 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,
871 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },871 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
872 "format_a":"ND","format_b":"FRACTAL_NZ","repo_range":{},"repo_seeds":{}})",872 "format_a":"ND","format_b":"FRACTAL_NZ","repo_range":{},"repo_seeds":{}})",
873- ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_FRACTAL_NZ, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {15083, 8906}, {1, 943, 16, 16}, {8906, 2}, {15083, 8906}, {15083, 2}, {8906, 2}, false, 0, 0, 31, 18UL,873+ ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_FRACTAL_NZ, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {15083, 8906}, {1, 943, 16, 16}, {8906, 2}, {15083, 8906}, {15083, 2}, {8906, 2}, false, 0, 0, 32, 18UL,
874- "31 8906 2 15083 288 16 192 288 16 48 15083 1 1 1 1 0 0 16908800 0 288 1 0 "874+ "32 8906 2 15083 192 16 160 192 16 80 15083 2 1 1 1 0 0 33686016 0 192 1 0 "
875 },875 },
876 {876 {
877 "MatMulV3_950_basic_test15", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":true, "offset_x":0, "opImplMode":0},877 "MatMulV3_950_basic_test15", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":true, "offset_x":0, "opImplMode":0},
@@ -907,7 +907,7 @@ static TilingTestParam ascend950_cases_params[] = {
907 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 56, "socVersion": "Ascend950" },907 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 56, "socVersion": "Ascend950" },
908 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",908 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
909 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {4, 8192}, {1280, 8192}, {4, 1280}, {4, 8192}, {1280, 8192}, {4, 1280}, false, 0, 0, 27, 66UL,909 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {4, 8192}, {1280, 8192}, {4, 1280}, {4, 8192}, {1280, 8192}, {4, 1280}, false, 0, 0, 27, 66UL,
910- "27 4 1280 8192 16 48 1344 16 48 336 8192 1 1 1 1 0 0 16908800 0 16 1 0 "910+ "27 4 1280 8192 16 48 512 16 48 256 8192 1 1 1 1 0 0 33686016 0 16 1 0 "
911 },911 },
912 {912 {
913 "MatMulV3_950_basic_test20", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":true,"transpose_b":true, "offset_x":0, "opImplMode":0},913 "MatMulV3_950_basic_test20", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":true,"transpose_b":true, "offset_x":0, "opImplMode":0},
@@ -934,7 +934,7 @@ static TilingTestParam ascend950_cases_params[] = {
934 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },934 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
935 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",935 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
936 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {48, 953}, {3306, 953}, {48, 3306}, {48, 953}, {3306, 953}, {48, 3306}, false, 0, 0, 30, 66UL,936 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {48, 953}, {3306, 953}, {48, 3306}, {48, 953}, {3306, 953}, {48, 3306}, false, 0, 0, 30, 66UL,
937- "30 48 3306 953 48 112 576 48 112 144 953 1 1 1 1 0 0 16908800 0 48 1 0 "937+ "30 48 3306 953 48 112 256 48 112 128 953 1 1 1 1 0 0 33686016 0 48 1 0 "
938 },938 },
939 // {939 // {
940 // "MatMulV3_950_al1_full_load_23", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},940 // "MatMulV3_950_al1_full_load_23", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -951,8 +951,8 @@ static TilingTestParam ascend950_cases_params[] = {
951 "block_dim":{"CORE_NUM":30 ,"vector_core_cnt": 60},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,951 "block_dim":{"CORE_NUM":30 ,"vector_core_cnt": 60},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,
952 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },952 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
953 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",953 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
954- ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {190, 16}, {2130, 16}, {190, 2130}, {190, 16}, {2130, 16}, {190, 2130}, false, 0, 0, 30, 66UL,954+ ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {190, 16}, {2130, 16}, {190, 2130}, {190, 16}, {2130, 16}, {190, 2130}, false, 0, 0, 32, 66UL,
955- "30 190 2130 16 96 144 64 96 144 16 16 1 1 1 1 0 0 16908800 0 96 1 0 "955+ "32 190 2130 16 128 128 16 128 128 16 16 4 4 1 1 0 0 33686016 0 128 1 0 "
956 },956 },
957 {957 {
958 "MatMulV3_950_abl1_full_load_04", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},958 "MatMulV3_950_abl1_full_load_04", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -961,7 +961,7 @@ static TilingTestParam ascend950_cases_params[] = {
961 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },961 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
962 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",962 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
963 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {304, 112}, {3152, 112}, {304, 3152}, {304, 112}, {3152, 112}, {304, 3152}, false, 0, 0, 32, 66UL,963 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {304, 112}, {3152, 112}, {304, 3152}, {304, 112}, {3152, 112}, {304, 3152}, false, 0, 0, 32, 66UL,
964- "32 304 3152 112 160 208 256 160 208 64 112 1 1 1 1 0 0 16843264 0 160 1 0 "964+ "32 304 3152 112 160 208 128 160 208 64 112 1 1 1 1 0 0 33620480 0 160 1 0 "
965 },965 },
966 {966 {
967 "MatMulV3_950_al1_full_load_05", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false},967 "MatMulV3_950_al1_full_load_05", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false},
@@ -970,7 +970,7 @@ static TilingTestParam ascend950_cases_params[] = {
970 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },970 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
971 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",971 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
972 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {4, 8192}, {32000, 8192}, {4, 32000}, {4, 8192}, {32000, 8192}, {4, 32000}, false, 0, 0, 32, 65601UL,972 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {4, 8192}, {32000, 8192}, {4, 32000}, {4, 8192}, {32000, 8192}, {4, 32000}, false, 0, 0, 32, 65601UL,
973- "32 4 32000 8192 16 256 256 16 256 64 8192 1 1 1 1 0 0 16908800 2 16 1 0 "973+ "32 4 32000 8192 16 400 128 16 400 32 8192 1 2 1 1 0 0 33686016 2 16 1 0 "
974 },974 },
975 {975 {
976 "MatMulV3_950_stream_k_black_24", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},976 "MatMulV3_950_stream_k_black_24", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -988,7 +988,7 @@ static TilingTestParam ascend950_cases_params[] = {
988 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },988 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
989 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",989 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
990 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {5120, 821}, {5120, 32}, {821, 32}, {5120, 821}, {5120, 32}, {821, 32}, false, 0, 0, 32, 4114UL,990 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {5120, 821}, {5120, 32}, {821, 32}, {5120, 821}, {5120, 32}, {821, 32}, false, 0, 0, 32, 4114UL,
991- "32 821 32 5120 208 32 256 208 32 64 640 1 1 1 1 0 0 16843264 0 208 1 0 ",ge::DT_FLOAT16, ge::DT_FLOAT16991+ "32 821 32 5120 208 32 128 208 32 64 640 1 1 1 1 0 0 16843264 0 208 1 0 ",ge::DT_FLOAT16, ge::DT_FLOAT16
992 },992 },
993 {993 {
994 "MatMulV3_950_stream_k_fp32_white_26", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},994 "MatMulV3_950_stream_k_fp32_white_26", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -997,7 +997,7 @@ static TilingTestParam ascend950_cases_params[] = {
997 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },997 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
998 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",998 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
999 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, false, {32, 8192}, {8192, 64}, {32, 64}, {32, 8192}, {8192, 64}, {32, 64}, true, 0, 0, 32, 4098UL,999 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, false, {32, 8192}, {8192, 64}, {32, 64}, {32, 8192}, {8192, 64}, {32, 64}, true, 0, 0, 32, 4098UL,
1000- "32 32 64 8192 32 64 512 32 64 128 256 1 1 1 1 0 0 16843264 0 32 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT1000+ "32 32 64 8192 32 64 256 32 64 128 256 1 1 1 1 0 0 16843264 0 32 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT
1001 },1001 },
1002 {1002 {
1003 "MatMulV3_950_stream_k_dpsk_tf32_white_27", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},1003 "MatMulV3_950_stream_k_dpsk_tf32_white_27", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -1033,8 +1033,8 @@ static TilingTestParam ascend950_cases_params[] = {
1033 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,1033 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,
1034 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1034 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1035 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1035 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1036- ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {560, 953}, {80, 953}, {560, 80}, {560, 953}, {80, 953}, {560, 80}, false, 0, 0, 24, 66UL,1036+ ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {560, 953}, {80, 953}, {560, 80}, {560, 953}, {80, 953}, {560, 80}, false, 0, 0, 27, 66UL,
1037- "24 560 80 953 48 48 1344 48 48 336 953 1 1 1 1 0 0 16908800 0 48 1 0 "1037+ "27 560 80 953 64 32 512 64 32 256 953 1 1 1 1 0 0 33686016 0 64 1 0 "
1038 },1038 },
1039 {1039 {
1040 "MatMulV3_950_abl1_full_load_27", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false,"offset_x":0, "opImplMode":0},1040 "MatMulV3_950_abl1_full_load_27", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false,"offset_x":0, "opImplMode":0},
@@ -1042,8 +1042,8 @@ static TilingTestParam ascend950_cases_params[] = {
1042 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,1042 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,
1043 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1043 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1044 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1044 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1045- ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {32, 640}, {32, 480}, {640, 480}, {32, 640}, {32, 480}, {640, 480}, false, 0, 0, 32, 18UL,1045+ ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {32, 640}, {32, 480}, {640, 480}, {32, 640}, {32, 480}, {640, 480}, false, 0, 0, 32, 1048593UL,
1046- "32 640 480 32 80 128 128 80 128 32 32 1 1 1 1 0 0 16908800 0 80 1 0 "1046+ "32 640 480 32 64 128 32 64 128 32 32 1 1 1 1 0 0 33686016 0 64 1 0 "
1047 },1047 },
1048{1048{
1049 "MatMulV3_950_abl1_full_load_28", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},1049 "MatMulV3_950_abl1_full_load_28", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -1052,7 +1052,7 @@ static TilingTestParam ascend950_cases_params[] = {
1052 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1052 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1053 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1053 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1054 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {512, 1024}, {16, 1024}, {512, 1024}, {512, 1024}, {16, 1024}, {512, 1024}, false, 0, 0, 32, 66UL,1054 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {512, 1024}, {16, 1024}, {512, 1024}, {512, 1024}, {16, 1024}, {512, 1024}, false, 0, 0, 32, 66UL,
1055- "32 512 16 1024 16 16 2048 16 16 512 1024 1 1 1 1 0 0 16908800 0 16 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT1055+ "32 512 16 1024 16 16 1024 16 16 512 1024 1 1 1 1 0 0 33686016 0 16 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT
1056 },1056 },
1057 {1057 {
1058 "MatMulV3_950_abl1_full_load_29", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},1058 "MatMulV3_950_abl1_full_load_29", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -1061,7 +1061,7 @@ static TilingTestParam ascend950_cases_params[] = {
1061 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1061 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1062 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1062 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1063 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {300, 560}, {300, 20}, {560, 20}, {300, 560}, {300, 20}, {560, 20}, false, 0, 0, 18, 18UL,1063 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {300, 560}, {300, 20}, {560, 20}, {300, 560}, {300, 20}, {560, 20}, false, 0, 0, 18, 18UL,
1064- "18 560 20 300 32 32 1024 32 32 256 300 1 1 1 1 0 0 16908800 0 32 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT1064+ "18 560 20 300 32 32 512 32 32 256 300 1 1 1 1 0 0 33686016 0 32 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT
1065 },1065 },
1066 {1066 {
1067 "MatMulV3_950_abl1_full_load_31", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},1067 "MatMulV3_950_abl1_full_load_31", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -1070,7 +1070,7 @@ static TilingTestParam ascend950_cases_params[] = {
1070 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1070 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1071 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1071 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1072 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {944, 48}, {80, 48}, {944, 80}, {944, 48}, {80, 48}, {944, 80}, false, 0, 0, 30, 66UL,1072 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {944, 48}, {80, 48}, {944, 80}, {944, 48}, {80, 48}, {944, 80}, false, 0, 0, 30, 66UL,
1073- "30 944 80 48 64 48 192 64 48 48 48 1 1 1 1 0 0 16908800 0 64 1 0 "1073+ "30 944 80 48 32 80 48 32 80 48 48 1 1 1 1 0 0 33686016 0 32 1 0 "
1074 },1074 },
1075 {1075 {
1076 "MatMulV3_950_bl1_full_load_32", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},1076 "MatMulV3_950_bl1_full_load_32", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -1079,7 +1079,7 @@ static TilingTestParam ascend950_cases_params[] = {
1079 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1079 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1080 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1080 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1081 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {1024, 1022}, {1024, 25}, {1022, 25}, {1024, 1022}, {1024, 25}, {1022, 25}, false, 0, 0, 32, 18UL,1081 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, true, false, 0, 0, {1024, 1022}, {1024, 25}, {1022, 25}, {1024, 1022}, {1024, 25}, {1022, 25}, false, 0, 0, 32, 18UL,
1082- "32 1022 25 1024 32 32 1024 32 32 256 1024 1 1 1 1 0 0 16908800 0 32 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT1082+ "32 1022 25 1024 32 32 512 32 32 256 1024 1 1 1 1 0 0 33686016 0 32 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT
1083 },1083 },
1084 {1084 {
1085 "MatMulV3_950_fixpipe_opti_01", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},1085 "MatMulV3_950_fixpipe_opti_01", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false, "offset_x":0, "opImplMode":0},
@@ -1088,7 +1088,7 @@ static TilingTestParam ascend950_cases_params[] = {
1088 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1088 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1089 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1089 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1090 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {1024, 128}, {4090, 128}, {1024, 4090}, {1024, 128}, {4090, 128}, {1024, 4090}, false, 0, 0, 32, 1048641UL,1090 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, true, 0, 0, {1024, 128}, {4090, 128}, {1024, 4090}, {1024, 128}, {4090, 128}, {1024, 4090}, false, 0, 0, 32, 1048641UL,
1091- "32 1024 4090 128 256 256 256 256 256 64 128 1 1 1 1 0 0 16843264 0 256 1 0 "1091+ "32 1024 4090 128 256 256 128 256 256 64 128 1 1 1 1 0 0 16843264 0 256 1 0 "
1092 },1092 },
1093 {1093 {
1094 "MatMulV3_950_fixpipe_opti_02", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false},1094 "MatMulV3_950_fixpipe_opti_02", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false},
@@ -1096,8 +1096,8 @@ static TilingTestParam ascend950_cases_params[] = {
1096 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,1096 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,
1097 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1097 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1098 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1098 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1099- ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, 0, {10256, 32}, {32, 720}, {10256, 720}, {10256, 32}, {32, 720}, {10256, 720}, false, 0, 0, 32, 2097153UL,1099+ ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, 0, {10256, 32}, {32, 720}, {10256, 720}, {10256, 32}, {32, 720}, {10256, 720}, false, 0, 0, 32, 2228225UL,
1100- "32 10256 720 32 256 256 64 256 256 32 32 1 1 15 1 240 0 16843264 0 256 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT1100+ "32 10256 720 32 128 720 32 128 256 32 32 1 1 1 1 0 0 33686528 0 128 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT
1101 },1101 },
1102 {1102 {
1103 "MatMulV3_950_asw_big_k_01", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false},1103 "MatMulV3_950_asw_big_k_01", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false},
@@ -1106,7 +1106,7 @@ static TilingTestParam ascend950_cases_params[] = {
1106 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1106 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1107 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1107 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1108 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, 0, {160, 2080000}, {2080000, 128}, {160, 128}, {160, 2080000}, {2080000, 128}, {160, 128}, false, 0, 0, 20, 1UL,1108 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, 0, {160, 2080000}, {2080000, 128}, {160, 128}, {160, 2080000}, {2080000, 128}, {160, 128}, false, 0, 0, 20, 1UL,
1109- "20 160 128 2080000 32 32 1024 32 32 256 2080000 1 1 1 1 0 0 16908800 0 32 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT1109+ "20 160 128 2080000 32 32 512 32 32 256 2080000 1 1 1 1 0 0 33686016 0 32 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT
1110 },1110 },
1111 // ASWT大于一轮切换基础API1111 // ASWT大于一轮切换基础API
1112 {1112 {
@@ -1115,8 +1115,8 @@ static TilingTestParam ascend950_cases_params[] = {
1115 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,1115 "block_dim":{"CORE_NUM":32, "vector_core_cnt": 64},"corerect_range_flag":null,"dynamic_mode":"dynamic_mkn", "fused_double_operand_num": 0,
1116 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1116 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1117 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1117 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1118- ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, 0, {1188, 64}, {64, 2524}, {1188, 2524}, {1188, 64}, {64, 2524}, {1188, 2524}, false, 0, 0, 32, 2UL,1118+ ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, 0, {1188, 64}, {64, 2524}, {1188, 2524}, {1188, 64}, {64, 2524}, {1188, 2524}, false, 0, 0, 32, 2097153UL,
1119- "32 1188 2524 64 208 256 128 208 256 32 64 1 1 1 1 0 0 16843264 0 208 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT1119+ "32 1188 2524 64 208 256 64 208 256 32 64 1 1 1 1 0 0 33620480 0 208 1 0 ", ge::DT_FLOAT, ge::DT_FLOAT
1120 },1120 },
1121 {1121 {
1122 "MatMulV3_950_matmul_to_mul", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false},1122 "MatMulV3_950_matmul_to_mul", "MatMulV3", R"({"_pattern": "MatMul", "attrs":{"transpose_a":false,"transpose_b":false},
@@ -1144,7 +1144,7 @@ static TilingTestParam ascend950_cases_params[] = {
1144 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },1144 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "vector_core_cnt": 64, "socVersion": "Ascend950" },
1145 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",1145 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
1146 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, 0, {1, 9398}, {9398, 135021}, {1, 135021}, {1, 9398}, {9398, 135021}, {1, 135021}, false, 0, 0, 32, 65537UL,1146 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, 0, {1, 9398}, {9398, 135021}, {1, 135021}, {1, 9398}, {9398, 135021}, {1, 135021}, false, 0, 0, 32, 65537UL,
1147- "32 1 135021 9398 16 256 128 16 256 64 9398 1 2 1 1 0 0 16908800 0 16 1 0 ",1147+ "32 1 135021 9398 16 512 64 16 512 32 9398 1 4 1 1 0 0 33686016 0 16 1 0 ",
1148 DT_FLOAT16, DT_FLOAT16, {}, {}, {}, true, ge::FORMAT_ND, ge::FORMAT_ND, {135021}, {135021}, DT_FLOAT161148 DT_FLOAT16, DT_FLOAT16, {}, {}, {}, true, ge::FORMAT_ND, ge::FORMAT_ND, {135021}, {135021}, DT_FLOAT16
1149 },1149 },
1150 {1150 {
@@ -2772,7 +2772,7 @@ TEST_F(MatMulV3TilingRuntime, 950_slice_non_contiguous_case) {
2772 string case_name = "950_slice_non_contiguous_case";2772 string case_name = "950_slice_non_contiguous_case";
2773 auto tiling_data_result = TilingData2Str(tiling_context->GetRawTilingData(), case_name, tiling_key);2773 auto tiling_data_result = TilingData2Str(tiling_context->GetRawTilingData(), case_name, tiling_key);
2774 auto golden_tiling_data = GenGoldenTilingData(2774 auto golden_tiling_data = GenGoldenTilingData(
2775- "1 10 4 7 16 16 64 16 16 16 7 1 1 1 1 0 0 16908800 0 2 0 0", case_name, tiling_key);2775+ "1 10 4 7 16 16 16 16 16 16 7 1 1 1 1 0 0 33686016 0 2 0 0", case_name, tiling_key);
2776 cout << "===== 950_slice_non_contiguous_case:" << tiling_key << " === \n" << tiling_data_result << std::endl;2776 cout << "===== 950_slice_non_contiguous_case:" << tiling_key << " === \n" << tiling_data_result << std::endl;
2777 ASSERT_EQ(tiling_key, 1);2777 ASSERT_EQ(tiling_key, 1);
2778 ASSERT_EQ(block_dim, 1);2778 ASSERT_EQ(block_dim, 1);
Mmatmul/quant_batch_matmul_v3/tests/ut/op_host/test_quant_batch_matmul_v3_tiling.cpp+1-0
@@ -761,6 +761,7 @@ static void ThreadFunc(const QuantBatchMatmulV3TilingTestParam *params, size_t t
761 lock_guard<mutex> lock(tilingTestMutex);761 lock_guard<mutex> lock(tilingTestMutex);
762 params[idx].Test();762 params[idx].Test();
763 } else {763 } else {
764+ lock_guard<mutex> lock(tilingTestMutex);
764 params[idx].Test();765 params[idx].Test();
765 }766 }
766 }767 }
Mmatmul/transpose_batch_mat_mul/tests/ut/op_host/test_transpose_batch_mat_mul_tiling.cpp+1-1
@@ -312,7 +312,7 @@ static TilingTestParam ascend950_cases_params[] = {
312 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "socVersion": "Ascend950" },312 "hardware_info": {"BT_SIZE": 4096, "load3d_constraints": "unknown", "Intrinsic_fix_pipe_l0c2out": true, "Intrinsic_data_move_l12ub": false, "Intrinsic_data_move_l0c2ub": false, "Intrinsic_data_move_l12bt": true, "Intrinsic_data_move_out2l1_nd2nz": true, "UB_SIZE": 253952, "L2_SIZE": 134217728, "L1_SIZE": 524288, "L0A_SIZE": 65536, "L0B_SIZE": 65536, "L0C_SIZE": 262144, "CORE_NUM": 32, "socVersion": "Ascend950" },
313 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",313 "format_a":"ND","format_b":"ND","repo_range":{},"repo_seeds":{}})",
314 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, false, {1, 4, 4096}, {4, 4096, 1024}, {1, 4, 1024}, false, 0, 0, 32, 1UL,314 ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, ge::FORMAT_ND, false, false, 0, false, {1, 4, 4096}, {4, 4096, 1024}, {1, 4, 1024}, false, 0, 0, 32, 1UL,
315- "32 1 1024 4096 4096 16 128 4096 16 128 128 64 8 1 1 0 0 0 0 393216 16384 0 1 1 1 1 32 4 0 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 4 0 4 4 4 1 1 1 1 1 1 1 1 1 1 4 4 4 0 1 1 16 128 512 258 16 1 0 ",315+ "32 1 1024 4096 4096 16 128 4096 16 128 128 4 4 1 1 0 0 0 0 393216 16384 0 1 1 1 1 2 2 0 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 4 0 4 4 4 1 1 1 1 1 1 1 1 1 1 4 4 4 0 1 1 16 128 256 258 16 1 0 ",
316 {1, 0, 2}, {0, 1, 2}, {1, 0, 2}, 1316 {1, 0, 2}, {0, 1, 2}, {1, 0, 2}, 1
317 }317 }
318};318};