fix: conv3d dx 1x1 bias kernelsplit-ops-nn-AtomGit

Mconv/conv3d_backprop_input_v2/op_host/op_tiling/arch35/conv3d_backprop_input_v2_kernel_split_tiling.cpp+0-4

	@@ -149,10 +149,6 @@ void Conv3DDXV2KernelSplitTiling::SetParamForKernelSplit(bool isKernelSplitOnlyH
149		149
150	bool Conv3DDXV2KernelSplitTiling::CheckKernelSplitHW11Enable()	150	bool Conv3DDXV2KernelSplitTiling::CheckKernelSplitHW11Enable()
151	{	151	{
152	- // 有 bias 场景暂不支持 1*1 kernel 拆分
153	- if (hasBiasFlag_) {
154	- return false;
155	- }
156	uint64_t mValueForCheck = static_cast<uint64_t>(runInfo_.dedx_h) * runInfo_.dedx_w;	152	uint64_t mValueForCheck = static_cast<uint64_t>(runInfo_.dedx_h) * runInfo_.dedx_w;
157	uint64_t nValueForCheck = static_cast<uint64_t>(runInfo_.dedx_cin1_g) * BLOCK_CUBE;	153	uint64_t nValueForCheck = static_cast<uint64_t>(runInfo_.dedx_cin1_g) * BLOCK_CUBE;
158	uint64_t kValueForCheck = runInfo_.dedy_cout1_g * BASIC_BLOCK_SIZE_32 / dtypeByteL0b_;	154	uint64_t kValueForCheck = runInfo_.dedy_cout1_g * BASIC_BLOCK_SIZE_32 / dtypeByteL0b_;

Mconv/conv3d_backprop_input_v2/op_kernel/arch35/convolution_3d_backprop/conv3d_bp_func_arch35.h+13-8

	@@ -967,18 +967,23 @@ template <class Intf>
967	static __aicore__ inline bool ProcessKernelSplitIteration(Intf* self, bool hasBias)	967	static __aicore__ inline bool ProcessKernelSplitIteration(Intf* self, bool hasBias)
968	{	968	{
969	if constexpr (Intf::conv3dConfig.kernelSplitMode == TPL_SPLIT_KERNEL_HW) {	969	if constexpr (Intf::conv3dConfig.kernelSplitMode == TPL_SPLIT_KERNEL_HW) {
		Y Y yuxin519 天前减少一下分支的深度，比如把if constexpr (Intf::conv3dConfig.kernelSplitMode != TPL_SPLIT_KERNEL_HW) {return false;} H hexinhui 15 天前评论： 15 天前评论：
970	- if (IterateForKernelSplit<Intf>(self)) {	970	+ if (!IterateForKernelSplit<Intf>(self)) {
971	- UpdateFullLoadL1Status<Intf>(self);	971	+ return false;
972	- if (unlikely(self->ctx.tiling_->hk == 1)) {	972	+ }
973	- return true;	973	+ UpdateFullLoadL1Status<Intf>(self);
974	- }	974	+ if (unlikely(self->ctx.tiling_->hk == 1)) {
975	- if (unlikely(hasBias)) {	975	+ if (unlikely(hasBias && self->ctx.needComputeFlag_)) {
		976	+ self->ctx.needComputeFlag_ = false;
976	Compute<Intf, true>(self);	977	Compute<Intf, true>(self);
977	- } else {
978	- Compute<Intf, false>(self);
979	}	978	}
980	return true;	979	return true;
981	}	980	}
		981	+ if (unlikely(hasBias)) {
		982	+ Compute<Intf, true>(self);
		983	+ } else {
		984	+ Compute<Intf, false>(self);
		985	+ }
		986	+ return true;
982	}	987	}
983	return false;	988	return false;
984	}	989	}

Mconv/conv3d_backprop_input_v2/op_kernel/arch35/convolution_3d_backprop/conv3d_bp_kernel_split_func.h+2-2

	@@ -401,14 +401,14 @@ struct IterateAllForKernelSplit {
401	const uint32_t lastRearrangeW = self->ctx.tiling_->strideW - 1;	401	const uint32_t lastRearrangeW = self->ctx.tiling_->strideW - 1;
402	bool hasBias = self->ctx.hasBias_;	402	bool hasBias = self->ctx.hasBias_;
403	while (self->template Iterate<sync>(false, hasBias)) {	403	while (self->template Iterate<sync>(false, hasBias)) {
404	- if (unlikely(isKernel1x1 && self->ctx.rearrangeHIndex_ != 0)) {	404	+ if (unlikely(isKernel1x1 && !hasBias && self->ctx.rearrangeHIndex_ != 0)) {
405	continue;	405	continue;
406	}	406	}
407	if ASCEND_IS_AIC_SCALAR {	407	if ASCEND_IS_AIC_SCALAR {
408	if (self->ctx.rearrangeWIndex_ == 0) {	408	if (self->ctx.rearrangeWIndex_ == 0) {
409	CrossCoreCWaitVForKS<Intf>(self);	409	CrossCoreCWaitVForKS<Intf>(self);
410	}	410	}
411	- if (!isKernel1x1 \|\| self->ctx.rearrangeWIndex_ == 0) {	411	+ if (!isKernel1x1 \|\| hasBias \|\| self->ctx.rearrangeWIndex_ == 0) {
412	self->template GetTensorC<sync>(output, enAtomic);	412	self->template GetTensorC<sync>(output, enAtomic);
413	}	413	}
414	if (self->ctx.rearrangeWIndex_ == lastRearrangeW) {	414	if (self->ctx.rearrangeWIndex_ == lastRearrangeW) {

Mconv/conv3d_backprop_input_v2/op_kernel/arch35/convolution_3d_backprop/impl/conv_bp_input_sub_func_kernelsplit_hw.h+2-2

	@@ -276,7 +276,7 @@ __aicore__ inline void InterleaveUbOutForKernelSplit(Intf* self, int64_t dataLen
276	uint32_t doubleVfLen = (vfLen << crossBlockNum);	276	uint32_t doubleVfLen = (vfLen << crossBlockNum);
277	uint16_t repeatTimes = (dataLen + vfLen - 1) / vfLen;	277	uint16_t repeatTimes = (dataLen + vfLen - 1) / vfLen;
278	uint64_t twoBlockLen = (dataLen << crossBlockNum);	278	uint64_t twoBlockLen = (dataLen << crossBlockNum);
279	- bool kernelFlag1 = (self->ctx.tiling_->wk == 1 && self->ctx.tiling_->hk == 1);	279	+ bool kernelFlag1 = (self->ctx.tiling_->wk == 1 && self->ctx.tiling_->hk == 1 && !self->ctx.hasBias_);
280	auto src0Ptr = (__ubuf__ ReDstT*)self->ctx.vecOutBuf_[0].GetPhyAddr();	280	auto src0Ptr = (__ubuf__ ReDstT*)self->ctx.vecOutBuf_[0].GetPhyAddr();
281	auto src1Ptr = (__ubuf__ ReDstT*)self->ctx.vecOutBuf_[dataLen].GetPhyAddr();	281	auto src1Ptr = (__ubuf__ ReDstT*)self->ctx.vecOutBuf_[dataLen].GetPhyAddr();
282	auto dst0Ptr = (__ubuf__ ReDstT*)self->ctx.vecOutBuf_[twoBlockLen].GetPhyAddr();	282	auto dst0Ptr = (__ubuf__ ReDstT*)self->ctx.vecOutBuf_[twoBlockLen].GetPhyAddr();
	@@ -320,7 +320,7 @@ __aicore__ inline void LoadWorkSpaceDataToUb(Intf* self, const int64_t hwSize, c
320	mte2Param.srcStride = 0;	320	mte2Param.srcStride = 0;
321	mte2Param.dstStride = 0;	321	mte2Param.dstStride = 0;
322	LoadWorkSpaceDataToUbInner(self, srcOffset, 0, mte2Param);	322	LoadWorkSpaceDataToUbInner(self, srcOffset, 0, mte2Param);
323	- if (self->ctx.tiling_->wk != 1 \|\| self->ctx.tiling_->hk != 1) { // kernel=1*1 只需要搬一块	323	+ if (self->ctx.tiling_->wk != 1 \|\| self->ctx.tiling_->hk != 1 \|\| self->ctx.hasBias_) { // kernel=1*1 只需要搬一块
324	srcOffset += hwSize * self->ctx.baseUseN_;	324	srcOffset += hwSize * self->ctx.baseUseN_;
325	int64_t dstOffset = hwSize * curUseN;	325	int64_t dstOffset = hwSize * curUseN;
326	LoadWorkSpaceDataToUbInner(self, srcOffset, dstOffset, mte2Param);	326	LoadWorkSpaceDataToUbInner(self, srcOffset, dstOffset, mte2Param);